# A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

^{*}

## Abstract

**:**

_{REF}

^{2}switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

## 1. Introduction

- A common mode-based monotonic charge recovery (CMMC) technique for switching is proposed to optimize the switching energy of capacitive DAC. The proposed technique of the SAR ADC employs a common mode based monotonic charge recovery switching scheme, which has the advantage of the regular V
_{CM}based switching scheme, resulting in reduction of the switching energy. - A self-comparator clock generator circuit controlled by asynchronous SAR logic is implemented with a modified dynamic latch comparator to eliminate the necessity of an external clock and power optimization of the comparator.

## 2. The Proposed ADC Architecture

_{REF}

^{2}switching energy is consumed by the proposed CMMC switching technique.

## 3. Circuit Implementation

#### 3.1. Bootstrap Switching

_{IN}for NMOS switches, and constant overdrive voltage is achieved through bootstrap switching. The implemented boostrap switching schematic is shown in Figure 4. When CLK

_{SAM}is low in the hold phase, capacitor C

_{1}is charged to VDD with M1 and M4. When CLK

_{SAM}is high in the tracking phase, the input voltage V

_{IN}is connected to the bottom plate V

_{B}through M8, and the boosted voltage V

_{T}is connected to the gate of sampling switch M9 through M3. Transistor M6 is initially used to turn on M3. Since M6 is turned off if V

_{IN}is higher than VDD—V

_{th,n}, Transistor M7 is included to ensure that M3 stays on while V

_{B}is charged to V

_{IN}. When CLK

_{SAM}goes low, M3 is turned off with M5, and V

_{g}is discharged through M2 and NMOS of the inverter. Transistor M2 protects the inverter MOSFETs from the boosted voltage V

_{g}during the tracking phase.

#### 3.2. CDAC

_{CM}while the top plate is connected to the input signal, V

_{IN}. After sampling, without consuming any energy from the capacitor array, the first signed bit can be immediately determined. The next bit cycle either charges the capacitor from V

_{CM}to V

_{REFT}or discharges the capacitor from V

_{CM}to V

_{REFB}, depending upon the first comparison bit value.

^{n−1}capacitors for the n-bit ADC, while a conventional ADC requires 2

^{n}capacitors [24], which is half of the conventional ADCs.

_{REF}, towards the top or bottom half of the CDAC, in the monotonic switching.

_{REF}− V

_{CM}= (1/2)V

_{CM}on both the top and bottom half of the DAC. The energy consumption is proportional to CV

^{2}and the energy consumption of the monotonic switching is proportional to CV

_{REF}

^{2}, hence, the energy consumption of the proposed CMMC switching is proportional to 2C(V

_{REF}/2)

^{2}= (1/2)CV

_{REF}

^{2}. As we can conclude that, the proposed CMMC switching algorithm is more energy efficient as compared to the monotonic switching algorithm. The common-mode voltage V

_{CM}of the DAC in the proposed CMMC switching algorithm does not change as compared to the monotonic switching algorithm, this improves the static performance of the ADC and it simplifies the designing of the comparator for ADC. The switching energy of the proposed switching architecture in each stage is represented in Figure 5. The CMMC switching algorithm consumes far less energy as compared to the conventional implementation. For 10-bit case, 63.75 CV

_{REF}

^{2}switching energy is consumed by the proposed CMMC switching technique. The fast Fourier transform (FFT) spectrum of the behavioral simulation is done in MATLAB

^{®}for the proposed switching architecture with 1% unit capacitor mismatch as shown in Figure 6. The static performance integral non-linearity (INL) and differential non-linearity (DNL) of the proposed switching with 1% unit capacitor mismatch, as shown in Figure 7.

#### 3.3. Dynamic Latch Comparator

## 4. Measurement Results

## 5. Conclusions

_{REF}

^{2}energy for 10-bit operation. Additionally, a dynamic latch comparator with self-comparator clock generating circuit has been implemented to carry out the power optimized operation and good resolution. Comparator clock generator circuit is controlled by asynchronous SAR logic to adjust the settling time of the MSB and LSB bits. The proposed prototype of the SAR ADC is realized in 55 nm CMOS technology. The proposed architecture achieves a FOM of 17.3 fJ/conv-step with the ENOB of 9.74 bits and SNDR of 60.39 dB at measurement level when operating at 1 MS/s with a 1 V supply.

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

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**Figure 6.**FFT spectrum of the behavioral simulation result of proposed switching with 1% unit capacitor mismatch.

**Figure 7.**Static performance of proposed switching with 1% unit capacitor mismatch. (

**a**) Integral non-linearity (INL). (

**b**) Differential non-linearity (DNL).

**Figure 11.**Measured FFT spectrum for different input frequencies with the sampling speed of 1 MS/s (

**a**) for an input frequency of 250.97 kHz; and (

**b**) for an input frequency of 450.19 kHz.

**Figure 12.**Measured static performance parameter (

**a**) integral non-linearity (INL), and (

**b**) differential non-linearity (DNL) results.

Parameter | [10] | [11] | [21] | [22] | [23] | This Work |
---|---|---|---|---|---|---|

Process (nm) | 40 | 130 | 180 | 55 | 180 | 55 |

Resolution (bits) | 12 | 10 | 8 | 12 | 10 | 10 |

Sampling Rate (MS/s) | 1 | 1 | 1 | 1 | 1 | 1 |

Supply Voltage (V) | 1.1 | 0.8 | 1.8 | 0.9 | 1.2 | 1 |

SNDR (dB) | 68.1 | - | 45.3 | 68 | - | 60.39 |

ENOB (bits) | - | 8.8 | 7.23 | - | 8.7 | 9.74 |

DNL (LSB) | - | −0.33/0.56 | 0.66 | −0.58/0.60 | 0.4 | −0.5/0.7 |

INL (LSB) | −1.8/1.0 | −0.61/0.55 | 0.61 | −0.81/0.58 | 0.46 | −0.7/0.6 |

Power Consumption (µW) | 31.1 | 9 | 10.3 | 30 | 34.6 | 14.8 |

FOM (fJ/conv. Step) | 15.0 | 27 | 67 | 24.5 | 83 | 17.3 |

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**MDPI and ACS Style**

Verma, D.; Shehzad, K.; Khan, D.; Kim, S.J.; Pu, Y.G.; Yoo, S.-S.; Hwang, K.C.; Yang, Y.; Lee, K.-Y.
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application. *Electronics* **2020**, *9*, 1100.
https://doi.org/10.3390/electronics9071100

**AMA Style**

Verma D, Shehzad K, Khan D, Kim SJ, Pu YG, Yoo S-S, Hwang KC, Yang Y, Lee K-Y.
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application. *Electronics*. 2020; 9(7):1100.
https://doi.org/10.3390/electronics9071100

**Chicago/Turabian Style**

Verma, Deeksha, Khuram Shehzad, Danial Khan, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, and Kang-Yoon Lee.
2020. "A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application" *Electronics* 9, no. 7: 1100.
https://doi.org/10.3390/electronics9071100