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Article

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

by 1,2
1
Department of Electronics Engineering, Chang Gung University, Taoyuan City 330, Taiwan
2
Department of Radiation Oncology, Chang Gung Memorial Hospital-LinKou, Taoyuan City 330, Taiwan
Electronics 2020, 9(4), 607; https://doi.org/10.3390/electronics9040607
Received: 10 March 2020 / Revised: 26 March 2020 / Accepted: 1 April 2020 / Published: 3 April 2020
This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation. View Full-Text
Keywords: field-programmable gate array (FPGA); time-to-digital converter (TDC); triple modular redundancy (TMR); dual-mode; run-time calibration; differential non-linearity (DNL) field-programmable gate array (FPGA); time-to-digital converter (TDC); triple modular redundancy (TMR); dual-mode; run-time calibration; differential non-linearity (DNL)
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MDPI and ACS Style

Chen, Y.-H. Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme. Electronics 2020, 9, 607. https://doi.org/10.3390/electronics9040607

AMA Style

Chen Y-H. Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme. Electronics. 2020; 9(4):607. https://doi.org/10.3390/electronics9040607

Chicago/Turabian Style

Chen, Yuan-Ho. 2020. "Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme" Electronics 9, no. 4: 607. https://doi.org/10.3390/electronics9040607

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