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Reducing the Overhead of BCH Codes: New Double Error Correction Codes

Institute of Information and Communication Technologies (ITACA), Universitat Politècnica de València, Camino de Vera s/n, 46022 Valencia, Spain
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Electronics 2020, 9(11), 1897; https://doi.org/10.3390/electronics9111897
Received: 15 October 2020 / Revised: 4 November 2020 / Accepted: 7 November 2020 / Published: 11 November 2020
(This article belongs to the Section Computer Science & Engineering)
The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors. View Full-Text
Keywords: reliability; fault tolerance; error control codes; double error correction; BCH codes reliability; fault tolerance; error control codes; double error correction; BCH codes
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MDPI and ACS Style

Saiz-Adalid, L.-J.; Gracia-Morán, J.; Gil-Tomás, D.; Baraza-Calvo, J.-C.; Gil-Vicente, P.-J. Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics 2020, 9, 1897. https://doi.org/10.3390/electronics9111897

AMA Style

Saiz-Adalid L-J, Gracia-Morán J, Gil-Tomás D, Baraza-Calvo J-C, Gil-Vicente P-J. Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics. 2020; 9(11):1897. https://doi.org/10.3390/electronics9111897

Chicago/Turabian Style

Saiz-Adalid, Luis-J., Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo, and Pedro-J. Gil-Vicente 2020. "Reducing the Overhead of BCH Codes: New Double Error Correction Codes" Electronics 9, no. 11: 1897. https://doi.org/10.3390/electronics9111897

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