Next Article in Journal
High Speed Back-Bias Voltage (VBB) Generator with Improved Pumping Current
Next Article in Special Issue
Multiclass ECG Signal Analysis Using Global Average-Based 2-D Convolutional Neural Network Modeling
Previous Article in Journal
A Low-Cost Current Sensor Based on Semi-Cylindrical Magnetostrictive Composite
Previous Article in Special Issue
Blind Source Separation for the Aggregation of Machine Learning Algorithms: An Arrhythmia Classification Case
Article

An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface

1
Department of Electrical Engineering, City University of Hong Kong, Kowloon, Hong Kong, China
2
Department of Electrical and Electronic Engineering, Chittagong University of Engineering & Technology, Chittagong 4349, Bangladesh
3
Department of Biomedical Engineering, University of Southern California, Los Angeles, CA 90089, USA
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(11), 1834; https://doi.org/10.3390/electronics9111834
Received: 7 October 2020 / Revised: 28 October 2020 / Accepted: 30 October 2020 / Published: 3 November 2020
(This article belongs to the Special Issue Biomedical Signal Processing)
As computational and functional brain model development are solely dependent upon the data acquired from the neural interface, this device plays a vital role in both prosthetic developments and neurological experiments. A wireless neural interface is preferred over a traditional wired one because it can maximize the comfort of the subject and ensure the freedom of movement while implemented. This paper describes the field programmable gate array (FPGA) prototype design of a low-power multichannel neuron activity extraction unit suitable for a wireless neural interface. To achieve the low-power requirement, we proposed a novel neural signal extraction algorithm which can provide an up to 6000X transmission rate reduction considering the input signal. Consequently, this technique offers at least 2X power reduction compared to the state-of-the-art systems. We implemented this scheme in Xilinx Zynq-7000 FPGA, which can be used as an intermediate transition towards the application specific integrated circuit (ASIC) design for on-chip neural signal processing. The proposed FPGA prototype offers reconfigurable computability, which means the model can be modified and verified according to prerequisites before the final ASIC design. This prototype consists of a signal filtering unit and a signal extraction unit which can be used either as stand-alone units or combined as a complete system. Our proposed scheme also provides a provision to work as a single-channel or a scalable multichannel interface based on user’s demands. We collected practical neural signals from rat brains and validated the efficacy of the implemented system using in-silico signal processing. View Full-Text
Keywords: FPGA; signal processing; neural signal extraction FPGA; signal processing; neural signal extraction
Show Figures

Figure 1

MDPI and ACS Style

Chowdhury, M.H.; Elyahoodayan, S.; Song, D.; Cheung , R.C.C. An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface. Electronics 2020, 9, 1834. https://doi.org/10.3390/electronics9111834

AMA Style

Chowdhury MH, Elyahoodayan S, Song D, Cheung  RCC. An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface. Electronics. 2020; 9(11):1834. https://doi.org/10.3390/electronics9111834

Chicago/Turabian Style

Chowdhury, Mehdi H., Sahar Elyahoodayan, Dong Song, and Ray C.C. Cheung . 2020. "An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface" Electronics 9, no. 11: 1834. https://doi.org/10.3390/electronics9111834

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop