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Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal Layers

1
Foundry Division, Samsung Electronics Co. Ltd, Hwaseong 18448, Korea
2
Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon 16419, Korea
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(11), 1274; https://doi.org/10.3390/electronics8111274
Received: 11 October 2019 / Revised: 27 October 2019 / Accepted: 29 October 2019 / Published: 1 November 2019
(This article belongs to the Section Semiconductor Devices)
Air-gap (AG) technology on back-end-of-line (BEOL) provides a means to improve performance without area or power degradation. However, the “blind” use of AG based on traditional design methodologies does not provide sufficient performance gain. We developed an AG-aware design methodology to maximize performance gain with minimum cost. The experimental results of the proposed methodology, which was tested using a 10 nm Advanced RISC Machine (ARM) Cortex-A9 quad-core central processing unit (CPU), indicated a performance gain of 6.1–8.4% compared with traditional AG design. The performance gain achieved represents about half of the 10–15% performance improvement under the same power by a process node shrink. A Si process of consecutive double AG layers was developed by overcoming various process challenges, such as AG depth control, Cu/ultra-low-k damage, the hermetic AG liner, and step-height control above the AG. Furthermore, the capacitance was reduced by 17.0%, which satisfied the target goal in the simulation stage for the assumed structure. The optimized integration process was validated according to the function yield of the CPU, which was comparable to that of a non-AG process. The time-dependent dielectric breakdown and electromigration lifetime of the AG wire satisfied the 10-year criteria, and the assembly yield was verified.
Keywords: air gap; dielectric; CPU performance; BEOL; physical design; interconnect capacitance air gap; dielectric; CPU performance; BEOL; physical design; interconnect capacitance
MDPI and ACS Style

Ryu, S.; Cho, Y.; Han, T.H. Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal Layers. Electronics 2019, 8, 1274.

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