# Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation

^{*}

## Abstract

**:**

## 1. Introduction

_{θ}is bounded by the expression in Equation (1), which depends on the number of iterations n. This means that ideally we can reduce the angle computation error using more iterations of the CORDIC algorithm.

^{−1}function in Equation (2), then the error bound depends mainly on the number of iterations. Due to the quantization in the data paths of the fixed-point implementation, every loop of the algorithm has a truncation error that accumulates itself. This is the meaning of the terms $\left(n-1\right)$ and $n\delta $ in Equation (2). Particularly, the latter can lead to an increase of the error upper bound in each iteration. Instead, the ${2}^{-n\text{}+\text{}1}$ term indicates the improvement of the error due to more iterations. An example of the dependence of the error upper bound on the number n, once the parameters ε, r and δ are fixed, will be shown in Section 3. It must be noted that Equation (2) expresses an upper bound to the error, and not the real error (see the difference between the red lines and blue lines in Figures 6–9 in Section 3).

^{−1}term in Equation (2). The idea proposed in this work is to have a fast estimation of the magnitude of the initial vector and to design a circuit able to magnify the coordinates to let the standard atan-CORDIC work in the area where the phase error is small.

## 2. Fast Magnitude Estimator and Improved CORDIC Architecture

## 3. Computation Accuracy Evaluation

## 4. VLSI Implementation and Characterization

^{−5}rad with an optimized algorithm. At 60 MHz with 180 nm 1.8 V CMOS technology, the ARM7-TDMIs has a power consumption of about 24 mW. Although [8] is optimized to achieve a lower error, 2.42 × 10

^{−5}rad vs. 6.14 × 10

^{3}rad in our implementation, with K = 12, the proposed design outperforms the design in [8] in terms of the reduced processing time, by a factor ×124, the reduced power consumption, by a factor ×31, and the reduced circuit complexity, by a factor ×9.5 . To achieve a similar calculation accuracy as in [8], our IP has been re-synthetized with K = 20. In such a case, the processing time is still within 1 µs and the complexity in the logic gates is still below 4 kgates.

^{2}[18]. The N-MOS supplied at 1.8 V has a voltage threshold of 0.35 mV and a current capability of 600 µA/µm

^{2}. The P-MOS supplied at 1.8 V has a voltage threshold of 0.42 mV and a current capability of 260 µA/µm

^{2}.

## 5. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

## References

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**Figure 6.**Standard atan-CORDIC phase error of x = 16 and y. The red line is the coarse upper-bound error evaluated with Equation (2); the blue trace is the standard atan-CORDIC phase error.

**Figure 7.**Improved atan-CORDIC phase error of x = 16 and y. The red line is the coarse upper-bound error evaluated with Equation (2); the blue trace is the standard atan-CORDIC phase error.

**Figure 8.**Standard atan-CORDIC max phase error on all the input space. The red line is the coarse upper-bound error evaluated with Equation (2); the blue trace is the standard atan-CORDIC phase error.

**Figure 9.**Improved atan-CORDIC max phase error on all the input space. The red line is the coarse upper-bound error evaluated with Equation (2); the blue trace is the standard atan-CORDIC phase error.

**Table 1.**Max angle error expressed in LSB of the standard (std) vs. the proposed (our) CORDIC, K = 12, 12 iterations from 0 to 11, bits for x and y from 10 to 14, M areas from 6 to 9.

M Areas | ||||||||
---|---|---|---|---|---|---|---|---|

6 | 7 | 8 | 9 | |||||

x, y Bits | std | our | std | our | std | our | std | our |

10 | 414 | 50 | 414 | 16 | 414 | 16 | 414 | 16 |

11 | 414 | 50 | 414 | 13 | 414 | 10 | 414 | 10 |

12 | 414 | 50 | 414 | 13 | 414 | 10 | 414 | 6 |

13 | 414 | 50 | 414 | 13 | 414 | 10 | 414 | 4 |

14 | 414 | 50 | 414 | 13 | 414 | 10 | 414 | 4 |

**Table 2.**Max angle error expressed in LSB of the standard (std) vs. the proposed (our) CORDIC, K = 12, nine iterations from 0 to 8, bits for x and y from 10 to 14, M-areas from 6 to 9.

M areas | ||||||||
---|---|---|---|---|---|---|---|---|

6 | 7 | 8 | 9 | |||||

x, y Bits | std | our | std | our | std | our | std | our |

10 | 410 | 45 | 410 | 15 | 410 | 15 | 410 | 15 |

11 | 410 | 45 | 410 | 10 | 410 | 10 | 410 | 10 |

12 | 410 | 45 | 410 | 9 | 410 | 9 | 410 | 8 |

13 | 410 | 45 | 410 | 9 | 410 | 9 | 410 | 7 |

14 | 410 | 45 | 410 | 9 | 410 | 9 | 410 | 7 |

**Table 3.**Max angle error expressed in LSB of the standard vs. proposed CORDIC (K = 12, 12 bits for x and y data paths, six M areas).

Max. Number of Iterations | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|

2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | |

Standard CORDIC | 512 | 302 | 252 | 333 | 374 | 394 | 404 | 409 | 412 | 413 | 414 |

Proposed CORDIC | 512 | 302 | 160 | 82 | 43 | 30 | 40 | 45 | 48 | 49 | 50 |

IP macrocell | Standard CORDIC | This work | [6] | [8] |
---|---|---|---|---|

Equivalent gates | 1400 | 1700 (1900 pipelined) | 8000 | 18,000 + 32kB RAM + 512 kB E2PROM |

Clock frequency, MHz | 46 | 30 (46 pipelined) | 10 | 60 |

Max. angle error | 0.6355 rad | 6.1 × 10^{−3} rad | N/A (K = 16, n = 20) | 2.42 × 10^{−5} rad |

Processing latency, µs | 0.28 | 0.4 (0.28 pipelined) | N/A | 35 |

Power consumption, mW | 0.57 | 0.45 (0.77 pipelined) | N/A | 24 |

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**MDPI and ACS Style**

Pilato, L.; Fanucci, L.; Saponara, S.
Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation. *Electronics* **2017**, *6*, 22.
https://doi.org/10.3390/electronics6010022

**AMA Style**

Pilato L, Fanucci L, Saponara S.
Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation. *Electronics*. 2017; 6(1):22.
https://doi.org/10.3390/electronics6010022

**Chicago/Turabian Style**

Pilato, Luca, Luca Fanucci, and Sergio Saponara.
2017. "Real-Time and High-Accuracy Arctangent Computation Using CORDIC and Fast Magnitude Estimation" *Electronics* 6, no. 1: 22.
https://doi.org/10.3390/electronics6010022