Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics
Abstract
:1. Introduction
2. Approaches for Making Flexible Devices
2.1. The All-Organic Approach
2.2. The Hybrid Systems Approach
2.3. Spalling Technology
2.4. The Complementary Transfer-free Inorganic Approach
3. NVM Operational Principles and Architectures
3.1. NVM Operational Principles
NVM Type | Operation Principle | Flexed | ||
---|---|---|---|---|
ReRAM (Memristor) | A resistive oxide is sandwiched between two metallic layers. The resistance of the oxide changes with applied “set” and “reset” voltage pulses. A high-resistance state corresponds to “0” and a low-resistance state corresponds to “1”. | Yes | ||
FeRAM | A ferroelectric material has two possible polarization states inherent from its crystalline structure. Applying write/erase voltage pulse switches for positive to negative polarization states, corresponding to “0” or “1”. | Yes | ||
MRAM | Spintronic devices such as magnetic tunneling junctions are composed of a fixed (“pinned”) magnetic moment layer, a tunneling barrier (oxide), and a free layer. Current flowing in nearby lines is expected to magnetize the free layer. If the free layer magnetic moment is parallel to that of the pinned layer, the device is “ON” and the resistance across the structure is low. If the free layer is magnetized such that its magnetic moment is anti-parallel to the pinned layer, the device is “OFF” and the structure will be in high-resistance state. | No | ||
PCRAM | Current or laser pulses are applied to change the phase of a material from crystalline (low resistance) to amorphous (high resistance) and vice versa at a localized space, which changes the material’s electrical and optical properties. Short pulses above the melting temperature are needed to make the change from the crystalline to the amorphous phase, while longer pulses below the melting temperature are required to restore the crystalline order of the material. | Yes | ||
Flash | FG | FG flash has the same structure as a field effect transistor (FET) except that its gate dielectric is split into three layers. The first is tunneling oxide, the second is an embedded conductor layer (i.e., doped polysilicon or embedded quantum dots (QDs) or metallic nanoparticles (NPs)) floating gate, and the third is a blocking oxide. When a programming voltage is applied, carriers tunnel from the channel to the floating gate. This results in a shift of the threshold voltage of the transistor corresponding to “1”. A reverse bias is applied during the erase operation to move the charges back into the channel. | Yes | |
CT | The charge trap flash replaces the floating gate with a conductor layer that has an insulting layer (i.e., silicon nitride). The most common structures are the SONOS (Polysilicon-oxide-nitride-oxide-silicon) and the TANOS (titanium-alumina-nitride-oxide-silicon). | Yes | ||
NEM-NVM | A nano-electromechanical switch is fabricated such that (i) upon applying a programming electrical signal, its pull-in voltage shifts when operated at a designed switching voltage or (ii) it has a free moving cantilever that has bistable physical states affecting its electrical properties. | No | ||
Molecular Based NVM | A bistable molecule can be switched from a low-conductance state (“0”) to a high-conductance state “1” by applying brief bias voltage pulses to switch the state through oxidation and translation of the molecular structure between the two stable states. | No |
3.2. NVM Architectures
4. Flexible Field-Effect Transistors (FETs) for Logic and NVM Arrays
4.1. All-Organic Transistors
Reference | [165] | [170] | [171] | [167] | [169] | [172] | [173] | [168] | [174] | [175] | [176] | [166] | [120] | [177] |
Year | 2012 | 2012 | 2012 | 2010 | 2013 | 2013 | 2013 | 2014 | 2014 | 2015 | 2010 | 2014 | 2013 | 2015 |
Structure | PEN/Ag gate BST dielectric/pentacene channel/Ag source and drain | PET/Al source and drain/C60 channel/Parylene-C dielectric/Al gate | Metal gate/Mylar/TIPS-pentacene/Metal source and drain | PI/Al gate/ hybrid (AlOx)-organic self-assembled monolayer (SAM) gate dielectric/Pentacene p-channel/Au source and drain | PET/ SWCNT/Ag source and drain/Barium titanate NP in PMMA ink dielectric/Ag gate | Au gate/Parylene dielectric/Au source and drain/TTC18-TTF channel | PI/gate electrode/Parylene dielectric/C8-BTBT channel/Au source and drain/Parylene/PI | PI/Al gate/c-PVP/c-PVP/Pentacene/ Au source and drain | PET/Ag source and drain/barium titanate -BTO-poly(methyl methacrylate) dielectric/Ag gate | PET/ITO gate/PVP dielectric/Pentacene channel/Au source and drain | PEN/Al gate/PI dielectric/QQT(CN)4/Cr-Au source and drain | PET/Ti-Au source and drain/Graphene/PMMA/Au gate | PAR/Au source and drain/P3HT:PEO-blend NW/ion-gel polyelectrolyte/Au gate | PEN/PVP/Ag gate/Parylene dielectric/Ag source and drain/DTBDT-C60 semiconductor |
Approach | All organic | All organic | All organic | All organic | All organic (Ink-jet Printed) | All organic | All organic (Ink-jet Printing) | All Organic | All Organic (Screen Printing) | All Organic | All Organic | All Organic (Low Temperature Deposition + Graphene Transfer) | All organic | All organic |
Dimensions (µm) | 100 × 2000 | 70 × 1800 | 50 × 500 | 85 × 1250 | 20 × 5000 | length is 20 | 150 × 1500 | 105 × 1000 | 100 × 500 | 45 × 4000 | 10 to 20 length | 0.34 × 0.31 | 90 × 1100 | |
Mobility (cm2/VS) | 0.53–1.24 | 0.58 | 0.1 to 0.4 | 0.5 | 9 | 0.0043 | 0.15 | 0.56 | 7.67 | 0.45 | 0.1 to 0.006 | 340 | 9.7 | 1.9 |
SS (mV/Dec) | 100–160 | 1250 | 5000 | 166 | ~3300 | 2300 | 1000 to 1500 | 250 | 170 | |||||
Vth (V) | −1.11 to −1.18 | −0.1 | ~10 to 30 | ~−0.5 | 1.15 | 20 | ~10 | −0.82 | 0.5 | −0.16 | ||||
Operation Voltage (V) | 3 | 10 to 40 | 3 | −10 to 10 | 10 to −50 | −4 to 4 | <10 | 10 to −30 | 100 to −100 | −60 to 40 | 2 | 20 | ||
min bending radius (mm) | 3 | 5.1 | 0.26 unencapsulated and 0.11 encapsulated in Parylene | 0.1 | 1 | 2 | 1 | 0.75 | 3 | 2 | 5 | 10 | 6.25 | |
ION/IOFF | 104 | 105 | 5 × 103 | 1.5 × 103 | 105 | 500 | 5 × 104 | 105 | 104 to 105 | 105 | 108 | |||
Yield | 66% | |||||||||||||
Bending cycles | 104 |
Reference | [178] | [179] | [180] | [181] | [182] | [183] | [184] | [28] | [185] | [186] | [187] | [188] | [189] | [190] | [191] | [192] | [193] |
Year | 2013 | 2014 | 2013 | 2014 | 2014 | 2014 | 2014 | 2014 | 2011 | 2012 | 2013 | 2014 | 2014 | 2015 | 2015 | 2015 | 2013 |
Structure | Parylene/Au gate/Parylene dielectric/pentacene channel/Au source and drain | Au source and drain/ (P(NDI2OD)T2 or N2200) n-type or (pBTTT) p-type/PMMA dielectric/Au gate | PVA/PMMA/Au source and drain/MoS2/Al2O3/Cu gate | PEN/Buffer/Al gate/Al2O3/a-IGZO/Mo-Al-Mo source and drain/PR protection | PI/Ni gate/PVP/Al2O3/a-IGZO/Ni source and drain | PDMS/CuPc NW/metal source and drain/Si3N4/Metal Gate | PI/Cu and MoTi Source and drain/organic semiconductor OSC active/organic gate insulator OGI/Cu gate | PI/ Inorganic Si FinFET | PI/IGZO TFT/PI | PI/SiO2-SiNx-SiO2-SiNx-SiO2/Mo gate/ Hybrid organic-inorganic S-ALO/Au Source and Drain/TIPS PEN:PS Channel | PI/IGZO TFT | Kapton Tape/IZO TFT/ | CPI/IGZO TFT | PI/ZnO TFT | PI/PVP/Al gate/PVP/ZrO2:B/In2O3/Al | PVP/AlOx /aZITO/AryLite | Kapton/PI/Ti/Pd/Al2O3 or HfO2/MOS2/Ti/Au |
Approach | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low Temperature) | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Transfer + encapsulation) | Hybrid (Detachment from Glass Substrate) | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low Temperature + Stripping off Si | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low Temperature) | Hybrid (Deposition at Low temperature) |
Dimensions (µm) | 2 to 10 gate length | 20 × 1000 | 4.3 × 10 | 100 × 100 | 60 × 800 | 10 × 200 | 6 × (14–−160) | 0.25 × 3.6 | 115 × 280 | 4 × 20 to 6000 | 6 × 50 | 50 × 1000 | L 20 × W 10 | 20 × 200 | 50 × 1000 | 1 × 3 | |
Mobility (cm2/VS) | 0.0013 to 0.00022 | 0.1 to 0.3 | 19 | 11.2 | 5.3 to 8.39 | 2 | 0.34 | 141.53 (N) to 13.22 (P) | 13.7 | 0.61 | 18 | 6 to 11.2 | 12.7 | 12 | 0.42 | 10.9 | 30 |
SS (mV/Dec) | ~5000 | 250 | 270 | 520 to 960 | 80 (N) to 70 (P) | 200 | 2000 to 4600 | 160 | 82 | ||||||||
Vth (V) | −4 to 9.5 | −2.12 | 0.5 | 7.03 to 9.8 | 0.345 (N) to 0.713 (P) | 0.154 | −0.27 | 0.9 | 18.8 to 31.3 | −1.7 | 8.07 | 0.7 | −2 | ||||
Operation Voltage (V) | −32 | 20 to 50 | −5 to 2 | 10 to 10 | 20 to −10 | −10 | 30 to −30 | −1.5 to 1.5 | 5 | 0.5 to 2 | 5 | −20 to 20 | 8 | −40 to 40 | 3 | 3 | |
Switching time (ms) | <0.8 × 10−3 | ||||||||||||||||
min bending radius (mm) | 0.4 to 0.8 | 1 | 5 | 10 | 10 | 3 | 4 | 5 | 0.125 | 2 | 5 | 10 | 2 | 3.3 | 5 | 10 | 1 |
ION/IOFF | 104 | 105 | 106 | 109 | 1.4 × 105 to 3.5 × 106 | 104 | 107 | 104.6 (N) to 104.78 (P) | 107 | 3.8 × 104 to 1.5 × 106 | 108 | 3.69 × 105 | 105 | 107 | |||
Yield | 90% | 60% | |||||||||||||||
Bending cycles | 10 | 106 | 105 | 450 | 105 | 5000 | 1000 | 1000 | 5 × 104 | 104 | 100 |
4.2. Hybrid Transistors
4.3. Inorganic Transistors on Flexible Silicon
Reference | [194] | [45] | [125] | [195] |
Year | 2013 | 2014 | 2012 | 2012 |
Structure | Si/NiSi/Al source and drain/Al2O3 dielectric/TaN-Al gate | Inorganic FinFETs on Thinned Si | Inorganic Planar MOSFETs on Exfoliated Si | Inorganic Planar MOSFETs on Thinned Si |
Approach | Inorganic (Etch-protect-Release) | Inorganic (Soft Back Etch) | Inorganic (Exfoliation) | Inorganic (Spalling) |
Dimensions (μm) | 8 length × 5 width | 0.25 (P) to 1 (N) × 3.6 | 0.15 to 1 length | 0.03 length |
Mobility (cm2/VS) | 43 | 102 (P) | 252 (N) to 51 (P) | |
SS (mV/Dec) | 80 | 150 (N) to 63 (P) | 81 (P) to 72 (N) | |
Vth (V) | −0.44 | 0.36 (N) to −0.556 (P) | 0.25 | |
Operation Voltage (V) | 1 to −2 | −1.25 to 1.25 | −1 to 1 | 0.6 |
Switching time (ms) | <16 × 109 | |||
min bending radius (mm) | 0.5 | 6.3 | ||
ION/IOFF | 104 | 105 | 106 (P) | 105 |
Yield | 75% | |||
Bending cycles | 5 | 200 |
5. Flexible NVM Technologies
- a)
- Form Factor (F2): Although form factor usually refers to the physical lateral (length and width) and vertical (height) dimensions for memory module millimeters, at the device level, the form factor is defined as the lateral area of a single memory cell (1 bit) divided by the square of the smallest feature (technology node) and has no units. For example, a memory cell that is 1 × 0.5 μm2 built at the 0.25-μm node would have a form factor of 8F2.
- b)
- Density: The number of memory bits that fit per unit area.
- c)
- Cost ($/bit): The total cost to make memory modules divided by the number of integrated memory bits.
- d)
- Endurance: The number of write/erase cycles a memory cell undergoes before its performance degrades significantly.
- e)
- Retention: The retaining ability of a memory cell to store uncompromised information over time.
- f)
- Operation voltage: The maximum voltage required for a write/erase operation of a memory bit.
- g)
- Speed: The amount of time the memory cell needs to switch between different memory states (‘0’ or ‘1’).
- h)
- Memory window: Measures the distinguishability of the different memory states. Voltage-sensitive memory is proportional to the voltage shift, while current sensitive memory is proportional to the current ratio for different states.
5.1. Flexible ReRAM
5.2. Flexible FeRAM
Reference | [205] | [217] | [212] | [204] | [206] | [211] | [210] | [87] | [27] | [203] | [86] | [209] | [208] | [207] | [219] | [78] | [218] | [81] | [202] | [201] |
Year | 2010 | 2012 | 2013 | 2012 | 2014 | 2015 | 2012 | 2010 | 2011 | 2010 | 2010 | 2012 | 2014 | 2012 | 2014 | 2015 | 2014 | 2012 | 2014 | 2015 |
Memory Type | (1R) | (1R) | (1T) | (1R) | (1D1R) | (1R) | (1R) | (1R) | (1T1R) | (1R) | (1R) | (1R) | (1R) | (1R) | (1R) | (1R) | (1R) | (1D-1R) | (1R) | (1R) |
Flexible Final Structure | PET/Ti/Au/Al/PI:PCBM/Al | PEN/Au/Ag2Se/Ag | PI/SiO2/Ti source and drain/a-IGZO/Ni gate | PEN/Al bottom/coPI layer/ Al top | PI/Si-p-n types diode/Cu/CuOx/Al | PET/ITO/WO3.H2O nanosheets/Cu | Glass/graphene/SiOx/Graphene | PES/Al/graphene-O/Al | Plastic/transferred Si channel material/Au source and drain-> on drainAl/TiO2/Al + Au for WL,BL, and SL | PET/ITO/PMMA/graphene/PMMA/Al | PET/ITO/graphene-O/Al | PES/Al/ZrO2/Al | Kapton/Cu/CuOx/Ag | PES/Cu/TiO2/Cu | Al foil/Ag-CNP(cellulose nanofiber paper)/Ag | PET/Au/Black Phosphorous Quant Dots (BPQD)-PVP/Ag | Si/SiO2/Al/TaN/Al2O3/TaN/Al | PI/Al/B-CNT and N-CNT in polystyrene/Al | PET/rGo/g-C3N4-NSs/rGo | Au/HKUST-1/Au/PET |
Approach | All organic | Hybrid (low temperature deposition) | Hybrid (Deposition at Low Temperature) | All organic | Hybrid (Transfer + Low Temperature Deposition) | Hybrid (Low Temperature Deposition) | Hybrid (Low Temperature Deposition) | All organic | Hybrid (Transfer) | All organic | All organic | Hybrid (Low Temperature Deposition) | Hybrid (Low Temperature Deposition) | Hybrid (Deposition at Low Temperature) | Hybrid (Inorganic Flexible Substrate + Organic Device) | Hybrid (Deposition at Low Temperature) | Inorganic | All Organic | All Organic | All Organic |
Operating Voltage (V) | 4.5 | −2 | −0.5 to +2 | −3 | +2 and +5 | −1.4 to +1 | 0 to +14 | −4 | −4 to +10 | −5 | −2 to +3 | −0.5 to 2.8 | −1 to +1 | 0 to 1.5 | −0.5 | −1.2 to +2.8 | −11 to +11 | 3 | 4.87 | 0.78 |
Form Factor (F2) | -- | -- | 2 | -- | 11.1 | -- | -- | -- | 20 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
Memory Window (V) | -- | -- | 1 | -- | 1 | -- | -- | -- | 4 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
Speed (ns) | -- | 500 × 103 | 1000 | 5 × 106 | -- | 50 | -- | -- | 106 | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | |
Endurance (cycles) | 50 | 104 | 106 | 104 | 100 | 5000 | 400 | 100 | 100 | 1.5 × 105 | 100 | 778 | 100 | -- | 100 | -- | -- | 100 | 50 | 106 |
Retention (s) | 104 | 105 | 104 | 104 | 105 | 105 | 5 × 104 | 105 | 104 | 105 | 5 × 106 | 105 | 120 × 104 | -- | 105 | 1.1 × 103 | -- | 105 | 5000 | 104 |
Operating temperature (°C) | 25 | 200 | 85 | 25 | 25 | 25 | 25 | 25 | 25 | 25 | 25 | 25 | −18 to 82 | -- | 25 | 25 | 25 | 25 | 25 | −70 to +70 |
Bending Radius (mm) | 9 | 16 | 10 | 5 | 10 | 8 | 6 | 7 | 5 | 10 | 4 | -- | 5 | 10 | 0.35 | -- | 1 | 10 | 8 | 3.2 |
Bending Cycles | 140 | 100 | 1000 | 1000 | 1000 | 2000 | 300 | 1000 | 1000 | -- | 1000 | -- | 1000 | 100 | 1000 | -- | -- | 500 | 1000 | 160 |
Yield | -- | -- | -- | 95%–99% | 85%–90% | -- | 70% | 80% | 60% | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
Cell Dimensions (µm) | -- | -- | 10 × 20 channel | 200 × 200 | 150 × 300 channel | -- | 100 diameter | 50 × 50 | 10 × 200 | 17.74 to 26.71 diameter | -- | -- | 20 × 20 | -- | 50 × 50 | 500 × 500 | 100 × 100 | -- | 1000 × 3000 | 100 diameter |
600 × 600 | 500 cell | 500 × 500 | 250 × 250 |
Reference | [84] | [231] | [235] | [232] | [233] | [236] | [229] | [237] | [238] | [239] | [240] | [230] | [241] | [242] | [243] |
Year | 2013 | 2010 | 2012 | 2011 | 2011 | 2013 | 2015 | 2011 | 2011 | 2012 | 2012 | 2012 | 2015 | 2014 | 2013 |
Memory Type | Ferroelectric (1T) | Ferroelectric (1C) | Ferroelectric (1C) | Ferroelectric (1T) | Ferroelectric (1T) | Ferroelectric (1C) | Ferroelectric (1C) | Ferroelectric (1C) | Ferroelectric (1C) | Ferroelectric (1T) | Ferroelectric (1C) | Ferroelectric (1C) | Ferroelectric (1R) | Ferroelectric (1T) | Ferroelectric (1T) |
Flexible Final Structure | PI/Su-8/SiO2/Pt gate electrode/ PZT/graphene channel/ Cr-Au for source and drain electrodes | Plastic/Cr-Au/Ti-Pt/PZT/Pt/Cr/Au | Al foil/ PVD-TrFE/ Au | PEN/Ti-Au-Ti soucre and drain/Al2O3/ZnO channel/Al2O3 interface dielectric/PVDF-TrFE ferroelectric/Au | Au/poly(vinylidene fluoride-trifluoroethylene)/Al2O3/ZnO/Ti/Au/Ti/poly(ethylene naphthalate) | ULTEM 1000B/PEDOT:PSS/P(VDF-TrFE)/PEDOT:PSS | Si/SiO2/Ti-Pt/PZT/Pt | PEN/PEDOT:PSS/P(VDF-TrFE)/PEDOT:PSS | PEN/Au/P(VDF-TrFE)/Au | Bank Note/PDMS/PEDOT:PSS bottom electrode/ P(VDF-TrFE) ferroelectric/ Pentacene channel/ Au soucre and drain | Ag/BaTiO3/PVDF-TrFE nanocomposites/Ag | Pt/PZT(200 nm)/SRO(30 nm)/Pt(200 nm) foil | PET/Ag ink/PVDF-TrFE/Ag ink | PDMS/Au source and drain/F8T2 organic semiconductor/PVDF-TrFE ferroelectric/ Al gate | PI/PVP/Au source and Drain/Polymer blend channel/PVDF-TrFE ferroelectric/Al gate |
Approach | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Transfer) | Hybrid (Low Temperature Deposition) | Hybrid (Low Temperature Deposition) | All organic (ink-jet printing) | Inorganic | All organic | All organic | All organic | Hybrid (inorganic/organic composite substrate and device) | Inorganic | All Organic | All Organic | All Organic |
Operating Voltage (V) | −11 | −3 | −12 | −14 to +12 | −10 to +8 | −30 | −15 | −10 | −30 to +30 | −15 to +15 | −3.3 | −4 | 23 | −20 to +20 | −80 to +80 |
Form Factor (F2) | 8 | -- | -- | 2 | 2 | -- | -- | -- | -- | 16.67 | -- | -- | -- | 3 | 1 |
Memory Window (V) | 6 | -- | -- | 7.8 | 3.4 | -- | -- | -- | -- | 8 | -- | -- | -- | 11 | 35 |
Speed (ns) | -- | -- | -- | 1 × 109 | 2 × 109 | 50 × 106 | 500 | 106 | 10 × 103 | -- | -- | -- | 108 | 108 | -- |
Endurance (cycles) | 1000 | -- | -- | -- | -- | 45% polarization after 105 | 109 | 106 has 80% Pr | -- | 105 | -- | 107 | -- | 6 × 104 | 100 |
Retention (s) | 200 | -- | -- | 1.5 × 104 | <104 | -- | 105 | -- | -- | 104 | -- | -- | -- | 2000 | 104 |
Operating temperature (°C) | 25 | 25 | 25 | 25 | 25 | 25 | 200 | 25 | 25 | 25 | 25 | 25 | 25 | 25 | 25 |
Bending Radius (mm) | 9 | 8 | 6 | 9.7 | 9.7 | -- | 5 | -- | 6.5 | -- | -- | -- | -- | 6 | -- |
Bending Cycles | 200 | -- | 500 | 2 × 104 | 2 × 104 | -- | 1000 | -- | -- | -- | -- | -- | -- | -- | -- |
Yield | -- | -- | -- | -- | -- | -- | 95% | -- | -- | 90% | -- | -- | -- | -- | -- |
Cell Dimensions (µm) | 10 × 80 channel | 100 × 400 | 180 diameter | 20 × 40 channel | 20 × 40 channel | 60 × 60 | 100 × 100 | -- | 25 × 25 | 60 × 1000 channel | -- | 100 diameter | 30 × 30 | 20 × 60 | 20 × 20 |
250 × 250 | 50 × 50 |
Property | Best Reported Value for PZT-based FeRAM |
---|---|
Switching Speed | Pico seconds regime for material switching [225,226] and 70 ns for actual arrays due to bit/word line capacitances [244] |
Ferroelectric Capacitor’s Lateral Dimensions | 0.1 µm2 [245] |
Switching Energy | 400 fJ/bit [246] |
Retention | >10 years @ 85 °C [247] , experimentally three days (2.5 × 10^5) was demonstrated for FeRAM (using SrBi2Ta2O9(SBT)) [248,249] |
Technology Node (CMOS Logic) | 130 nm [247] |
Operation Voltage | 1.5 Volts [246] |
Read/Write Cycles | >1015 [250,251] |
5.3. Flexible PCRAM
Reference | [252] | [253] | [254] | [255] |
Year | 2010 | 2011 | 2012 | 2015 |
Memory Type | PCRAM (1R) | PCRAM (1R) | PCRAM (1R) | PCRAM (1D-1R) |
Flexible Final Structure | PI/TiN/GST/Pt probe tip | PET or PI or Stainless steel/ TiW bottom electrode/GST (Ge2Sb2Te5)/Cr top electrode | GFR Hybrimer Film/TiN/Pt/TiN/IST/Ps-b-PMMA/Cr | BCP/Transferred Si Diode/TiW bottom electrode/GST/SiOx cylinders/TiN/TiW top electrode |
Approach | Hybrid (Low Temperature Deposition + Transfer by Hot Embossing and Nano Imprint Lithography -NIL) | Hybrid (Low Temperature Deposition + NIL) | Hybrid (Low Temperature Deposition) | Hybrid (transfer + low temperature deposition) |
Operating Voltage (V) | 1.8 | 3 | 1.8 | 8.5 |
Form Factor (F2) | -- | -- | -- | -- |
Memory Window | -- | -- | -- | -- |
Speed (ns) | 30 | 200 | 100 | 1000 |
Endurance (cycles) | -- | -- | -- | 100 |
Retention (s) | -- | -- | -- | 104 |
Operating temperature (°C) | 25 | 25 | 25 | 25 |
Bending Radius (mm) | -- | -- | 2.25 | 10 |
Bending Cycles | -- | -- | -- | 1000 |
Yield | -- | -- | -- | 66% |
Cell Dimensions (μm) | 0.2 to 0.3 diameter | 0.25 diameter | 0.035 diameter | -- |
5.4. Flexible Flash
6. Conclusions and Future Prospects
Reference | [260] | [82] | [80] | [76] | [77] | [262] | [74] | [85] | [73] | [261] |
Year | 2012 | 2011 | 2012 | 2014 | 2011 | 2012 | 2010 | 2012 | 2013 | 2015 |
Memory Type | Flash + Nano Particles (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) | Flash (1T) |
Flexible Final Structure | PET/Ag gate electrode/Al2O3/PMMA with Au NP composite/Pentacene/Au source and drain electrodes | PET/graphene gate electrode/Al2O3/CNT channel/graphene for source and drain electrodes | PES/Si NW/Al2O3/Pt-NP//Al2O3/Al source, drain, and gate | PET/ P(NDI2OD-T2) Channel/ Au source and drain/PVA tunneling dielectric/ Au-NP/ P(VDF−TrFE−CFE) blocking dielectric/ Al gate | PES/ITO gate/PVP blocking/APTES-Au-NP/PVP tunneling/MoO3 buffer/ Pentacene channel/ITO source and drain | PES/Al source and drain/ZnOPDA/AlOx-SAOLs/Zno:Cu/AlOx-SAOLs/Pentacene/ Al gate | PES/Ti-Au gate/ PVP blocking/ APTES-Au NP storage/PVP tunneling/ Pentacene channel/ Au source and drain | PEN/graphene channel/Al2O3/HfOx/Al2O3/ ITO | PET/ITO gate/Al2O3/Au NP charge trapping/Al2O3/PDPP-TBT/Au source and drain | PDMS/PI/Au/Al2O3-SiO2/SWCNT/Au |
Approach | All organic | All organic | Hybrid (Transfer) | All organic | All organic | Hybrid (Low Temperature Deposition) | All organic | Hybrid (Deposition at Low Temperature) | All organic | Hybrid (Transfer) |
Operating Voltage (V) | −5 to +5 | −10 to +10 | −10 to +10 | −6 to +6 | −90 to +90 | −15 to +15 | −90 to +90 | −21 to +23 | −40 to +40 | −25 to +25 |
Form Factor (F2) | 10 | -- | -- | 20 | 10 | 2 | 10 | 6.67 | 20 | 11 |
Memory Window | 2.1 | 10 | 1.85 | 2 | 15 | 14.1 | 9.7 | 8.6 | 7.5 | 13.2 |
Speed (ns) | -- | 100 | 107 | 2 × 109 | 1 × 109 | 1 × 108 | 1 × 109 | hypothesized ~14 ns read time and 20 μs/20 ms write/erase time | 10 × 107 | 105 |
Endurance (cycles) | 1000 | 500 | 104 | 105 | -- | -- | 700 | -- | 1000 | 104 |
Retention (s) | 105 | 1000 | 104 | 105 | 105 | 1000 | 105 | 30% after 10 years | 106 | 104 |
Operating temperature (°C) | 100 | 25 | 25 | 25 | 85 | 25 | 25 | degrades at 85 | 25 | 25 |
Bending Radius (mm) | 10 | 8 | 16 | 9 | 20 | -- | 20 | 5 | 10 | 5 |
Bending Cycles | 1000 | 1000 | 1000 | 100 | 2000 | -- | 1000 | 10 | 1000 | 1000 |
Yield | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
Cell Dimensions (μm) | 50 × 500 channel | -- | 2 channel length | 100 × 2000 channel | 100 × 1000 channel | 50 × 100 channel | 100 × 1000 channel | 30 × 4.5 channel | 50 × 1000 channel | 18 × 200 |
Acknowledgments
Conflicts of Interest
References
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Ghoneim, M.T.; Hussain, M.M. Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics. Electronics 2015, 4, 424-479. https://doi.org/10.3390/electronics4030424
Ghoneim MT, Hussain MM. Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics. Electronics. 2015; 4(3):424-479. https://doi.org/10.3390/electronics4030424
Chicago/Turabian StyleGhoneim, Mohamed T., and Muhammad M. Hussain. 2015. "Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics" Electronics 4, no. 3: 424-479. https://doi.org/10.3390/electronics4030424