Replacing State Variables for Moore FSMs with Twofold State Assignment

Abstract

In this paper, a new method of structural decomposition is proposed. The method focuses on FPGA-based Moore finite state machines (FSMs). The method makes it possible to improve both spatial and temporal characteristics of the FSM circuits. Each internal state is represented by two codes. One of them is a partial state code representing a state as an element of some class of compatibility. The second code is represented by a concatenation of two codes: a code of output collection and a code of identifier. The method can be applied if FSM circuits are implemented using look-up table (LUT) elements of field-programmable gate arrays. The resulting FSM circuit includes three logic blocks. The first block generates partial Boolean functions representing partial output collections and identifiers. These functions depend on partial state codes. The partial codes are assigned in a way minimizing the number of arguments in partial functions. This allows generating all partial functions by single-LUT circuits. The second block generates codes of output collections and identifiers. The third block transforms them into FSM outputs and partial state codes. The paper includes an example of FSM synthesis by applying the proposed method. The experiments are conducted using standard benchmark FSMs. The experiments show that the proposed approach can be used for complex FSMs where the total number of FSM inputs and state variables are at least twice the number of inputs of the base LUT. The results of experiments show that the proposed method allows improving both the spatial and temporal characteristics for complex FSMs compared with their counterparts based on methods used by the Vivado tool.

1. Introduction

Nowadays, a model of a finite state machine (FSM) is a powerful tool used for representing various sequential blocks [1,2,3]. For example, this model is used for representing the control units of computers [4,5,6,7,8], hardware–software interfaces and communication protocols of embedded systems [9] and in many other cases [10,11,12,13,14,15,16]. It could even be used for the synthesis of both a control unit and a data path, creating a single operational block [17,18,19]. This wide range of applications is a source of developing new methods for synthesizing and optimizing characteristics of FSMs. The optimization methods depend significantly on the specifics of the logic elements used for implementing the FSM circuit. Also, they depend on peculiarities of an FSM model used [3]. In this paper, we propose a method for reducing the chip area occupied by circuits of Moore FSMs.

The majority of papers and monographs deal with Mealy FSMs. The reason for this situation is that Mealy FSMs can have significantly fewer states than equivalent Moore FSMs [20]. This leads to the conclusion that circuits of Mealy FSMS will require fewer resources than it is for equivalent Moore FSMs. But the outputs of Moore FSMs depend only on internal states. As a result, a part of the logic circuit that generates outputs is simpler for Moore FSMs than for equivalent Mealy FSMs. Moreover, Mealy FSMs are unstable because their outputs depend directly on their inputs. This dependence leads to the following phenomena: rattling of the inputs results in glitches in the outputs. In turn, these glitches could result in improper functioning of the system of which an FSM is a part. To stabilize the outputs, an addition register is introduced in the FSM circuit. This register consumes some chip resources and increases the cycle time. There are no output glitches in Moore FSMs. As a result, the circuits of Moore FSMs require fewer flip-flops and can be faster than those of equivalent Mealy FSMs. These positive features of Moore FSMs explain our choice of this model as a research subject.

We discuss a case when FSM circuits are implemented using the internal resources of field-programmable gate arrays (FPGAs) [21,22,23]. Our choice is justified by the fact that, starting from 1984, these chips have been widely applied for implementing diversified digital systems [24]. The architectures of FPGA chips are constantly being improved [25,26]. The leading experts are sure that FPGAs will play an important role in the development of various hardware tools for artificial intelligence [27]. This means that FPGAs will continue to be used in the foreseeable future [28]. In this paper, we discuss a case in which the logic circuits of Moore finite-state machines are implemented using fine-grain configurable logic blocks (CLBs) based on look-up table (LUT) elements.

In the paper, we discuss SRAM-based single-output LUTs having $S_L$ inputs [21,23]. Such LUTs are used in FPGA chips produced by AMD Xilinx [29]. This company occupies a leading position in the FPGA market. Each SRAM cell keeps one bit of information. Using LUT inputs allows transferring the content of a particular cell to the LUT output. Due to it, a LUT generates a Boolean function dependent on up to $S_L$ arguments [30,31]. To be a flexible logic element, each LUT has very small value of $S_L$ (around six) [21,23]. This is a specific required using the functional decomposition (FD) of functions to be generated. The FD-based methods allow representing initial systems of Boolean functions (SBFs) as compositions of partial functions [31,32]. This leads to obtaining multi-level FSM circuits [3].

Very often, the criterion of optimality for an FSM circuit is a minimum chip area occupied [33,34]. As a rule, optimizing the required chip area diminishes the value of power consumed by an FSM circuit [35,36,37]. In the best case, optimizing chip area does not significantly increase the time of the operation cycle. In this paper, we propose a method that allows reducing the required chip area without a decrease in the maximum operating frequency of the resulting Moore FSM circuit.

As it is known [37], the spatial characteristics of a LUT-based FSM circuit are determined mostly by the number of LUTs consumed (LUT count) and the system of inter-CLB interconnections. Thus, to reduce the chip area occupied by an FSM circuit, it is necessary to diminish the number of LUTs required. Also, it is necessary to optimize the system of interconnections. This is connected with the following issues. Firstly, the delay associated with interconnections now dominates the delay associated with logic [30,38]. Also, the interconnection system consumes up to 70% of power [39]. So, optimizing interconnections reduces both circuit delay and power consumption.

As shown in [24], the value SL = 6 provides the optimal balance among LUT characteristics such as occupied chip area, delay, and power consumption. This means that we cannot expect that the number of LUT inputs will be increased in the foreseeable future. But we witness the constant growth of the complexity of FPGA-based projects [14,40]. So, it is necessary to develop efficient design methods to overcome this specific feature of LUTs.

In this paper, we propose a new design method allowing to improve the LUT counts in the circuits of Moore FSMs. The proposed method is based on representing state codes as concatenations of codes of output collections (OC) and identifiers. The main contributions of our current work are the following:

1.

A new design method allowing for improving two main characteristics of FPGA-based circuits of Moore FSMs (LUT count and performance).

2.

Finding the conditions for applying the proposed method.

3.

Conducting the experiments showing the positive and negative sides of the proposed method.

The main idea of the proposed method is to represent state variables as functions of variables encoding OCs and identifiers. We use this approach for Moore FSMs with twofold state codes. The proposed method belongs to methods of structural decomposition (SD). Using this method allows designing three-level Moore FSM circuits having fewer LUTs than their counterparts based on functional decomposition.

The remained part of the paper includes five sections and a brief conclusion. In the paper, we show: 1) the background of Moore FSMs and FPGAs (Section 2); 2) the state-of-the-art in FSM-based design (Section 3); 3) the proposed design method (Section 4); 4) an example of FSM design using the proposed method (Section 5) and 5) the experimental results (Section 6) and their discussion (Section 7).

To improve the readability of the paper, we create Table 1. The table includes most of the sets, variables, and blocks, and identifies their meanings.

Table 1. Summarized notation table.

Symbol	Meaning
$S_L$	the number of inputs of the LUT
$A=\{a_1,\dots ,a_M\}$	the set of internal states, where $a_m\in A$ is a state
$X=\{x_1,\dots ,x_L\}$	the set of external inputs, where $x_e\in X$ is an input
$Y=\{y_1,\dots ,y_N\}$	the set of outputs, where $y_n\in Y$ is an output
$Y_q\subset Y$	the collection of outputs
$D=\{D_1,\dots ,D_R\}$	the set of input memory functions
$B_T$	the block generating input memory functions
$B_Y$	the block generating FSM outputs
$NL\left(f_i\right)$	the number of literals in the sum-of-products
$R_Q$	the number of bits in the codes of OCs $Y_q\subseteq Y$
$Z=Z(T,X)$	the set of variables encoding the OCs
$BZV$	the block generating additional variables
${\mathrm{\Pi }}_E$	the partition of the set A
${\tau }^k$	the set of variables encoding states for the class $A^k\in {\mathrm{\Pi }}_E$
$B\tau$	the block generating partial state variables
$V=\{v_1,\dots ,v_{RI}\}$	the set of variables encoding the identifiers
R	the number of state variables
$R_I$	the number of variables encoding identifiers
$L_m$	the number of inputs determining transitions from the state $a_m\in A$
$R_k$	the number of bits in the partial state codes for states $a_m\in A^k$
$R_E$	the number of bits in extended state codes
$D^k$	the set of IMFs generating during transitions from states $a_m\in A^k$
$X^k$	the set of inputs determining transitions from states $a_m\in A^k$
$\tau$	the set of variables encoding expanded state codes $EC\left(a_m\right)$
$PC\left(a_m\right)$	partial state code of the state $a_m\in A^k$
$BVZ$	the block generating variables encoding OCs and identifiers

2. Background Information

As a rule, modern FPGAs include diversified CLBs (for example, LUTs, digital signal processors, embedded memory blocks) and a matrix of programmable interconnections [21,22,23,29,41]. In this article, we consider design based on CLBs consisting of LUTs and programmable flip-flops. There is a wired connection between the LUT output and informational input of a flip-flop. In the case of FSM-based projects, these flip-flops are used for organizing either registers or counters keeping state codes [42].

The main peculiarity of a LUT is a very limited value of $S_L$. Nowadays, the value of $S_L$ does not exceed 6 [21,22,23]. If a Boolean function to be generated depends on at least 1 + $S_L$ variables, then the corresponding circuit should be implemented using FD-based methods [31]. As a result, such FSM circuit is multi-level. Moreover, the CLBs are connected using the irregular interconnect system. As shown in [3], irregular interconnect systems are slower and require more power than their SD-based counterparts.

The mathematical model of Moore FSM is a six-tuple $S=<A,X,Y,\delta ,\lambda ,a_1>$ [42] including the following components: $A=\{a_1,$...$,a_M\}$ is a set of internal states, $X=\{x_1,$...$,x_L\}$ is a set of external inputs, $Y=\{y_1,$...$,y_N\}$ is a set of FSM outputs, $\delta$ is a transition function, $\lambda$ is an output function, and $a_1\in A$ is an initial state. So, an FSM has M states, L inputs and N outputs. In the starting point of operation, a Moore FSM should be set into the state $a_1\in A$. Various tools are used for representing this six-tuple. On of the most visual types of representation is a state transition table (STTs) [1]. Thanks to this clarity, we use these tables in our paper.

The STT can be viewed as a list of transitions existed into a state transition graph (STG). If an STG has M nodes, then the corresponding STT describes transitions from M states $a_m\in A$. If transitions are shown for a state $a_m\in A$, this state is called a current state. They are written in the column $a_m$ of STT. For STG of a Moore FSM, the CO $Y_q\subseteq Y$ is written, where $q\in \{1,$...$,Q\}$. In the STT, these COs are written into the column of current states. In STG, interstate transitions are represented by arcs directed from the current states to states of transitions. The states of transitions are placed into the column $a_s$ of STT. If there are H arcs in an STG, then there are H lines in the equivalent STT. In the STG, the input signal $X_h$ determined a particular transition is written above the corresponding arc. The signal $X_h$ is represented by a conjunction of inputs $x_l\in X$ (or their compliments) determined a particular transition. In the STT, this signal is written into a column $X_h$. So, an STT consists of columns $a_m$, $a_s$, $X_h$, h.

To implement an FSM circuit, it is necessary to create two SBFs [42]. To do it, it is necessary to replace states by their binary codes. This is done during the step of state assignment [1,42]. During this step, each FSM state is represented by a binary code $K\left(a_m\right)$. These codes include R bits. Each bit corresponds to a state variable $T_r\in T=\{T_1,$...$,T_R\}$ where T is a set of state variables. The minimum possible value of R is provided by the maximum binary state assignment when

$$R=\lceil lo{g}_{2}M\rceil .$$

(1)

The Equation (1) determines the maximum binary codes (MBCs). These codes are very popular; they are used in many academic CAD systems [43,44]. Also, this style is used by industrial CAD tools [45,46].

State codes are kept into a special state register (RG). As a rule, in FPGA-based design, the state register is constructed using synchronous D flip-flops [3]. These flip-flops have the shared inputs of synchronization (Clock) and reset (Start). To change the content of RG, special input memory functions (IMFs) are used. These functions form a set of IMFs $D=\{D_1,$...$,D_R\}$.

To design an FSM circuit, it is necessary to represent: (1) FSM outputs as functions depended on state variables and (2) IMFs as functions depended on both state variables and FSM inputs. The following SBFs represent a circuit of Moore FSM:

$$D=D(T,X);$$

(2)

$$Y=Y\left(T\right).$$

(3)

These SBFs are derived from a direct structure table (DST). The DST includes the columns of STT ($a_m$, $a_s$, $X_h$, h) and the columns $K\left(a_m\right)$, $K\left(a_s\right)$, $D_h$. Obviously, the column $K\left(a_m\right)$ includes the codes of current states, while the column $K\left(a_s\right)$ contains the codes of the states of transitions. The column $D_h$ includes IMFs determining the change of RG’s content from $K\left(a_m\right)$ to $K\left(a_s\right)$.

To generate functions $D_r\in D$, it is necessary to use at least R LUTs. These LUTs are combined into a block BT. To generate outputs $y_n\in Y$, it is necessary to use at least N LUTs. These two blocks of LUTs represent a LUT-based logic circuit of Moore FSM $U_1$ (Figure 1) [36,47].

Figure 1. Structural diagram of LUT-based Moore FSM $U_1$.

In FSM $U_1$, the block $BT$ implements SBF (2), the block $BY$ generates functions from SBF (3). The block $BT$ includes a hidden state register distributed among its LUTs. This register transforms IMFs into state variables. To control the operation of RG, the signals of clearing (Start) and synchronization (Clock) enter the block $BT$.

One of the specifics of Moore FSM follows from (3): FSM outputs do not depend on FSM inputs. Due to it, the outputs could be generated by embedded memory blocks [3]. But it this paper, only LUT-based FSMs are discussed. However, the specific mentioned above makes easier the optimization process for the block $BY$. We discuss some possibilities of optimization in the next sections.

3. State-of-the-Art

The transition from an STT (or other form of FSM representation) to LUT-based electrical circuit is executed during the step of technology mapping [8,48]. This process is connected with necessity of solution of some optimization problems. The classical problems are: (1) minimizing the chip area occupied; (2) maximizing the operating frequency; (3) minimizing the power consumption; (4) increasing the testability of FSM circuit [3,49]. The fast development of intelligent tools [25,27] has raised the problem of increased security for FPGA-based projects [26]. In this paper, a method is proposed aimed at solving the first problem. To reduce the required chip area, it is necessary to minimize the value of LUT count (the number of LUTs required) and reduce the total length of inter-CLB interconnections [3].

We use the symbol $NL\left(f_i\right)$ for the number of literals [1] in sum-of-products (SOPs) of Boolean functions $f_i\in D\cup Y$. The relation between values of $NL\left(f_i\right)$ and $S_L$ determines the number of levels in LUT-based FSM circuit [3]. Consider the following condition:

$$NL\left(f_i\right)\le S_L.$$

(4)

If (4) holds, then an FSM circuit is single-level.Such a circuit consists of $R+N$ LUTs. Also, this is the fastest from all possible circuits for a given FSM. But it is necessary at least two levels of LUTs for generating functions $f_i\in D\cup Y$ for which the condition (4) is not met. Obviously, the LUT count should be minimized (if it is possible). To optimize the interconnection system, it is necessary to produce a circuit where the same inputs $x_l\in X$ and state variables $T_r\in T$ appear only on a single logic level. Otherwise, the circuit has a system of «spaghetti-type» interconnections [3]. As shown in [50], the circuits with regular system of interconnections consume less power and are faster than their counterparts with the spaghetti-type interconnections.

Let us briefly analyze the approaches which allow optimizing FPGA chip area occupied by a Moore FSM circuit. There are three basic methods aimed at solution of this problem: (1) the functional decomposition of SBFs (2) and (3) [4,31,51,52]; (2) the optimal state assignment [1,3,53]; (3) the structural decomposition of FSM circuits [3,50,54].

The FD-based methods use the following approach. If the condition (4) is not met, then a Boolean function is represented as a composition of partial Boolean functions. Each partial function should include no more than $S_L$ literals. This approach is based on the Shannon decomposition [52] and allows representing any Boolean function as an expression using disjunction, conjunction and negation. The initial function should be decomposed into one of the variables. As a result, the function is represented as a combination of two other functions that depend on the remaining variables. The functional decomposition is a very powerful tool used in the process of FPGA-based technology mapping [52,55]. Applying FD leads to appearing new functions different from (2) and (3). Each of this functions requires a single LUT to be generated. If the condition (4) is violated, then the logic circuit of FSM $U_1$ includes $R+N+NF1$ LUTs, where NF1 is the number of new functions different from $D_r\in D$ and $y_n\in Y$. The FD-based program tools could be found in academic CAD tools [43,44], as well as in industrial CAD packages [56,57,58].

Obviously, FD-based circuits are multi-level. Due to it, they are slower than their single-level counterparts. They have more complex interconnection system which adds some delay in the cycle time and increases the value of power consumption. But this is a universal approach which allows designing LUT-based circuits for FSMs of any complexity.

Using different strategies of state assignment leads to FPGA-based FSM circuits with different values of occupied chip areas [59]. If the main criterion of optimality is a minimum value of LUT count, then a state assignment is optimal if it gives a solution for this problem. To do it, it is necessary to delete the maximum possible amount of literals from SOPs of functions $D_r\in D$ and $y_n\in Y$.

It is known [3] that each literal of SOP is represented by a wire connecting some elements inside an FSM circuit. Obviously, eliminating literals from SOPs (2) and (3) allows reducing the total length of interconnections. In turn, this reduces the chip area required for an FSM circuit. Even if the condition (4) takes place, it makes sense to reduce the numbers of literals in SOPs of functions $D_r\in D$ and $y_n\in Y$. Therefore, using the optimal state assignment always makes sense.

Because it is difficult to predict which state assignment strategy is the best for optimizing a particular FSM circuit, it makes sense to use various strategies. Next, the best possible solution should be selected. Due to it, modern industrial CAD tools give opportunity to use various state assignment methods. A good example is the industrial package Vivado [57] of AMD Xilinx. The following strategies are used in Vivado: the automatic state assignment (the value of R may exceed the minimum value determined by (1)); one-hot (R=M); compact; Gray codes; Johnson codes; speed encoding. Our research [3] shows that increasing the value of R may optimize the SBF (2) but it makes SBF (3) more complex.

Methods of structural decomposition [3] are based on elimination of a direct dependence between FSM inputs and functions $D_r\in D$ and $y_n\in Y$. To eliminate this dependence, some additional functions are introduced. Each system of additional functions determines a unique logic block of FSM architecture. Each block has unique sets of input and output variables. These blocks are connected in a way when output functions of one block are used as inputs of another block (or blocks).

The first SD methods are [60]: the replacement of inputs and encoding of the collections of outputs. The first of them can be used for optimizing both Mealy and Moore FSMs. These methods are discussed, for example, in [3]. The second method is mostly used for optimizing Mealy FSMs where outputs depend on both state variables and FSM inputs. In this paper, we propose to use the encoding of OCs (EOC) for optimizing circuits of Moore FSMs. Let us explain the essence of EOC.

If there are Q various OCs into the STT of a particular FSM, then each OC $Y_q\subset Y$ is encoded by binary code $K\left(Y_q\right)$ having $R_Q$ bits:

$$R_Q=\lceil lo{g}_{2}Q\rceil .$$

(5)

To encode OCs, the additional variables are used. These variables are combined into a set of $Z=\{z_1,$...$,z_{RQ}\}$. To generate FSM outputs, it necessary to implement circuits for the following SBFs:

$$Z=Z(T,X);$$

(6)

$$Y=Y\left(Z\right).$$

(7)

Obviously, this approach has an overhead: the circuit implementing (6) adds a delay to FSM cycle time and consumes some internal resources of FPGA chip. So, this approach makes sense if it allows significantly reducing the occupied chip area compared with a circuit based on SBFs (2) and (3). This approach does not used for optimizing Moore FSM circuits because here outputs depend only on state variables. Comparison SBFs (3) and (7) shows that the set Z replaces the set T.

In the case of Moore FSMs, this approach could be used if the following conditions hold:

$$R>S_L;$$

(8)

$$R_Q\le S_L.$$

(9)

In this case, a multi-level circuit based on (3) is replaced by a single-level circuit based on (7), and, moreover, if the condition (9) holds, then it is possible to turn a LUT into two LUTs having $S_L-1$ inputs [37], which obviously allows halving the number of LUTs implementing the system of outputs; this approach can be used, for example, when Virtex-7 FPGAs [61] are used [33,34], and the same approach can also be used in Virtex Ultrascale+ FPGAs [29,41].

In [36], we discuss an approach that allows using EOC for optimizing circuits of Moore FSMs, which presumes generating state variables using codes of COs and some identifiers, and we now consider this approach.

As follows from (3), a state $a_m\in A$ unambiguously defines an OC $Y_q\subset Y$ generated in this state, and although it is obviously possible to define states using OCs, it may happen that the same OC $Y_q\subset Y$ is generated in several states $a_m\in A$, in which case it is necessary to use some additional identifier to select the proper state. For example, if a CO $Y_1$ is generated in the states $a_2,a_6,a_7$, then three identifiers $I_1,I_2,I_3$ are required to define a particular state, and we can define the states using pairs <OC, identifier>, such that the state $a_2$ is determined by the pair $<Y_1,I_1>$, the state $a_6$ by the pair $<Y_1,I_2>$, and the state $a_7$ by the pair $<Y_1,I_3>$.

To design an FSM circuit, we should encode OCs by binary codes $K\left(Y_q\right)$ and identifiers by binary codes $K\left(I_g\right)$. To encode OCs, we use $R_Q$ elements from the set Z. To encode identifiers, we use $R_I$ elements of the set $V=\{v_1,$...$,v_{RI}\}$. The value of $R_I$ is determined as

$$R_I=\lceil lo{g}_{2}G\rceil .$$

(10)

In (10), the symbol G stands for the maximum number of identifiers required for selecting a state.

Using these codes, we can represent a state code $C\left(a_m\right)$ as the concatenation of codes $K\left(Y_q\right)$ and $K\left(I_g\right)$:

$$C\left(a_m\right)=K\left(Y_q\right)\ast K\left(I_g\right).$$

(11)

In (11), the symbol * stands for the concatenation.

Using (11), it is possible to represent state variables in the following form:

$$T=T(Z,V).$$

(12)

Of course, the variables $z_r\in Z$ and $v_r\in V$ should be generated. To do it, the following SBFs should be obtained:

$$Z=Z(T,X);$$

(13)

$$V=V(T,X).$$

(14)

The SBFs (7), (12)–(14) determine an FSM $U_2$. Its structural diagram is shown in Figure 2.

Figure 2. Structural diagram of FSM $U_2$.

Three blocks create this FSM circuit. The block $BZV$ generates functions belonging to SBFs (13) and (14). This block includes a hidden register having $R_C=R_Q+R_I$ flip-flops. The variables $z_r\in Z$ and $v_r\in V$ are registered because they correspond to outputs of flip-flops. The pulses Start and Clock control the register. The block $BY$ implements SBF (7). The block $BT$ implements SBF (12).

If conditions (8) and (9) take place, then this approach allows implementing $U_2$-based Moore FSM circuits with fewer LUTs than their counterparts based on the model $U_1$ [47], and the best results are reached if the following condition holds:

$$R_C=R_Q+R_I=R.$$

(15)

As with all LUT-based models, the model $U_2$ has one serious drawback, which manifests itself if there are some states $a_m\in A$ for which the following condition is true:

$$R_C+L_m>S_L.$$

(16)

In (16), the symbol $L_m$ stands for the number of FSM inputs determining transitions from a state $a_m\in A$.

If (16) holds, then the circuit of block $BZV$ is multi-level, which leads to increased values of LUT count, cycle time, and consumed power; in this paper, we propose an approach that overcomes the negative influence of (16).

4. Essence of Proposed Method

To improve the basic characteristics of the Moore FSM circuit, we propose to transform the codes (11) into extended state codes (ESC) [3]. The extended state codes are based on finding a partition ${\mathrm{\Pi }}_E=\{A^1,$...$,A^K\}$ of the set A by the classes of compatible states. States are encoded as elements of classes $A^k\in {\mathrm{\Pi }}_E$. So, a state $a_m\in A^k$ is encoded by a partial state code $PC\left(a_m\right)$. The code $PC\left(a_m\right)$ includes $R_k$ bits, where

$$R_k=\lceil {log}_2(M_k+1)\rceil .$$

(17)

In (17), the symbol $M_k$ stands for the number of elements in the class $A^k\in {\mathrm{\Pi }}_E$. To take into account the relation $a_m\notin A^k$, some code should be used. Due to it, 1 is added to $M_k$. Let us point out that states are compatible if their presence in the same class does not increase the required number of LUT inputs beyond the value $S_L$ [3].

The state variables ${\tau }_r\in {\tau }^k=\{{\tau }_1,$...$,{\tau }_{Rk}\}$ create partial codes for a particular class $A^k\in {\mathrm{\Pi }}_E$. The sets ${\tau }^k$ are combined into the set $\tau$ having $R_E$ state variables:

$$R_E=R_1+R_2+...+R_K.$$

(18)

Concatenations of partial codes create extended state codes $EC\left(a_m\right)$:

$$EC\left(a_m\right)=P{C}_1\left(a_m\right)\ast P{C}_2\left(a_m\right)\ast ...\ast P{C}_K\left(a_m\right).$$

(19)

In (19), we use the subscripts to show that a particular partial code used to represent a state $a_m\in A$ as an element of a class $A^k\in {\mathrm{\Pi }}_E$. The symbol * stands for the operation of concatenation of binary strings. We do not use these subscripts during the synthesis process.

The k-th class determines a block $Bk$ generating partial IMFs:

$$D^k=D^k({\tau }^k,X^k).$$

(20)

In (20), the symbol $D^k$ stands for a set of partial IMFs generated during transitions from the states $a_m\in A^k$, and the symbol $X^k$ stands for a set of FSM inputs causing transitions from the states $a_m\in A^k$. These K blocks create the first level of the proposed FSM architecture. Each block $Bk$ generates up to $R_C$ partial functions.

These PBFs should be combined together as disjunctions:

$$D_r=D_r^1\vee D_r^2\vee ...\vee D_r^K.$$

(21)

To generate functions $D_r\in D$, we propose to use a block $BVZ$. This is the second logic level of the FSM circuit. To transform (21) into stable variables $z_r\in Z$ and $v_r\in V$, the block should include a hidden register. There are $R_C=R_Q+R_I$ flip-flops in this register. The variables $z_r\in Z$ are formed on the outputs of the first $R_Q$ flip-flops. The variables $v_r\in V$ are represented by the outputs of the last $R_I$ flip-flops. Obviously, these flip-flops should be controlled by synchronization and initialization pulses.

Two blocks of LUTs create the third circuit level. The block $BY$ is a circuit generating FSM functions of SBF (7). The block $B\tau$ generates expanded state codes $EC\left(a_m\right)$ as functions of additional variables $z_r\in Z$ and $v_r\in V$:

$$\tau =\tau (Z,V).$$

(22)

Using this preliminary information, we propose to represent a Moore FSM using the Moore FSM model $U_3$. The proposed structural diagram is shown in Figure 3.

Figure 3. Structural diagram of Moore FSM $U_3$.

The principle of operation of $U_3$ is clear from the previous text. In this paper, we propose a method for synthesizing the LUT-based circuit for FSM $U_3$. We assume that an FSM is representing its STT. If other representation forms are used, they should be converted to the equivalent STT. There are the following steps in the proposed method:

1.

Splitting the set of states by K classes of compatible states.

2.

Encoding of states $a_m\in A^k$ by partial state codes $PC\left(a_m\right)$.

3.

Finding the output collections $Y_q\subset Y$.

4.

Encoding of output collections in a way that minimizes SBF (7).

5.

Representing states by pairs <OC, identifier>.

6.

Encoding the identifiers and creating FSM codes $C\left(a_m\right)$.

7.

Constructing tables of blocks $Bk$ and finding SBFs (20).

8.

Constructing the table of block $BVZ$ and finding SBF (21).

9.

Constructing the table of block $B\tau$ and finding SBF (22).

10.

Implementing the FSM logic circuit using the internal resources of a particular FPGA chip.

All steps of the proposed method have polynomial complexity with respect to the number of FSM states and transitions, and therefore can be efficiently applied to FSMs of practical size without introducing scalability limitations.

As follows from our previous research [36], an FSM could belong to a complexity group. There are three groups of FSMs (trivial, complex, and very complex). Of course, we still discuss FPGA-based Moore FSMs. For a particular FSM, the group can be determined using such parameters as R, L, $L_m$, $S_L$. All these parameters have been already determined.

For trivial FSMs, there is no sense in using decomposition methods. Their circuits contain exactly $R+N$ LUTs. As follows from [36], the trivial FSMs satisfy the following condition:

$$R+L<2S_L.$$

(23)

For very complex FSMs, the following condition holds:

$$L_m\ge S_L.$$

(24)

For such FSMs, it is impossible to create the compatible classes of states. Because of the condition (24), LUTs do not have enough inputs for state variables. So, the FPGA-based circuits of very complex FSMs could be obtained using only FD-based methods.

If conditions (23) and (24) are violated, SD-based methods can be used to optimize the spatial characteristics of FSM circuits. Such FSMs belong to the group of complex FSMs. So, our method deals with complex Moore FSMs. The method is represented by a flow-chart (Figure 4). We hope this flowchart will help to understand the sequence of steps in the proposed design method.

Figure 4. Flowchart of the proposed method.

The first conditional node includes checking the condition (23). This is necessary to eliminate the trivial FSMs (output yes). If an FSM to be synthesized is not trivial (output no), then we should eliminate the very complex FSMs. This is checked using the condition (24) written in the second conditional node. The output yes shows that a particular FSM is very complex. The output no from the second conditional node indicates that a particular FSM is complex. So, it is necessary to execute the 10 steps shown in the operator nodes of the flowchart. These nodes include short commands taken from the list of steps shown above.

5. Example of Synthesis of Moore FSM ${\mathbf{U}}_{\mathbf{3}}$

As shown in the results of the experiment (Section 6), this method should be used for rather complex FSMs. Such a complex example cannot be presented within the scope of this paper. Due to this, we show only the principle of synthesis in this section. Let us discuss how to synthesize a LUT-based circuit of rather simple FSM $Ex1$ using the proposed method. To implement the FSM circuit, we use LUTs with $S_L=5$ inputs. The behavior of FSM Ex1 is represented by Table 2.

Table 2. State transition table of Moore FSM Ex1.

${\mathit{a}}_{\mathit{m}}$	${\mathit{a}}_{\mathit{s}}$	${\mathit{X}}_{\mathit{h}}$	h
$a_1(-)$	$a_2$	$x_1$	1
	$a_3$	$\overline{x_1}$	2
$a_2\left(y_1{y}_2\right)$	$a_3$	$x_2$	3
	$a_4$	$\overline{x_2}{x}_1$	4
	$a_5$	$\overline{x_2}\overline{x_1}$	5
$a_3\left(y_3\right)$	$a_4$	1	6
$a_4\left(y_2{y}_3\right)$	$a_6$	$x_3$	7
	$a_7$	$\overline{x_3}{x}_4$	8
	$a_4$	$\overline{x_3}\overline{x_4}$	9
$a_5\left(y_1{y}_2\right)$	$a_5$	$x_4$	10
	$a_8$	$\overline{x_4}$	11
$a_6\left(y_2{y}_3\right)$	$a_3$	$x_4$	12
	$a_8$	$\overline{x_4}{x}_3$	13
	$a_9$	$\overline{x_4}\overline{x_3}$	14
$a_7\left(y_4{y}_5\right)$	$a_7$	$x_1{x}_2$	15
	$a_8$	$x_1\overline{x_2}$	16
	$a_{10}$	$x_1$	17
$a_8\left(y_2{y}_4\right)$	$a_{10}$	$x_2$	18
	$a_1$	$\overline{x_2}$	19
$a_9\left(y_3\right)$	$a_3$	$x_3$	20
	$a_{10}$	$\overline{x_3}$	21
$a_{10}\left(y_2{y}_4\right)$	$a_4$	$x_4$	22
	$a_1$	$\overline{x_4}$	23

The following sets could be derived from Table 2: $A=\{a_1,$...$,a_{10}\}$, $X=\{x_1,$...$,x_4\}$ and $Y=\{y_1,$...$,y_5\}$. So, the FSM $Ex1$ has the following parameters: M = 10, L = 4, and N = 5. Table 2 includes H = 23 transitions $<a_m,a_s>$.

Step 1. To find the partition ${\mathrm{\Pi }}_E$, we use the greedy algorithm proposed in [47]. The main goal of the algorithm is to include as many possible states as possible into the classes $A^k\in {\mathrm{\Pi }}_E$.

The algorithm tries to minimize the number of FSM inputs determining transitions from states $a_m\in A^k$. As a result, the number of classes is minimized [47].

Using this approach in the discussed case, we can get the partition including $K=2$ classes: ${\mathrm{\Pi }}_E=\{A^1,A^2\}$. Each class $A^k\in {\mathrm{\Pi }}_E$ consists of five states: $A^1=\{a_1,a_2,a_3,a_7,a_8\}$ and $A^2=\{a_4,a_5,a_6,a_9,a_{10}\}$. The transitions from states $a_m\in A^1$ depend on FSM inputs $x_l\in X^1=\{x_1,x_2\}$. The transitions from states $a_m\in A^2$ depend on FSM inputs $x_l\in X^2=\{x_3,x_4\}$.

Step 2. In the discussed case, each class includes five states: $M_1=M_2=5$. Using (17) gives $R_1=R_2=3.$ This determines the sets of partial state variables ${\tau }^1=\{{\tau }_1,{\tau }_2,{\tau }_3\}$, ${\tau }^2=\{{\tau }_4,{\tau }_5,{\tau }_6\}$. These sets form the set $\tau =\{{\tau }_1,$...$,{\tau }_6\}$. The states $a_m\in A^1$($a_m\in A^2$) are encoded by codes $PC\left(a_m\right)$ using variables from the set ${\tau }^1$ (${\tau }^2$).

It is known [3] that partial state codes do not affect the number of LUTs in FSM circuit. So, we encode them as it is shown in Figure 5.

Figure 5. Partial state codes for classes $A^1$ (a) and $A^2$ (b).

In Karnaugh maps (Figure 5), we use the symbol ∉ to show that this code is reserved for all states $a_m\notin A^k$. This means that, for example, the following extended state codes can be obtained: $EC\left(a_1\right)=001000$, $EC\left(a_2\right)=010000$, $EC\left(a_4\right)=000001$, and so on.

Step 3. To create output collections $Y_q\subset Y$, it is enough to analyze the column of the current state. In the discussed case, analysis of Table 2 allows getting the output collections $Y_1=⌀$, $Y_2=\{y_1,y_2\}$, $Y_3=\left\{y_3\right\}$, $Y_4=\{y_2,y_3\}$,$Y_5=\{y_4,y_5\}$, and $Y_6=\{y_2,y_4\}$. This gives $Q=6.$ Using (5) gives $R_Q=3$. In turn, this defines a set $Z=\{z_1,z_2,z_3\}$. The variables $z_r\in Z$ are used to create codes $K\left(Y_q\right)$.

Step 4. The OCs should be encoded in a way that minimizes the SOPs of the FSM outputs. This could be done, for example, using the approach from [62]. Let us create a system of relations between outputs $y_n\in Y$ and OCs. These relations are represented by disjunctions of OCs. The relation $y_n\in Y_q$ adds the term $Y_q$ into the disjunction representing the output $y_n\in Y_q$. In the discussed case, the following SBF represents these relations:

$$\begin{array}{c}{y}_1=Y_2;\hfill \\ y_2=Y_2\vee Y_4\vee Y_6;\hfill \\ y_3=Y_3\vee Y_4;\hfill \\ y_4=Y_5\vee Y_6;\hfill \\ y_5=Y_5.\hfill \end{array}$$

(25)

For example, as follows from Table 2, the output $y_2$ is produced if FSM Ex1 should generate collections $Y_2,Y_4,Y_6$. So, SBF (25) should include the equation $y_2=Y_2\vee Y_4\vee Y_6.$ All other Equation (25) are constructed in the same way. To minimize the number of literals in the SOP of $y_2$, it is necessary to cover the codes $K\left(Y_2\right)$, $K\left(Y_4\right)$, and $K\left(Y_6\right)$ by the minimum possible number of generalized intervals of three-dimensional Boolean space. One of the possible outcomes of encoding is shown in Figure 6.

Figure 6. Outcome of encoding of COs.

In the common case, using SBF similar to (25) and codes $K\left(Y_q\right)$, SOPs for the system (7) could be created. Using SBF (25) and codes (Figure 6) gives the following system of SOPs:

$$\begin{array}{c}{y}_1=\overline{z_1}\overline{z_2}{z}_3;\hfill \\ y_2=z_3;\hfill \\ y_3=z_2;\hfill \\ y_4=z_1;\hfill \\ y_5=z_1\overline{z_3}.\hfill \end{array}$$

(26)

Analysis of (26) shows that its SOPs include 8 literals. Each literal corresponds to a connection between some LUT input and a source of $z_r\in Z$. So, the fewer literals in (7), the fewer interconnects an FSM circuit has. This allows reducing both the power consumption and required chip area [39].

In the worst case, the SBF (7) includes $R_{Q}N$ literals. In the discussed case, there is $R_{Q}N$ = 15. So, the proposed approach eliminates 7 literals (around 42% of literals).

The SBF (26) represents a circuit of $BY$. As we can see, three SOPs include only a single literal (SOPs for outputs $y_2,y_3,y_4$). So, to generate these outputs, there is no need for LUTs.

Step 5. To represent states using output collections and identifiers, it is necessary to analyze an STT. In our example, this is Table 2. For each OC $Y_q\subset Y$, we should create a set $A\left(Y_q\right)$. This set includes states in which a particular OC is generated. Analysis of Table 2 allows finding the following sets: $A\left(Y_1\right)=\left\{a_1\right\}$, $A\left(Y_2\right)=\{a_2,a_5\}$, $A\left(Y_3\right)=\{a_3,a_9\}$, $A\left(Y_4\right)=\{a_4,a_6\}$, $A\left(Y_5\right)=\left\{a_7\right\}$, $A\left(Y_6\right)=\{a_8,a_{10}\}$.

As follows from these sets, the maximum number of identifiers is equal to 2, whereas the minimum number is equal to 0. This analysis leads to the set of identifiers $I=\{I_1,I_2\}$. Instead of pairs, we represent states as concatenations of OCs and identifiers. One of the possible variants is the following:

$$\begin{array}{c}{a}_1=Y_1\ast \varnothing ;a_2=Y_2\ast I_1;\hfill \\ a_3=Y_3\ast I_1;a_4=Y_4\ast I_1;\hfill \\ a_5=Y_1\ast I_2;a_6=Y_4\ast I_2;\hfill \\ a_7=Y_5\ast \varnothing ;a_8=Y_6\ast I_1;\hfill \\ a_9=Y_3\ast I_2;a_{10}=Y_6\ast I_2.\hfill \end{array}$$

(27)

Step 6. There is $G=2$. Using (10) gives $R_I=1$. This determines the set $V=\left\{v_1\right\}$. Let us encode identifiers in the trivial way: $K\left(I_1\right)=0$ and $K\left(I_2\right)=1$. Using codes of OCs (Figure 6) and identifiers allows creating state codes (11). In the discussed case, we show codes $C\left(a_m\right)$ in Table 3.

Table 3. State codes for FSM Ex1.

${\mathit{a}}_{\mathit{m}}$	${\mathit{a}}_1$	${\mathit{a}}_2$	${\mathit{a}}_3$	${\mathit{a}}_4$	${\mathit{a}}_5$	${\mathit{a}}_6$	${\mathit{a}}_7$	${\mathit{a}}_8$	${\mathit{a}}_9$	${\mathit{a}}_{10}$
$z_1$	0	0	0	0	0	0	1	1	0	1
$z_2$	0	0	1	1	0	1	0	0	1	0
$z_3$	0	1	0	1	1	1	0	1	0	1
$v_1$	−	0	0	0	1	1	−	0	1	1

In the common case, such a table has $R_C$ rows and M columns. The rows are marked by variables $z_r\in Z$ and $v_r\in V$. The columns are marked by the states of Moore FSM. The following codes, for example, are derived from Table 3: $C\left(a_1\right)=000x$, $C\left(a_2\right)=0010$, and so on. We use the symbol «x» to denote the insignificant bit of a particular code.

Step 7. Tables of blocks $Bk$ are constructed using the initial STT, partial state codes $PC\left(a_m\right)$ and state codes $C\left(a_m\right)$ based on pairs <OC, identifier>. These tables consist of the following columns: $a_m$, $PC\left(a_m\right)$, $a_s$, $EC\left(a_s\right)$, $X_h$, $D_h$, h. There is no need to show OCs $Y_q\subset Y$ in the column of current state, because the system (7) is already created. Obviously, the relation $a_m\in A^k(k\in \{1,2\}$) is used to create the column of current states $a_m$.

To create the table of $B1$ (Table 4), it is necessary to use the rows 1–6 and 15–19 of STT (Table 2). The column $PC\left(a_m\right)$ is filled using the Karnaugh map (Figure 5a). To create the table of $B2$(Table 5), it is necessary to use the rows 7–14 and 20–23 of STT (Table 2). The column $PC\left(a_m\right)$ is filled using the Karnaugh map (Figure 5b).

Table 4. Table of block $B1$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{s}}$	$\mathit{C}\left({\mathit{a}}_{\mathit{s}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	h
$a_1$	001	$a_2$	0010	$x_1$	$D_3$	1
		$a_3$	0100	$\overline{x_1}$	$D_2$	2
$a_2$	010	$a_3$	0100	$x_2$	$D_2$	3
		$a_4$	0110	$\overline{x_2}{x}_1$	$D_2{D}_3$	4
		$a_5$	0011	$\overline{x_2}\overline{x_1}$	$D_3{D}_4$	5
$a_3$	011	$a_4$	0110	1	$D_2{D}_3$	6
$a_7$	100	$a_7$	1000	$x_1{x}_2$	$D_1$	7
		$a_8$	1010	$x_1\overline{x_2}$	$D_1{D}_3$	8
		$a_{10}$	1011	$\overline{x_1}$	$D_1{D}_3{D}_4$	9
$a_8$	101	$a_{10}$	1011	$x_2$	$D_1{D}_3{D}_4$	10
		$a_1$	0000	$\overline{x_2}$	−	11

Table 5. Table of block $B2$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{s}}$	$\mathit{C}\left({\mathit{a}}_{\mathit{s}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	h
$a_4$	001	$a_6$	0111	$x_3$	$D_2{D}_3{D}_4$	1
		$a_7$	1000	$\overline{x_3}{x}_4$	$D_1$	2
		$a_4$	0110	$\overline{x_3}\overline{x_4}$	$D_2{D}_3$	3
$a_5$	010	$a_5$	0011	$x_4$	$D_3{D}_4$	4
		$a_8$	1010	$\overline{x_4}$	$D_1{D}_3$	5
$a_6$	011	$a_3$	0100	$x_4$	$D_2$	6
		$a_8$	1010	$\overline{x_4}{x}_3$	$D_1{D}_3$	7
		$a_9$	0101	$\overline{x_4}\overline{x_3}$	$D_2{D}_4$	8
$a_9$	100	$a_3$	0100	$x_3$	$D_2$	9
		$a_{10}$	1011	$\overline{x_3}$	$D_1{D}_3{D}_4$	10
$a_{10}$	101	$a_4$	0110	$x_4$	$D_2{D}_3$	11
		$a_2$	0000	$\overline{x_4}$	−	12

These tables are used for deriving SBFs (20). Let us show only two partial IMFs, $D_1^1$ and $D_1^2$. These partial IMFs are represented by the following SBF:

$$\begin{array}{c}{D}_1^1=F_7\vee F_8\vee F_9\vee F_{10}={\tau }_1\overline{{\tau }_3}\vee {\tau }_1{\tau }_2{x}_2;\hfill \\ D_2^2=F_2\vee F_5\vee F_7\vee F_{10}=\overline{{\tau }_4}\overline{{\tau }_5}{\tau }_6\overline{x_3}{x}_4\vee \overline{{\tau }_4}{\tau }_5{\tau }_6\overline{x_4}\vee \overline{{\tau }_4}{\tau }_5{\tau }_6\overline{x_4}{x}_3\vee {\tau }_4\overline{{\tau }_5}\overline{{\tau }_6}\overline{x_3}.\hfill \end{array}$$

(28)

In (28), the symbol $F_h$ stands for a product term corresponding to the h-th line of a particular table. For example, the first line of Table 4 determines the term $F_1=\overline{{\tau }_1}{\overline{\tau }}_2{\tau }_3{x}_1$. The first line of Table 5 determines the term $F_1=\overline{{\tau }_4}{\overline{\tau }}_5{\tau }_6{x}_3$.

Step 8. The block $BZV$ includes both combinational part (LUTs) and memory (flip-flops of RG). The combinational part is a circuit generating IMFs (21). The memory part registered these functions, which represent additional variables $z_r\in Z$ and $v_r\in V$. A table of block $BZV$ has $R_C+1$ columns and K rows. The first column includes the classes $A^k$. Other columns are marked by IMFs $D_r\in D$. If some IMF $D_r^k\in A^k$ presents in the table of block $Bk$, then the symbol «1» is written on the intersection of the row $A^k$ and the column $D_r$. If some IMF $D_r^k\in A^k$ is absent in the table of block $Bk$, then the symbol «0» is written on the intersection of the row $A^k$ and the column $D_r$. Analysis of Table 4 shows that its column $D_h$ includes all $R_C=4$ partial IMFs. The same is true for Table 5. Using this information, we can create the table of block $BZV$ for our example (Table 6).

Table 6. Table of block $BVZ$.

$\mathit{Class}$	${\mathit{D}}_1$	${\mathit{D}}_2$	${\mathit{D}}_3$	${\mathit{D}}_4$
$A^1$	1	1	1	1
$A^2$	1	1	1	1

Using Table 6 gives the final values of IMFs (21). The following system of disjunctions is constructed on the base of Table 6:

$$\begin{array}{c}{D}_1=D_1^1\vee D_1^2;D_2=D_2^1\vee D_2^2;\hfill \\ D_3=D_3^1\vee D_3^2;D_4=D_4^1\vee D_4^2.\hfill \end{array}$$

(29)

Step 9. The table of block $B\tau$ shows the dependence between codes $C\left(a_m\right)$ and extended state codes $EC\left(a_m\right)$. This table should include the columns $a_m$ (all states are included in this column), $C\left(a_m\right)$, $EC\left(a_m\right)$, ${\tau }_m$ (partial state variables equal to 1 in the extended state code from the $m-th$ line of the table), m. Using state codes (Table 3) and extended state codes (concatenations of partial codes from Karnaugh maps shown in Figure 5), we can create Table 7 representing the block $B\tau$.

Table 7. Table of block $B\tau$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{C}\left({\mathit{a}}_{\mathit{m}}\right)$	$\mathit{E}\mathit{C}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{\tau }}_{\mathit{m}}$	m
$a_1$	$000\ast$	001000	${\tau }_3$	1
$a_2$	0010	010000	${\tau }_2$	2
$a_3$	0100	011000	${\tau }_2{\tau }_3$	3
$a_4$	0110	000001	${\tau }_6$	4
$a_5$	0011	000010	${\tau }_5$	5
$a_6$	0111	000011	${\tau }_5{\tau }_6$	6
$a_7$	$100\ast$	100000	${\tau }_1$	7
$a_8$	1010	101000	${\tau }_1{\tau }_3$	8
$a_9$	0101	000100	${\tau }_4$	9
$a_{10}$	1011	000101	${\tau }_4{\tau }_6$	10

Using Table 7 gives the following SOPs representing partial state variables:

$$\begin{array}{c}{\tau }_1=A_7\vee A_8=z_1\overline{z_2}\overline{v_1};\hfill \\ {\tau }_2=A_2\vee A_3=\overline{z_1}\overline{z_2}{z}_3\overline{v_1}\vee \overline{z_1}{z}_2\overline{z_3}\overline{v_1};\hfill \\ {\tau }_3=A_1\vee A_3\vee A_8=\overline{z_1}\overline{z_3}\overline{v_1}\vee z_1\overline{z_2}{z}_3\overline{v_1};\hfill \\ {\tau }_4=A_9\vee A_{10}=\overline{z_1}{z}_2\overline{z_3}{v}_1\vee z_1\overline{z_2}{z}_3{v}_1;\hfill \\ {\tau }_5=A_5\vee A_6=\overline{z_1}{z}_3{v}_1;\hfill \\ {\tau }_6=A_4\vee A_6\vee A_{10}=\overline{z_1}{z}_2{z}_3\vee z_1\overline{z_2}{z}_3{v}_1.\hfill \end{array}$$

(30)

Let us explain, for example, how the SOP of ${\tau }_1$ is created. This variable is written in rows 7 and 8 of Table 7. This gives the function ${\tau }_1=A_7\vee A_8$, where the term $A_m$ is a conjunction of variables $z_r\in Z$ and $v_r\in V$ (or their complements) corresponding to $C\left(a_m\right)$. To minimize this function, we should use the code 1000 for $A_7$. This gives $A_7=z_1\overline{z_2}\overline{z_3}\overline{v_1}$. Also, there is $A_8=z_1\overline{z_2}{z}_3\overline{v_1}$. The disjunction of these terms does not include the variable $z_3$. This gives the final expression ${\tau }_1=z_1\overline{z_2}\overline{v_1}$ which is present in (30). In the same manner, all other equations from (30) are obtained.

Step 10. To implement an LUT-based FSM circuit using FPGAs from AMD Xilinx, we should use, for example, the industrial-grade Vivado [45]. This package does not support LUTs with $S_L=5$. So, we have no way to show the outcome of the implementation in our example. But we present many outcomes in the next section.

6. Experimental Results

We investigated the efficiency of the proposed method using standard benchmarks from the library [63]. This library consists of 53 benchmark Mealy FSMs taken from the practice of logic design. These benchmarks are very often used by different researchers to compare new and known results [52,59,64]. The benchmarks are represented using KISS2 files. To conduct the research, we transform these files into equivalent Moore FSMs. The transformation was executed using approach [20]. In Table 8, the main characteristics of the obtained Moore FSMs are shown. The last column of Table 8 includes the result of the summation for the number of inputs and state variables.

Table 8. Characteristics of Moore FSMs.

Benchmark	L	N	M	H	${\mathit{R}}_{\mathit{m}}$	$\mathit{L}+\mathit{R}$
bbara	4	2	12	72	4	8
bbsse	7	7	23	104	5	12
bbtas	2	2	9	36	4	6
beecount	3	4	10	40	4	7
cse	7	7	32	183	5	12
dk14	3	5	26	208	5	8
dk15	3	5	17	136	5	8
dk16	2	3	75	300	7	9
dk17	2	3	16	64	4	6
dk27	1	2	10	20	4	5
dk512	1	3	23	48	5	6
donfile	2	1	25	100	5	7
ex1	9	19	80	637	7	16
ex2	2	2	25	92	5	7
ex3	2	2	14	44	4	6
ex4	6	9	17	28	5	11
ex5	2	2	16	52	4	6
ex6	5	8	13	61	4	9
ex7	2	2	17	56	5	7
keyb	7	2	22	193	5	12
kirkman	12	6	139	3817	8	20
lion	2	1	5	14	3	5
lion9	2	1	11	31	4	6
mark1	5	16	21	29	5	10
mc	3	5	8	20	3	6
modulo12	1	1	13	26	4	5
opus	5	6	10	22	4	9
planet	7	19	103	248	7	14
planet1	7	19	103	248	7	14
pma	8	8	49	132	6	14
s1	8	6	20	107	5	13
s1488	8	19	168	912	8	16
s1494	8	19	168	1030	8	16
s1a	8	6	21	115	5	13
s208	11	2	36	309	6	17
s27	4	1	6	34	3	7
s298	3	6	332	1669	9	12
s386	7	7	23	127	5	12
s420	19	2	36	282	6	25
s510	19	7	73	133	7	26
s8	4	1	6	24	3	7
s820	18	19	70	613	7	25
s832	18	19	70	707	7	25
sand	11	9	88	654	7	18
scf	27	56	138	190	8	35
shiftreg	1	1	16	32	4	5
sse	7	7	23	104	5	12
styr	9	10	57	366	6	15
tav	4	4	27	322	5	9
tbk	6	3	60	2942	6	12
tma	7	6	38	72	6	13
train11	2	1	14	34	4	6
train4	2	1	6	21	3	5

To translate KISS2 –based files into VHDL-based FSM models, we use our CAD tool K2F [47]. To synthesize and simulate FSMs, the Active-HDL environment is used. To get FSM circuits, we used Vivado v2025. 1 [45]. The FPGA chip Virtex7 Ultrascale+ xcvu29p-fsga2577-2L-e [41] was used as a target platform. This chip includes LUTs with 6 inputs. Eight such LUTs are placed into a single CLB. Using dedicated multiplexers, it is possible to create super-LUTs having either 7 (four 7-input LUTs), or 8 (two 8-input LUTs), or 9 inputs (one 9-input LUT). To create a 7-input LUT, the multiplexers F7 MUX are used. To create an 8-input LUT, the multiplexers F8 MUX are used. To create a 9-input LUT, the multiplexers F9 MUX are used.

We take three other methods to compare with the proposed approach. These methods are as follows: (1) Auto of Vivado; (2) One-hot of Vivado; (3) Gray of Vivado. The results of experiments are shown in Table 9 (Auto), Table 10 (One-hot), Table 11 (Gray), and Table 12 ($U_3$). Each table contains the following columns: Benchmark, LUTs (the number of LUTs having 6 inputs), F7 MUX (the number of multiplexers used for creating super-LUTs with 7 inputs), F8 MUX (the number of multiplexers used for creating super-LUTs with 8 inputs), Registers (the number of D flip-flops used for creating the state register), Delay (the time of cycle), Freq. (the maximum operating frequency), Power (the value of consumed power).

Table 9. Experimental results for Auto-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	18	4	2	4	3.22	310.56	3.556
bbsse	38	4	0	5	2.868	348.68	7.879
bbtas	6	0	0	4	2.515	397.61	3.714
beecount	12	4	0	4	2.672	374.25	5.816
cse	94	0	0	32	2.96	337.84	3.096
dk14	42	0	0	26	3.525	283.69	7.520
dk15	17	0	0	5	2.693	371.33	9.031
dk16	69	26	0	7	3.303	302.76	7.889
dk17	7	0	0	4	2.471	404.69	6.473
dk27	7	0	0	10	3.051	327.76	4.116
dk512	15	0	0	21	3.017	331.46	4.752
donfile	11	5	0	5	2.553	391.70	3.631
ex1	198	28	3	7	4.499	222.27	19.744
ex2	5	0	0	4	2.823	354.23	3.985
ex3	6	0	0	4	2.546	392.77	4.559
ex4	18	0	0	17	2.753	363.24	3.378
ex5	5	0	0	4	2.798	357.40	4.208
ex6	21	1	0	4	3.67	272.48	13.531
ex7	5	0	0	4	2.798	357.40	4.220
keyb	35	7	0	5	3.082	324.46	3.489
kirkman	1197	0	0	139	7.247	137.99	17.279
lion	5	0	0	5	2.64	378.79	2.784
lion9	12	0	0	11	3.206	311.92	2.927
mark1	25	0	0	5	3.214	311.14	14.267
mc	5	0	0	3	2.682	372.86	7.599
modulo12	7	0	0	13	2.283	438.02	2.720
opus	16	1	0	4	2.531	395.10	6.430
planet	200	0	0	103	4.907	203.79	12.025
planet1	200	0	0	103	4.907	203.79	12.025
pma	217	0	0	49	4.832	206.95	4.605
s1	87	0	0	20	3.517	284.33	6.156
s1488	1449	0	0	168	6.057	165.10	17.491
s1494	305	33	2	11	5.175	193.24	25.468
s1a	83	0	0	21	2.756	362.84	9.054
s208	55	4	0	6	3.332	300.12	4.770
s27	6	2	0	3	2.546	392.77	3.745
s298	621	188	82	37	4.637	215.66	20.917
s386	39	3	0	5	3.161	316.36	6.448
s420	33	0	0	6	3.35	298.51	4.010
s510	66	10	1	7	3.194	313.09	8.229
s8	7	3	0	3	2.467	405.35	3.964
s820	165	20	4	7	3.956	252.78	10.493
s832	147	22	6	7	4.419	226.30	11.524
sand	516	0	0	88	5.513	181.39	8.976
scf	744	0	0	135	8.209	121.82	8.519
shiftreg	11	0	0	16	2.565	389.86	3.397
sse	38	4	0	5	2.868	348.68	7.879
styr	123	16	3	6	3.839	260.48	12.645
tav	42	0	0	27	3.006	332.67	4.621
tbk	139	10	0	6	3.532	283.13	5.132
tma	124	0	0	38	3.858	259.20	4.127
train11	14	0	0	14	3.196	312.89	2.879
train4	3	0	0	3	2.638	379.08	3.320
Total	7330	395	103	1250	186.057	16,382.55	401.012

Table 10. Experimental results for One-hot-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	17	0	0	12	2.494	400.96	2.723
bbsse	27	0	0	23	2.560	390.63	3.712
bbtas	9	0	0	9	2.531	395.10	2.805
beecount	18	0	0	10	3.554	281.37	3.705
cse	55	0	0	32	2.774	360.49	3.568
dk14	31	0	0	26	3.355	298.06	5.732
dk15	20	0	0	17	2.788	358.68	5.052
dk16	84	0	0	75	3.169	315.56	6.961
dk17	18	0	0	16	2.927	341.65	5.409
dk27	7	0	0	10	3.051	327.76	4.116
dk512	15	0	0	21	3.017	331.46	4.752
donfile	31	0	0	25	2.870	348.43	3.222
ex1	143	0	0	80	4.121	242.66	4.490
ex2	11	1	0	14	2.562	390.32	2.690
ex3	12	1	0	13	2.542	393.39	2.667
ex4	18	0	0	17	2.753	363.24	3.378
ex5	12	0	0	14	2.599	384.76	2.798
ex6	23	0	0	13	3.074	325.31	7.555
ex7	6	0	0	7	2.666	375.09	2.584
keyb	36	0	0	22	3.669	272.55	3.364
kirkman	267	0	0	139	4.777	209.34	5.048
lion	5	0	0	5	2.640	378.79	2.784
lion9	12	0	0	11	3.206	311.92	2.927
mark1	19	0	0	20	3.743	267.17	3.040
mc	10	0	0	8	2.736	365.50	3.735
modulo12	7	0	0	13	2.283	438.02	2.720
opus	16	0	0	10	3.463	288.77	3.900
planet	147	0	0	103	4.037	247.71	13.386
planet1	147	0	0	103	4.037	247.71	13.386
pma	83	0	0	49	3.325	300.75	5.049
s1	42	0	0	20	3.558	281.06	6.741
s1488	232	0	0	168	5.113	195.58	7.025
s1494	232	0	0	168	5.847	171.03	7.043
s1a	36	0	0	21	3.051	327.76	2.868
s208	61	0	0	36	2.873	348.07	3.343
s27	10	0	0	6	2.446	408.83	3.256
s298	1143	14	0	341	9.276	107.81	11.008
s386	29	0	0	23	2.684	372.58	3.661
s420	62	0	0	36	3.920	255.10	3.331
s510	64	0	0	73	4.597	217.53	5.757
s8	11	0	0	6	2.446	408.83	2.787
s820	103	0	0	70	3.665	272.85	4.908
s832	104	0	0	70	3.531	283.21	4.918
sand	136	0	0	88	4.387	227.95	7.000
scf	111	0	0	135	6.787	147.34	4.952
shiftreg	11	0	0	16	2.565	389.86	3.397
sse	27	0	0	23	2.560	390.63	3.712
styr	91	0	0	57	3.629	275.56	4.056
tav	31	0	0	27	3.569	280.19	3.722
tbk	152	0	0	60	3.445	290.28	5.132
tma	59	0	0	38	4.009	249.44	3.482
train11	14	0	0	14	3.196	312.89	2.879
train4	5	0	0	6	2.671	374.39	2.828
Total	4072	16	0	2419	183.148	16,541.89	243.55

Table 11. Experimental results for Gray-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	18	0	0	4	2.716	368.19	3.300
bbsse	36	3	0	5	2.636	379.36	7.750
bbtas	6	0	0	4	2.583	387.15	3.600
beecount	12	4	0	4	2.855	350.26	5.899
cse	55	10	0	5	3.059	326.90	5.155
dk14	25	10	5	5	2.854	350.39	9.755
dk15	20	0	0	5	3.453	289.60	8.376
dk16	70	22	0	7	3.758	266.10	7.730
dk17	7	0	0	4	2.537	394.17	6.233
dk27	4	0	0	4	2.725	366.97	3.897
dk512	8	0	0	5	2.612	382.85	4.473
donfile	11	5	0	5	3.077	324.99	3.579
ex1	177	27	0	7	3.526	283.61	18.548
ex2	5	0	0	4	2.720	367.65	2.953
ex3	6	0	0	4	2.517	397.30	4.521
ex4	22	0	0	5	2.687	372.16	5.824
ex5	5	0	0	4	2.823	354.23	4.232
ex6	19	2	0	4	2.664	375.38	12.036
ex7	5	0	0	4	2.823	354.23	3.593
keyb	42	5	1	5	3.221	310.46	4.324
kirkman	377	53	9	8	5.990	166.94	14.522
lion	3	0	0	3	2.638	379.08	2.754
lion9	5	0	0	4	2.549	392.31	2.775
mark1	29	0	0	5	2.845	351.49	8.345
mc	6	0	0	3	2.659	376.08	5.522
modulo12	3	0	0	4	2.362	423.37	2.630
opus	18	0	0	4	2.863	349.28	4.560
planet	129	33	0	7	3.411	293.17	20.657
planet1	129	33	0	7	3.411	293.17	20.657
pma	73	6	0	6	2.874	347.95	12.260
s1	53	7	0	5	3.089	323.73	10.869
s1488	291	33	2	10	5.280	189.39	26.114
s1494	293	31	1	10	5.670	176.37	26.202
s1a	49	9	1	5	3.257	307.03	5.447
s208	45	5	0	6	2.791	358.29	5.388
s27	7	3	0	3	2.456	407.17	3.696
s298	607	198	79	39	4.373	228.68	21.491
s386	36	4	0	5	2.642	378.50	7.201
s420	60	12	3	6	2.972	336.47	4.179
s510	51	4	1	7	4.080	245.10	8.502
s8	7	3	0	3	2.453	407.66	3.594
s820	151	27	7	7	3.662	273.07	10.973
s832	145	24	5	7	4.168	239.92	10.298
sand	125	19	0	7	3.278	305.06	11.072
scf	194	19	1	8	8.929	111.99	25.147
shiftreg	3	0	0	4	2.362	423.37	3.989
sse	36	3	0	5	2.636	379.36	7.750
styr	97	14	1	6	3.026	330.47	10.220
tav	25	5	0	5	3.094	323.21	7.392
tbk	136	14	0	6	3.812	262.33	6.286
tma	53	7	0	6	2.772	360.75	9.646
train11	5	0	0	4	2.584	387.00	2.748
train4	2	0	0	3	2.441	409.67	2.923
Total	3796	654	116	312	171.275	17,539.40	451.587

Table 12. Experimental results for $U_3$-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	17	0	0	4	2.716	368.19	2.723
bbsse	27	3	0	5	2.636	379.36	3.712
bbtas	6	0	0	4	2.583	387.15	3.600
beecount	12	4	0	4	2.855	350.26	5.899
cse	55	10	0	5	3.059	326.90	5.155
dk14	25	10	5	5	2.854	350.39	9.755
dk15	20	0	0	5	3.453	289.60	8.376
dk16	70	22	0	7	3.758	266.10	7.730
dk17	7	0	0	4	2.537	394.17	6.233
dk27	4	0	0	4	2.725	366.97	3.897
dk512	8	0	0	5	2.612	382.85	4.473
donfile	11	5	0	5	3.077	324.99	3.579
ex1	139	14	0	7	2.821	354.48	4.040
ex2	5	0	0	4	2.720	367.65	2.953
ex3	6	0	0	4	2.517	397.30	4.521
ex4	18	0	0	5	2.687	372.16	3.378
ex5	5	0	0	4	2.823	354.23	4.232
ex6	19	2	0	4	2.664	375.38	12.036
ex7	5	0	0	4	2.823	354.23	3.593
keyb	36	5	1	5	3.221	310.46	3.090
kirkman	251	28	2	8	4.792	208.68	4.732
lion	3	0	0	3	2.638	379.08	2.754
lion9	5	0	0	4	2.549	392.31	2.775
mark1	19	0	0	5	2.845	351.49	3.040
mc	6	0	0	3	2.659	376.08	5.522
modulo12	3	0	0	4	2.362	423.37	2.630
opus	16	0	0	4	2.863	349.28	3.900
planet	111	14	0	9	2.762	362.06	12.315
planet1	111	14	0	9	2.762	362.06	12.315
pma	65	3	0	6	2.327	429.74	4.740
s1	40	3	0	5	2.532	394.94	6.471
s1488	225	15	0	8	4.220	236.97	6.674
s1494	218	15	0	8	4.536	220.46	6.761
s1a	34	3	0	5	2.671	374.39	2.696
s208	41	2	0	6	2.232	448.03	3.243
s27	7	3	0	3	2.456	407.17	3.696
s298	555	112	14	9	3.498	285.88	10.567
s386	36	4	0	5	2.642	378.50	7.201
s420	60	12	3	6	2.972	336.47	4.179
s510	51	4	1	7	4.080	245.10	8.502
s8	7	3	0	3	2.453	407.66	3.594
s820	103	27	7	7	3.662	273.07	4.908
s832	104	24	5	7	4.168	239.92	4.918
sand	125	19	0	7	3.278	305.06	11.072
scf	111	19	1	8	8.929	111.99	4.952
shiftreg	3	0	0	4	2.362	423.37	3.989
sse	31	0	0	5	2.615	382.41	6.960
styr	86	6	0	6	2.481	403.06	9.198
tav	25	5	0	5	3.094	323.21	7.392
tbk	136	14	0	6	3.812	262.33	6.286
tma	47	3	0	6	2.772	360.75	8.575
train11	5	0	0	4	2.584	387.00	2.748
train4	2	0	0	3	2.441	409.67	2.923
Total	3137	427	39	282	162.19	18,324.40	295.203

Power consumption values were obtained using the standard power estimation flow provided by the Vivado design environment. The estimates were generated under uniform default assumptions regarding clock frequency, signal switching activity, and operating conditions, without applying benchmark-specific activity files or custom input vector activity. This methodology ensures consistent conditions across all evaluated benchmarks and synthesis variants, enabling a relative comparison of power trends across different FSM implementations. While absolute power values may vary depending on switching activity assumptions, the reported results are intended to illustrate comparative power behavior under identical estimation settings.

Using (23) and (24) allows dividing the benchmarks by three groups: trivial, complex, and very complex. For trivial benchmarks, the following condition takes place: $L+R\le 12$. For complex FSMs, this condition is violated. However, the group of complex FSMs includes benchmarks that are too complex for our method. Our experience tells that these benchmarks include states for which the sum of significant FSM inputs exceeds the value of $S_L(L_m>6)$.

The group of complex FSMs includes the following benchmarks: ex1, kirkman, planet, planet1, pma, s1, s1488, s1494, s1a, s208, s298, styr, tma. The group of very complex FSMs includes the benchmarks s420, s510, s820, s832, sand, scf. All other benchmarks create the group of trivial FSMs. So, there are 13 complex FSMs, 6 very complex FSMs, and 34 trivial FSMs in the library [63].

There is no sense in using our method for trivial FSMs. For trivial benchmarks, it is better to use either One-hot- or Grey-based approaches. The same is true for very complex FSMs. The following rule is used to fill Table 12: for trivial and very complex FSMs, we should take the best results among either One-hot- or Grey-based approaches.

Using Table 9, Table 10, Table 11 and Table 12, we created Table 13, Table 14 and Table 15 to compare the basic characteristics of obtained circuits (the LUT count, operating frequency, and power consumed). These tables are organized in the same order. The rows are marked by benchmark names, and the columns by design methods. The row “Total” includes the sum of the corresponding values. The summarized characteristics of U₃-based FSMs are taken as 100%. The row “Percentage” shows the percentage of summarized characteristics, respectively, to benchmarks based on U₃.

Table 13. Experimental results (LUT count).

Benchmark	Auto	One-Hot	Gray	${\mathit{U}}_3$
bbara	18	17	18	17
bbsse	38	27	36	27
bbtas	6	9	6	6
beecount	12	18	12	12
cse	94	55	55	55
dk14	42	31	25	25
dk15	17	20	20	20
dk16	69	84	70	70
dk17	7	18	7	7
dk27	7	7	4	4
dk512	15	15	8	8
donfile	11	31	11	11
ex1	198	143	177	139
ex2	5	11	5	5
ex3	6	12	6	6
ex4	18	18	22	18
ex5	5	12	5	5
ex6	21	23	19	19
ex7	5	6	5	5
keyb	35	36	42	36
kirkman	1197	267	377	251
lion	5	5	3	3
lion9	12	12	5	5
mark1	25	19	29	19
mc	5	10	6	6
modulo12	7	7	3	3
opus	16	16	18	16
planet	200	147	129	111
planet1	200	147	129	111
pma	217	83	73	65
s1	87	42	53	40
s1488	1449	232	291	225
s1494	305	232	293	218
s1a	83	36	49	34
s208	55	61	45	41
s27	6	10	7	7
s298	621	1143	607	555
s386	39	29	36	36
s420	33	62	60	60
s510	66	64	51	51
s8	7	11	7	7
s820	165	103	151	103
s832	147	104	145	104
sand	516	136	125	125
scf	744	111	194	111
shiftreg	11	11	3	3
sse	38	27	36	31
styr	123	91	97	86
tav	42	31	25	25
tbk	139	152	136	136
tma	124	59	53	47
train11	14	14	5	5
train4	3	5	2	2
Total	7330	4072	3796	3137
Percentage, %	233.66	129.81	121.01	100.00

Table 14. Experimental results (maximum operating frequency, MHz).

Benchmark	Auto	One-Hot	Gray	${\mathit{U}}_3$
bbara	310.56	400.96	368.19	368.19
bbsse	348.68	390.63	379.36	379.36
bbtas	397.61	395.10	387.15	387.15
beecount	374.25	281.37	350.26	350.26
cse	337.84	360.49	326.90	326.90
dk14	283.69	298.06	350.39	350.39
dk15	371.33	358.68	289.60	289.60
dk16	302.76	315.56	266.10	266.10
dk17	404.69	341.65	394.17	394.17
dk27	327.76	327.76	366.97	366.97
dk512	331.46	331.46	382.85	382.85
donfile	391.70	348.43	324.99	324.99
ex1	222.27	242.66	283.61	354.48
ex2	354.23	390.32	367.65	367.65
ex3	392.77	393.39	397.30	397.30
ex4	363.24	363.24	372.16	372.16
ex5	357.40	384.76	354.23	354.23
ex6	272.48	325.31	375.38	375.38
ex7	357.40	375.09	354.23	354.23
keyb	324.46	272.55	310.46	310.46
kirkman	137.99	209.34	166.94	208.68
lion	378.79	378.79	379.08	379.08
lion9	311.92	311.92	392.31	392.31
mark1	311.14	267.17	351.49	351.49
mc	372.86	365.50	376.08	376.08
modulo12	438.02	438.02	423.37	423.37
opus	395.10	288.77	349.28	349.28
planet	203.79	247.71	293.17	362.06
planet1	203.79	247.71	293.17	362.06
pma	206.95	300.75	347.95	429.74
s1	284.33	281.06	323.73	394.94
s1488	165.10	195.58	189.39	236.97
s1494	193.24	171.03	176.37	220.46
s1a	362.84	327.76	307.03	374.39
s208	300.12	348.07	358.29	448.03
s27	392.77	408.83	407.17	407.17
s298	215.66	107.81	228.68	285.88
s386	316.36	372.58	378.50	378.50
s420	298.51	255.10	336.47	336.47
s510	313.09	217.53	245.10	245.10
s8	405.35	408.83	407.66	407.66
s820	252.78	272.85	273.07	273.07
s832	226.30	283.21	239.92	239.92
sand	181.39	227.95	305.06	305.06
scf	121.82	147.34	111.99	111.99
shiftreg	389.86	389.86	423.37	423.37
sse	348.68	390.63	379.36	382.41
styr	260.48	275.56	330.47	403.06
tav	332.67	280.19	323.21	323.21
tbk	283.13	290.28	262.33	262.33
tma	259.20	249.44	360.75	360.75
train11	312.89	312.89	387.00	387.00
train4	379.08	374.39	409.67	409.67
Total	16,382.55	16,541.89	17,539.40	18,324.40
Percentage, %	89.40	90.27	95.72	100.00

Table 15. Experimental results (power consumption, W).

Benchmark	Auto	One-Hot	Gray	${\mathit{U}}_3$
bbara	3.556	2.723	3.300	2.723
bbsse	7.879	3.712	7.750	3.712
bbtas	3.714	2.805	3.600	3.600
beecount	5.816	3.705	5.899	5.899
cse	3.096	3.568	5.155	5.155
dk14	7.520	5.732	9.755	9.755
dk15	9.031	5.052	8.376	8.376
dk16	7.889	6.961	7.730	7.730
dk17	6.473	5.409	6.233	6.233
dk27	4.116	4.116	3.897	3.897
dk512	4.752	4.752	4.473	4.473
donfile	3.631	3.222	3.579	3.579
ex1	19.744	4.490	18.548	4.040
ex2	3.985	2.690	2.953	2.953
ex3	4.559	2.667	4.521	4.521
ex4	3.378	3.378	5.824	3.378
ex5	4.208	2.798	4.232	4.232
ex6	13.531	7.555	12.036	12.036
ex7	4.220	2.584	3.593	3.593
keyb	3.489	3.364	4.324	3.090
kirkman	17.279	5.048	14.522	4.732
lion	2.784	2.784	2.754	2.754
lion9	2.927	2.927	2.775	2.775
mark1	14.267	3.040	8.345	3.040
mc	7.599	3.735	5.522	5.522
modulo12	2.720	2.720	2.630	2.630
opus	6.430	3.900	4.560	3.900
planet	12.025	13.386	20.657	12.315
planet1	12.025	13.386	20.657	12.315
pma	4.605	5.049	12.260	4.740
s1	6.156	6.741	10.869	6.471
s1488	17.491	7.025	26.114	6.674
s1494	25.468	7.043	26.202	6.761
s1a	9.054	2.868	5.447	2.696
s208	4.770	3.343	5.388	3.243
s27	3.745	3.256	3.696	3.696
s298	20.917	11.008	21.491	10.567
s386	6.448	3.661	7.201	7.201
s420	4.010	3.331	4.179	4.179
s510	8.229	5.757	8.502	8.502
s8	3.964	2.787	3.594	3.594
s820	10.493	4.908	10.973	4.908
s832	11.524	4.918	10.298	4.918
sand	8.976	7.000	11.072	11.072
scf	8.519	4.952	25.147	4.952
shiftreg	3.397	3.397	3.989	3.989
sse	7.879	3.712	7.750	6.960
styr	12.645	4.056	10.220	9.198
tav	4.621	3.722	7.392	7.392
tbk	5.132	3.618	6.286	6.286
tma	4.127	3.482	9.646	8.575
train11	2.879	2.879	2.748	2.748
train4	3.320	2.828	2.923	2.923
Total	401.012	243.550	451.587	295.203
Percentage, %	135.84	82.50	152.98	100.00

As shown in Table 13, the U₃-based FSMs required fewer LUTs than those for other investigated methods. There is the following economy: (1) 133% regarding Auto; (2) 29% regarding One-hot, and (3) 21% regarding Grey-based FSMs. As a rule, our approach gives better results for FSMs where condition (4) is violated and conditions (8) and (9) have places.

As shown in Table 14, the U₃-based FSMs have a higher operating frequency than the other investigated methods. There is the following gain: (1) 10.6% regarding Auto; (2) 9.73% regarding One-hot, and (3) 4.28% regarding Gray-based FSMs. The gain is increased for complex FSMs. We think that, for complex FSMs, the proposed approach produces circuits with fewer levels and shorter interconnection networks.

Our approach allows producing circuits with a more regular interconnect system. Interconnections are known to be responsible for up to 70% of energy losses in FPGA-based circuits [26,65,66]. Due to the regularization of interconnections, our approach results in lower energy consumption than other investigated methods. As shown in Table 15, the One-hot-based FSMs consume less power than U₃-based FSMs. But our method provides economy compared with both Auto-based (35.84%) and Gray-based (52.98%) FSMs.

Also, we created two tables that compare all FSM characteristics. Table 16 shows the comparison for all benchmarks. Table 17 shows a comparison for complex FSMs.

Table 16. Total results for all benchmarks.

	Auto	One-Hot	Gray	${\mathit{U}}_3$
Total LUTs	7330	4072	3796	3137
Percentage LUTs, %	233.66	129.81	121.01	100.00
Total Registers	1250	2419	312	282
Percentage Registers, %	443.26	857.80	110.64	100.00
Total Frequency	16,382.55	16,541.89	17,539.40	18,324.40
Percentage Frequency, %	89.40	90.27	95.72	100.00
Total Power	401.012	243.55	451.587	295.203
Percentage Power, %	135.84	82.50	152.98	100.00

Table 17. Total results for complex FSMs.

	Auto	One-Hot	Gray	${\mathit{U}}_3$
Total LUTs	4897	2710	2409	1954
Percentage LUTs, %	250.61	138.69	123.29	100.00
Total Registers	713	1346	127	97
Percentage Registers, %	735.05	1387.63	130.93	100.00
Total Frequency	3364.45	3595.09	4038.91	4823.91
Percentage Frequency, %	69.75	74.53	83.73	100.00
Total Power	174.185	90.637	209.771	99.287
Percentage Power, %	175.44	91.29	211.28	100.00

As shown in the comparison of Table 16 and Table 17, the One-hot-based FSMs are the winners in terms of power consumption. We think that this is connected with the fact that each state of One-hot-based FSMs is represented by an unique flip-flop. In our method, states are encoded to minimize the number of arguments in the Boolean functions representing FSM outputs.

But the proposed method provides the significant improvement for spatial (chip area occupied by FSM circuit) and frequency. As shown in Table 17, U₃-based complex FSMs require fewer LUTs than those for other investigated methods. There is the following economy: (1) 150.61% regarding Auto; (2) 38.69% regarding One-hot and (3) 23.29% regarding Grey-based FSMs. Also, analysis of Table 17 shows that U₃-based FSMs have a higher operating frequency than the other investigated methods. There is the following gain: (1) 30.25% regarding Auto; (2) 25.47% regarding One-hot and (3) 16.27% regarding Gray-based FSMs.

So, our approach improves both spatial and temporal characteristics of complex FSMs. If minimum power consumption is used as the criterion for optimality, then One-hot-based FSMs are preferable. But if minimizing either LUT count or cycle time is a main criterion, then our method should be used for complex FSMs. Of course, this conclusion is true only for benchmarks [63] and the device AMD Virtex™ UltraScale+™ 56G PAM4 VCU129 FPGA Evaluation Kit (Virtex7 Ultrascale+ xcvu29p-fsga2577-2L-e) [29,41]. It is almost impossible to make a similar conclusion for the general case. But our experiments show that the proposed approach can reduce the occupied chip area and improve the performance of complex FSMs.

Table 18 and Table 19 summarize the execution time and memory peak results measured for the Vivado FPGA design flow. The reported values include both the synthesis stage and the complete Vivado flow, which comprises synthesis and implementation (optimization, placement, and routing) for the target FPGA device (Virtex7 Ultrascale+ xcvu29p-fsga2577-2L-e) [29,41]. For each method, results are presented as average values per benchmark and as cumulative values aggregated across all benchmarks, allowing a direct comparison of individual benchmark costs and total computational effort. All experiments were performed using Xilinx Vivado v2025. 1 [45] on a workstation equipped with an Intel(R) Core(TM) i9-14900K processor, 64 GB of RAM, and running Windows 11 (version 25H2). Each benchmark was executed once using identical synthesis and implementation settings, with the maximum number of threads limited to eight via the set_param general. maxThreads 8.

Table 18. Synthesis and Vivado flow execution times for the analyzed methods.

Time (HH:MM:SS)	Auto	One-Hot	Gray	${\mathit{U}}_3$
Synthesis per Benchmark (Avg.)	00:00:25	00:00:22	00:00:24	00:00:26
Synthesis (Sum)	00:22:16	00:19:28	00:20:46	00:22:37
Vivado Flow per Benchmark (Avg.)	00:04:40	00:04:36	00:04:36	00:04:43
Vivado Flow (Sum)	04:07:18	04:03:22	04:03:34	04:10:14

Table 19. Peak memory consumption during synthesis and Vivado flow execution.

Memory Peak (MB)	Auto	One-Hot	Gray	${\mathit{U}}_3$
Synthesis per Benchmark (Avg.)	2789.497	2785.736	2785.574	2794.817
Synthesis (Sum)	147,843.330	147,643.988	147,635.444	148,125.325
Vivado Flow per Benchmark (Avg.)	8291.637	7994.082	8466.230	8352.188
Vivado Flow (Sum)	439,456.786	423,686.364	448,710.207	442,665.962

The observed differences between the analyzed methods are relatively small and remain within a narrow range for both execution time and memory peak values. Moreover, given the number and size of the analyzed benchmarks, differences of the order of minutes or seconds can be considered negligible in the context of the overall Vivado design flow execution.

7. Conclusions

One of the basic problems in FPGA-based FSM design is improving the spatial characteristics of FSM circuits. It is very important to find a solution with a minimum LUT count and escape the increasing cycle time. For complex FSMs, synthesis is connected with the decomposition of SBFs representing an FSM circuit. In this paper, we proposed a method based on the structural decomposition [3] of Moore FSM circuits. The proposed method uses output code collections to create partial state codes.

As the conducted experiments show, the proposed method results in circuits with better spatial (LUT count) and temporal (maximum operating frequency) characteristics than equivalent FSMs. These equivalent FSMs were designed using three state-encoding methods (Auto, One-hot, Gray). The improved characteristics are possible for rather complex FSMs for which the total number of FSM inputs and state variables is at least twice the number of inputs of the base LUT. In experiments, we used LUTs with six inputs.

So, the proposed state assignment method reduces the spatial characteristics and increases the FSM’s performance. Thus, the proposed method can be used for designing rather complex FSMs if the main optimality criterion for FSM circuits is minimum LUT count and cycle time. We think that this approach could be used when multiple FPGA-based accelerators are used in application-specific standard products (ASSP) chips [67,68]. In this case, it is necessary to use hardware–software interfaces to coordinate the interaction of microprocessors and accelerators [9]. Interface protocols are represented as finite-state machines. The ASSP chips possess limited resources of LUTs. So, for such solutions, reducing the LUT count in FSM circuits is very important.

As our experiments show, some FSMs include states for which the number of inputs determining interstate transitions exceeds the number of LUT inputs. We called such FSMs very complex. The proposed method cannot be applied to designing very complex FSMs. The solution to this problem is one of the directions of our future research. The second research direction is the use of AI tools [69,70,71] in the FPGA-based design of Moore FSMs.