A Novel and Highly Versatile Voltage Monitoring Circuit Enabling Power Consumption and Area Minimization

Abstract

Voltage monitoring circuits are a fundamental block in energy-harvesting-powered applications, as typically the system operation has to be enabled only after a certain supply voltage is reached after a cold start or intermediate voltage levels have to be detected during start-up. The voltage values of interest vary depending on the specific system; hence, a versatile voltage monitoring circuit scheme that can be easily adapted for the desired voltage is particularly appealing. Furthermore, in energy-harvesting-powered applications, special care must be paid to power consumption minimization, in order to ensure self-sustainability of the system, and to area occupation, thus enabling a small form factor and low cost. To address these requirements, this paper proposes a novel, highly versatile voltage-monitoring circuit for energy-harvesting-powered applications that minimizes power consumption and area occupation. Indeed, the proposed voltage monitor implementation, relying on cascaded PMOS-based and NMOS-based voltage detectors, can be easily adapted to any desired voltage level, also achieving high voltage levels to be detected by adding (multiple) diode-connected transistors in the first stage while maintaining the voltage monitor output rail-to-rail and avoiding static power consumption from the cascaded digital gates. The proposed solution, targeting a 800 mV voltage level to be detected, was designed in a 180 nm CMOS triple-well technology and extensively validated through simulations in Cadence Virtuoso. Furthermore, it was bench-marked with an implementation in the same process based on the standard voltage monitor scheme (including the necessary cascaded logic gates for achieving a rail-to-rail output) available in literature, showcasing a reduction up to about 1700× in power consumption and 3.87× in area occupation, considering a preliminary area estimation, when triple-well devices are employed, whereas, when relying only on standard devices, although no significat area benefit is obtained, a reduction of up to about 400× in power consumption is achieved.

1. Introduction

In recent years, Internet of Things (IoT) distributed wireless sensor networks, smart home sensor applications, and wearable biomedical and healthcare devices have become widespread [1,2,3,4]. These types of systems typically require minimizing form factor and cost, as well as ensuring self-sustained operation with a prolonged lifetime; hence, the need for energy harvesting from environmental sources as a way to enable battery-free solutions has emerged [5]. The employed energy sources are various: light [3,4,6,7,8], heat [2,9,10,11,12], mechanical vibrations [13,14,15,16,17], radio-frequency [18,19], and bio-fuel cells [20]. Independent of the used energy type, however, all systems require reaching a predetermined voltage before fully starting up the device and/or to detect intermediate voltage levels during cold start: typically, such voltage levels fall within the 250 mV–1 V range [1,2,3,8,9,11,12,21]. A voltage monitor, also known as a level or voltage detector, is therefore required for determining when the desired voltage level has been reached.

Conventional voltage monitoring circuits employ a temperature-independent voltage reference and a comparator [22,23,24]: such solutions, however, are not suitable for ultra-low-power energy harvesting systems, as they would feature a significant power consumption in the range of tens or hundreds of nW. Indeed, in energy-harvesting-powered solutions, special care must be paid to power consumption minimization in order to make the system self-sustainable. Moreover, as many applications target room temperature use (e.g., wearable or implantable healthcare devices, smart home sensor networks), the temperature-insensitivity requirement can be relaxed. Hence, specific voltage monitoring circuits, usually based on a simple two-transistor (2T) structure [21], have been developed for energy harvesting systems [1,2,3,21]. Such structures, however, face limitations when the voltage level to be detected falls within the higher half of the 250 mV–1 V range. This paper instead provides a highly versatile voltage monitoring circuit solution, which can be adapted to any required voltage level while overcoming the issues of the voltage monitors available in the literature. Indeed, the proposed voltage monitoring circuit, by cascading PMOS-based and NMOS-based voltage monitors, enables also implementing high voltage levels while minimizing area and power consumption. Indeed, the proposed solution allows adding (multiple) diode-connected transistors to the 2T structure, thus achieving high voltage levels to be detected while maintaining the voltage monitor output rail-to-rail and avoiding static power consumption from the cascaded digital gates.

This paper is organized as follows: Section 2 describes the voltage monitor solutions for energy harvesting systems available in the literature and their drawbacks; Section 3 illustrates the proposed voltage monitoring circuit; Section 4 provides a design example, employing a 180 nm CMOS technology, of the proposed voltage monitor, benchmarking it with the standard state-of-the-art solution; Section 5 concludes the paper.

2. State-of-the-Art Overview

Voltage monitoring circuits in energy harvesting applications typically require providing a zero-voltage output for input voltages lower than a predetermined threshold and a voltage output equal to the supply voltage for input voltages above the threshold. The threshold or trigger voltage constitutes the required minimum voltage for full start-up or for transitioning from one start-up phase to the following one. The simplest voltage monitoring circuit is composed of two transistors of the same type [1,21]: the PMOS-based implementation is illustrated in Figure 1a, whereas the NMOS-based one is shown in Figure 1b. The principle of operation for both realizations is analogous: the only difference is given by the fact that the resulting logic is complementary. In particular, contrary to the PMOS-based implementation, the NMOS-based solution outputs a voltage equal to the input voltage for input voltages lower than the trigger voltage and a zero voltage for input voltages higher than the trigger. Hence, an additional inverter in the NMOS-based case is required in order to maintain the same logic. When the input voltage is very low, however, the case when the output voltage is equal to the input voltage might not be correctly discriminated from the one where the output voltage is zero, since input voltages lower than the MOS devices threshold would be unable to correctly operate the logic gates: for this reason, only PMOS-based voltage monitoring circuits are found in the literature. Nevertheless, as will be seen in the next section, also relying on NMOS-based solutions might be of interest.

Figure 1. Schematic representation of the basic (a) PMOS-based and (b) NMOS-based 2T voltage monitoring circuits.

Considering the two-transistor (2T) PMOS-based solution, the trigger voltage is determined by the comparison between the currents of transistors $M_{P1}$ and $M_{P2}$. Both transistors operate in the subthreshold region, as $M_{P1}$ is biased with zero gate-to-source voltage; thus, supposing that the transistor is saturated (its source-to-drain voltage is larger than four times the thermal voltage), the source-to-drain current flowing through $M_{P2}$ is given by

$$I_2=I_0{e}^{{\displaystyle \frac{q(V_{SG}-|V_{TH}\left|\right)}{nkT}}}$$

(1)

where $V_{SG}$ is the transistor source-to-gate voltage, $V_{TH}$ its threshold voltage, k the Boltzmann constant, q the elementary charge, T the temperature expressed in Kelvin degrees, and n is the subthreshold slope coefficient.

• The term $I_0$ is equal to

  $$I_0=\mu C_{OX}{\displaystyle \frac{W_2}{L_2}}{\left({\displaystyle \frac{kT}{q}}\right)}^2=K{\displaystyle \frac{W_2}{L_2}}$$

  (2)

  where $\mu$ is the carrier’s (in this case holes) mobility, $C_{OX}$ is the gate oxide capacitance per unit area, and W and L are the width and length, respectively, of the transistor.
• Hence, the $M_{P2}$ current can be expressed as

  $$I_2=K{\displaystyle \frac{W_2}{L_2}}{e}^{{\displaystyle \frac{q(V_{IN}-|V_{TH}\left|\right)}{nkT}}}$$

  (3)

  where $V_{IN}$ is the input voltage, acting as supply for the 2T voltage monitoring circuit.
• Analogously, the source-to-drain current of $M_{P1}$ is given by

  $$I_1=K{\displaystyle \frac{W_1}{L_1}}{e}^{{\displaystyle \frac{-q|V_{TH}|}{nkT}}}$$

  (4)

  Current $I_1$ is constant and only depends on the transistor aspect ratio. The threshold or trigger voltage $V_{TRIGGER}$, corresponding to the detected level, is defined as the input voltage $V_{IN}$ when the output voltage $V_{OUT}$ changes from low to high, which corresponds to the input voltage when $I_1$ and $I_2$ are equal. From Equations (3) and (4), the value of $V_{TRIGGER}$ is derived:

  $$V_{{IN}_{I_1=I_2}}=V_{TRIGGER}={\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_1}{L_1}}·{\displaystyle \frac{L_2}{W_2}}\right)$$

  (5)
• Hence, the trigger voltage depends on the thermal voltage and on the sizes of transistors $M_{P1}$ and $M_{P2}$. The temperature dependency is not critical, as many energy harvesting applications (e.g., body-wearable devices, smart home sensor networks, and indoor solar cells) target room temperature use.

If two transistors with different threshold voltages [3] are used, the trigger voltage will become

$$V_{TRIGGER}={\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_1}{L_1}}·{\displaystyle \frac{L_2}{W_2}}\right)+V_{TH,1}-V_{TH,2}$$

(6)

where $V_{TH,1}$ and $V_{TH,2}$ are the threshold voltages of $M_{P1}$ and $M_{P2}$, respectively. For simplicity, the same subthreshold slope coefficient n has been considered for the two transistor types, but they could differ; however, since the variation would be small, Equation (6) represents a good approximation.

It is evident from Equations (5) and (6) that in order to obtain relatively large trigger voltages, on the order of a few hundred mV, very large transistor ratios, which are not suitable or practical for implementation, are required.

The same derivations can be carried out in the case of NMOS-based voltage monitoring circuits by substituting $V_{SG}$ with $V_{GS}$ and $|V_{TH}|$ with $V_{TH}$, and defining $V_{TRIGGER}$ as $V_{IN}$ when $V_{OUT}$ changes from high to low, which still corresponds to when $I_1$ and $I_2$ are equal.

In order to increase the trigger voltage, a possibility is supplying an additional bias to transistor $M_{P2}$ (or $M_{N2}$) [4,9], as illustrated in Figure 2, which shows the PMOS-based implementation and the dual NMOS-based realization. In this way, carrying out the same derivation as for the previous case, the trigger voltage becomes

$$V_{TRIGGER}=V_X+{\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_1}{L_1}}·{\displaystyle \frac{L_2}{W_2}}\right)$$

(7)

Voltage $V_X$ is typically provided by some crude voltage reference (e.g., 2T or 3T voltage references [25]). However, implementing large values of $V_X$ is again not practical with two-transistor or three-transistor architectures, and using more complex structures may not be feasible or would dramatically increase the power consumption.

Figure 2. Schematic representation of the basic (a) PMOS-based and (b) NMOS-based 2T voltage monitoring circuits with additional $V_X$ voltage biasing.

Another possibility to increase the trigger voltage is going from the 2T circuit of Figure 1 to the three-transistor (3T) structure of Figure 3 by adding a diode-connected transistor $M_{P3}$ (or $M_{N3}$), which features the same size as $M_{P2}$ ($M_{N2}$) [1,21]. Since $M_{P2}$ and $M_{P3}$ share the same size and the same current flows through them, from Equation (1), their source-to-gate voltages, $V_{SG,2}$ and $V_{SG,3}$, are the same, so

$$V_{SG,2}=V_{S,2}-0=V_{SG,3}=V_{IN}-V_{S,2}$$

(8)

$$V_{S,2}={\displaystyle \frac{V_{IN}}{2}}$$

(9)

where $V_{S,2}$ is the voltage found at the source of $M_{P2}$.

Figure 3. Schematic representation of the (a) PMOS-based and (b) NMOS-based voltage monitoring circuits with an additional diode-connected transistor.

• Therefore, the trigger voltage becomes

  $$V_{TRIGGER}=2{\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_1}{L_1}}·{\displaystyle \frac{L_2}{W_2}}\right)$$

  (10)

  which is twice the trigger voltage of a 2T voltage monitoring circuit with the same $M_{P1}$ and $M_{P2}$ sizes. To implement the same trigger voltage, therefore, a significant reduction of the transistor sizes is enabled. The price to pay for the trigger voltage increase is the fact that the output voltage for input voltages larger than the threshold is no longer equal to $V_{IN}$: indeed, it becomes equal to $V_{IN}$ minus the diode-connected transistor voltage drop, which is equal to $V_{SG,3}={\displaystyle \frac{V_{IN}}{2}}$, as derived from Equations (8)–(9). In order to restore the full dynamic, two inverters, supplied between ground and $V_{IN}$, must be cascaded to amplify the voltage swing. The same issue arises also in the NMOS-based implementation, where the output voltage for input voltages larger than the trigger voltage is not equal to zero but to the diode-connected transistor voltage drop (i.e., $V_{GS,3}={\displaystyle \frac{V_{IN}}{2}}$). As the cascaded inverter will feature an input voltage different from its positive or negative supply, it will exhibit a non-zero static power consumption, which can constitute a significant drawback in systems supplied through energy harvesting.

In principle, it is possible to stack multiple diode-connected transistors in order to obtain a trigger voltage that is three times or higher than that of the 2T architecture. However, as the output voltage would become $V_{IN}$ minus the diode voltage drops (for the PMOS-based solution), if the resulting output voltage is too low, it would fail to be properly detected as being at a high level by the cascaded inverter. The dual problem (the output voltage not recognized as low level) would arise in the NMOS-based implementation. Hence, in practice, only one diode-connected transistor can be added.

In order to avoid the power consumption increase in the 3T architecture, a cross-coupled voltage monitoring circuit, delivering a full-swing output, was proposed in [2]. It consists of one PMOS-based and one NMOS-based structure connected in a cross-coupled fashion, implementing a positive feedback, which enhances the switching speed. In this case, however, the trigger voltage expression becomes extremely complex, with multiple conditions, which should be simultaneously satisfied, imposed on the transistor sizes, as both PMOS and NMOS voltage detectors should share the same trigger voltage as well. With this type of structure, therefore, proper sizing of the transistors to obtain the desired trigger voltage value cannot be done by hand and requires instead several iterations and relying on numerical simulation methods.

3. Proposed Voltage Monitoring Circuit

There exists, therefore, no voltage monitoring circuit in the literature simultaneously satisfying small-area, minimized power consumption and easy tunability requirements. This paper instead proposes a highly versatile solution, which can implement any desired trigger voltage while minimizing both area and power consumption. The foundation for this novel type of voltage detector lies in two main considerations: (i) the fact that the output of a 2T structure is rail-to-rail and therefore would ensure no static power consumption for any cascaded logic gate and (ii) the characteristics of generalized PMOS and NMOS voltage detector circuits, which are illustrated schematically in Figure 4a and Figure 4b, respectively.

Figure 4. Schematic representation of the generalized (a) PMOS-based and (b) NMOS-based voltage monitoring circuits.

A generalized voltage monitoring circuit, either PMOS-based or NMOS-based, is constituted by the core 2T structure ($M_{P1}-M_{P2}$ or $M_{N1}-M_{N2}$), with the addition of a biasing voltage to the transistor $M_{P2}$ (or $M_{N2}$) and to n diode-connected $M_{XPi}$ (or $M_{XNi}$) transistors sharing $M_{P2}$ (or $M_{N2}$) size. As seen in Figure 2, the biasing voltage in the case of a PMOS solution must be a fixed voltage with respect to the ground, whereas in the dual case of an NMOS device, it must be a fixed voltage with respect to $V_{IN}$. The output voltage $V_{OUT}$ of a generalized PMOS-based voltage detector, for input voltages larger than the trigger voltage, is a fixed voltage $\Delta V_P$, determined by the diode drops, with respect to $V_{IN}$; the $V_{OUT}$ of a generalized NMOS-based voltage monitoring circuit, instead, for input voltages larger than the trigger voltage, is a fixed voltage $\Delta V_N$, determined by the diode drops, with respect to the ground. The output voltage, for input voltages larger than the trigger voltage, of a PMOS-based solution, therefore, meets exactly the requirements for the biasing voltage of an NMOS-based implementation (and vice versa). When the input voltage is lower than the trigger voltage, the $V_{OUT}$ in the case of an NMOS-based solution is $V_{IN}$; if applied as biasing voltage of a PMOS-based voltage monitor, it would bias $M_{P2}$ with a negative $V_{SG}$, and therefore the output voltage would be zero. Conversely, when the input voltage is lower than the trigger voltage, $V_{OUT}$ in the case of a PMOS-based solution is zero; if applied as biasing voltage of an NMOS-based voltage monitor, it would bias $M_{N2}$ with a negative $V_{GS}$ and therefore the output voltage would be $V_{IN}$. Hence, when the input voltage is below the trigger voltage in the PMOS-based solution and is used as the biasing voltage of an NMOS-based implementation, the output voltage of the NMOS-based circuit is compliant with the fact that the input voltage is below the PMOS-based voltage detector threshold. The same holds true also when considering the output voltage of an NMOS-based solution applied as biasing the voltage to a PMOS-based voltage detector.

Hence, it becomes apparent that cascading PMOS and NMOS-based solutions (and vice versa) is possible. Furthermore, if the last stage of the cascade is a 2T device, the output would be rail-to-rail, and no static power consumption issue would arise for any cascaded logic gate. This allows employing freely multiple stacked diode-connected transistors in stages different from the last, thus facilitating the implementation of relatively large trigger voltages.

In principle, any number of stages could be used, provided that PMOS and NMOS based structures are alternated and that the last stage is a 2T structure. However, in order to minimize area and power consumption, minimizing the number of stages is required. As explained previously, a PMOS-based voltage monitor is preferable with respect to an NMOS one when it has to interface any logic gate, hence a PMOS-based 2T output stage should be selected. Moreover, it must be taken into account that the illustrated output voltage shapes for the various voltage detectors are obtained only provided that the transistors ($M_{N1}$ and $M_{P1}$ in particular, considering an NMOS or a PMOS stage, respectively) do not suffer from body effect. Ensuring that no PMOS transistor suffers from body effect is possible in any technology by shorting the transistor body and source terminals, however the same does not hold true for NMOS devices, as the process used for the implementation must support the realization of triple-wells. When $M_{N1}$ suffers from body effect, $V_{OUT}$ does no longer feature a sharp shape: Figure 5 illustrates an NMOS voltage detector output waveform when a triple-well NMOS (without body effect) or a standard NMOS (suffering from body effect), maintaining the same width and length, are employed for $M_{N1}$ in a 3T structure. The results are obtained by means of a transient simulation in Cadence Virtuoso, increasing the $V_{IN}$ voltage in a ramp fashion. The fact that $V_{OUT}$ in the standard NMOS case becomes almost flat, before going to the diode voltage drop after reaching the designed trigger voltage, limits the performance of the proposed voltage monitoring circuit, obtained by cascading PMOS- and NMOS- based voltage detectors. The details of the limitations and how to possibly overcome them will be discussed later on.

Figure 5. Simulated output voltage of an NMOS voltage detector when employing isolated (triple-well) or standard NMOS devices for $M_{N1}$.

These considerations led to the definition of the proposed voltage monitoring circuit, illustrated in Figure 6. It consists of three stages: a PMOS-based first stage, an NMOS-based second stage, and a PMOS-based output stage. The first stage does not feature any extra biasing (the gate of $M_{P2}$ is connected to ground) and includes multiple additional diode-connected transistors in order to implement a rather large trigger voltage. The second stage exploits the first-stage output as extra biasing and, featuring an additional diode-connected transistor, implements the third-stage voltage biasing. The third and final stage is implemented through a PMOS-based 2T structure, ensuring full rail-to-rail output swing. Eventually, two cascaded inverters can be added to act as a digital buffer and drive any logic gate. The proposed solution targets an 800 mV trigger voltage and therefore employs two diode-connected transistors in the first stage; however, by adjusting the number of diodes in the first stage and the transistor sizes, any output voltage could be implemented. As the employed technology allows it, the proposed implementation uses an NMOS device in a triple-well for realizing $M_{N1}$, thus shorting its body terminal to its source, while other NMOS transistors are standard devices with the body connected to the ground. All PMOS transistors feature body and source terminals shorted together.

Figure 6. Schematic representation of the proposed voltage monitoring circuit.

We now consider the operation of the proposed circuit and how to size it to realize the desired trigger voltage. At first, when the input voltage is below the trigger voltage of the first stage, $V_{OA}$ (i.e., the first stage output) is zero, $V_{OB}$ is equal to $V_{IN}$, and $V_{OUT}$ is zero. When $V_{IN}$ exceeds the trigger voltage of the first stage, $V_{OA}$ becomes equal to $V_{IN}-\Delta V_A$, thus providing the biasing for $M_{N2}$ in the second stage. As long as the trigger voltage of the second stage is not exceeded, then $V_{OB}$ stays equal to $V_{IN}$ and $V_{OUT}$ stays at zero. When $V_{IN}$ exceeds the trigger voltage of the second stage, $V_{OB}$ switches to $\Delta V_B$ and provides the biasing for the third stage. When $V_{IN}$ exceeds the trigger voltage of the third stage as well, $V_{OUT}$ becomes equal to $V_{IN}$. Since one voltage detector cannot change its output until the previous voltage detector stage has reached its trigger voltage, a sequential operation takes place.

The trigger voltage of the first stage as a stand-alone, considering that two diode-connected transistors are employed, is

$$V_{TRIGGER,1}=3{\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_{P1}}{L_{P1}}}·{\displaystyle \frac{L_{P2}}{W_{P2}}}\right)$$

(11)

The trigger voltage of the second stage as a stand-alone when the first stage is providing the additional $\Delta V_A$ bias is

$$V_{TRIGGER,2}=\Delta V_A+2{\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_{N1}}{L_{N1}}}·{\displaystyle \frac{L_{N2}}{W_{N2}}}\right)$$

(12)

where

$$\Delta V_A={\displaystyle \frac{V_{TRIGGER,1}}{3}}$$

(13)

The trigger voltage of the third and last stage as a stand-alone when the second stage provides the additional $\Delta V_B$ bias is

$$V_{TRIGGER,3}=\Delta V_B+{\displaystyle \frac{nkT}{q}}ln\left({\displaystyle \frac{W_{P5}}{L_{P5}}}·{\displaystyle \frac{L_{P6}}{W_{P6}}}\right)$$

(14)

where

$$\Delta V_B={\displaystyle \frac{V_{TRIGGER,2}}{2}}$$

(15)

As explained previously, however, the sequential nature of the operation must be taken into account for deriving the trigger voltage of the overall voltage monitoring circuit. Indeed, it must be remembered that one stage cannot be triggered until the previous one has. Hence, the overall voltage monitoring circuit’s effective trigger voltage is the largest among $V_{TRIGGER,1}$, $V_{TRIGGER,2}$ and $V_{TRIGGER,3}$. Exploiting this property, it is therefore possible to set the desired output trigger voltage solely by adjusting $V_{TRIGGER,1}$, provided that the stand-alone trigger voltage of the successive stages is lower. Alternatively, it is also possible to exploit the following stages to increase the resulting overall output trigger voltage by realizing cascaded voltage detector stages with increasingly larger stand-alone trigger voltages. The simulated voltage waveforms found at the various nodes of the proposed voltage monitoring circuit in typical conditions are shown in Figure 7.

Figure 7. Simulated node voltages as a function of time for the proposed voltage monitoring circuit in nominal conditions.

The illustrated operation description is valid provided that, in addition to the PMOS devices, transistor $M_{N1}$ also does not suffer from a body effect, and it is therefore implemented through a triple-well device. If instead a standard NMOS device is used, the flat shape shown in Figure 6 and found at $V_{OB}$ affects the sequential operation: indeed, without the sharp shape, there is no longer a clear discrimination at the NMOS stage output between the cases when $V_{IN}$ is below or above the trigger voltage. This results in a lower trigger voltage at the overall voltage monitoring circuit’s output. In order to increase the trigger voltage, the aspect ratio of $M_{N1}$ should be increased, the ratio of $M_{N2}$ should be decreased, and/or the number of diode-connected transistors should be increased. Also, increasing the stand-alone trigger voltage of the last stage, and thus increasing (decreasing) the aspect ratio of $M_{P6}$ ($M_{P5}$), can help. Intervening in the first stage, instead, is not useful, as changing its trigger voltage has no significant effect on the resulting flat $V_{OB}$ shape. Employing isolated (triple-well) NMOS devices, when possible, is therefore clearly preferable. Alternatively, it is possible to implement the proposed circuit only with standard devices, but at the cost of increasing the area occupation. The simulated voltage waveforms found at the various nodes of the proposed voltage monitoring circuit when employing a standard NMOS device for $M_{N1}$ are shown in Figure 8. It is evident that, by maintaining the same transistor size when employing only standard devices, a lower trigger voltage is determined with respect to the case when a triple-well device is used for $M_{N1}$.

Figure 8. Simulated node voltages as a function of time for the proposed voltage monitoring circuit in nominal conditions when employing a standard NMOS device for implementing $M_{N1}$.

It should be noted that the response speed of voltage monitoring circuits for energy-harvesting-powered applications is not critical: indeed, the input voltage typically rises slowly (the rise time is on the order of hundreds of ms) as the charging of a large input storage capacitance is involved. Hence, when considering the evolution of the nodes with respect to time, considering a 500 ms rise time for the input voltage is reasonable.

4. Design Example

The proposed voltage monitoring circuit, implementing an 800 mV trigger voltage in nominal conditions, was designed in a 180 nm CMOS process supporting triple-well implementation. The selected transistor sizes are reported in Table 1. Each transistor features a modular structure, where the total width is given by the multiplicity times the reported W value. All transistors are realized with standard devices, with the exception of $M_{N1}$, which is implemented in a triple-well. All PMOS transistors and $M_{N1}$ feature the body shorted to the source, whereas $M_{N2}$ and $M_{N3}$ have the body connected to ground.

Table 1. Employed Transistor Sizes for the Proposed Voltage Monitoring Circuit Solution.

	W [m]	L [m]	Multiplicity
$M_{P1}$	6 $\mathsf{\mu }$	250 n	12
$M_{P2}$	440 n	8.8 $\mathsf{\mu }$	1
$M_{P3}$	440 n	8.8 $\mathsf{\mu }$	1
$M_{P4}$	440 n	8.8 $\mathsf{\mu }$	1
$M_{N1}$	1.8 $\mathsf{\mu }$	180 n	8
$M_{N2}$	440 n	4.4 $\mathsf{\mu }$	1
$M_{N3}$	440 n	4.4 $\mathsf{\mu }$	1
$M_{P5}$	1.8 $\mathsf{\mu }$	250 n	12
$M_{P6}$	440 n	1.1 $\mathsf{\mu }$	1

In order to be able to provide a fair comparison (the same technology, same desired trigger voltage) with the state-of-the-art voltage detector structures, a 3T PMOS-based voltage monitor was designed as well for benchmarking. This topology was selected as it represents the go-to solution for the targeted trigger voltage value. The designed standard voltage detector, including the cascaded digital buffer for restoring the full output swing, is illustrated in Figure 9. The selected transistor sizes are reported in Table 2.

Figure 9. Schematic representation of the standard voltage monitoring circuit used for benchmarking.

Table 2. Employed Transistor Sizes for the Standard Voltage Monitoring Circuit Used for Benchmarking.

	W [m]	L [m]	Multiplicity
$M_{P1}$	21.5 $\mathsf{\mu }$	250 n	72
$M_{P2}$	440 n	17.6 $\mathsf{\mu }$	1
$M_{P3}$	440 n	17.6 $\mathsf{\mu }$	1

For both the proposed and standard structures, the inverters were implemented with an NMOS featuring $W=250$ nm, $L=180$ nm and $Multiplicity=2$, and a PMOS featuring $W=450$ nm, $L=180$ nm and $Multiplicity=2$.

Both the proposed and the reference standard solutions were characterized through extensive simulations in Cadence Virtuoso.

The proposed voltage monitoring output voltages $V_{OUT}$ and $V_{OUTB}$ (before and after the digital buffer, respectively), under typical process conditions, as a function of the input voltage $V_{IN}$ are reported in Figure 10. The current consumption, excluding the inverters as they should feature zero power consumption, as a function of $V_{IN}$, is illustrated instead in Figure 11. As expected, a difference in the trigger voltage is found at different temperatures: as the variation is ±100 mV between 10 °C and 40 °C, this is in line with the state of the art and acceptable for energy-harvesting-powered applications targeting room temperature use. It can be noticed that the current consumption, directly determined by the leakage of the transistors with zero $V_{GS}$ voltage, increases with both temperature and $V_{IN}$. In order to assess the proposed and standard circuit current consumption, therefore, the case for $V_{IN}$ = 1.8 V (i.e., the maximum transistor voltage rating) will be considered as it represents the worst possible case.

Figure 10. Simulated output voltages (pre- and post-inverters) as a function of the input voltage for the proposed voltage monitoring circuit in nominal conditions.

Figure 11. Simulated current consumption (excluding inverters) as a function of the input voltage for the proposed voltage monitoring circuit in nominal conditions.

The proposed voltage monitoring circuit performance was also verified against process and mismatch variations, considering 500 Monte Carlo runs. The simulated trigger voltage values are illustrated in Table 3. The current consumption for the worst input voltage case are reported instead in Table 4. Although zero static power consumption is expected for the inverters, a slight increase in current consumption is found when taking them into account: this is due to their leakage current.

Table 3. Simulated Trigger Voltage for the Proposed Voltage Monitoring Circuit (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean [V]	Standard Deviation [mV]
10	737.1	12.7
25	802.2	10.9
40	872.8	10.0

Table 4. Simulated Current Consumption for the Proposed Voltage Monitoring Circuit (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean (w/o Inverters) [pA]	Standard Deviation (w/o Inverters) [pA]	Mean (w/ Inverters) [pA]	Standard Deviation (w/ Inverters) [pA]
10	123.4	39.4	138.6 (worst = 363.9)	43.8
25	296.9	102.3	322.5 (worst = 886.1)	112.1
40	693.6	242.6	740.1 (worst = 2035)	262.9

As was explained previously, the response speed of the voltage monitoring circuit is not critical. Nevertheless, the proposed voltage detector response time has been evaluated through simulations by applying a voltage step (from 0 to 1.8 V) as input voltage and considering the time required by the $V_{OUTB}$ node for switching to 1.8 V after the application of the input voltage step: in this way, an equivalent propagation delay time was derived and it was found equal to 3.06 $\mathsf{\mu }\mathrm{s}$ in typical conditions. This time is several orders of magnitude smaller than the typical rise time of the supply voltage in energy-harvesting-powered systems, so it does not affect the operation in such applications.

The standard reference solution was characterized as well. The standard 3T voltage detector output voltages $V_{OUT}$ and $V_{OUTB}$ (before and after the digital buffer, respectively), under typical process conditions, as a function of the input voltage $V_{IN}$ are reported in Figure 12. The same variation with temperature as with the proposed solution is found. As expected, $V_{OUT}$ for input voltage larger than the trigger voltage is equal to $V_{IN}$ minus the diode-connected transistor voltage drop. The simulated trigger voltages against process and mismatch variations, considering 500 Monte Carlo runs, are reported in Table 5. As the inverters implementing the digital buffer are necessary for restoring the full output swing and are therefore an integral part of the voltage detector, only the current consumption with the inverters is of actual interest. The simulated current consumption for the worst case input voltage, considering 500 Monte Carlo runs including both process and mismatch, is reported in Table 6.

Figure 12. Simulated output voltages (pre and post inverters) as a function of the input voltage for the standard voltage monitoring circuit in nominal conditions.

Table 5. Simulated Trigger Voltage for the Standard 3T Voltage Monitoring Circuit (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean [V]	Standard Deviation [mV]
10	748.4	9.3
25	806.2	11.3
40	884.7	24.5

Table 6. Simulated Current Consumption for the Standard Voltage Monitoring Circuit (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean (w/o Inverters) [nA]	Standard Deviation (w/o Inverters) [nA]	Mean (w/ Inverters) [nA]	Standard Deviation (w/ Inverters) [nA]
10	0.86	0.40	46.48 (worst = 520.2)	51.53
25	2.21	1.06	142.2 (worst = 1396)	151.3
40	5.44	2.53	435.6 (worst = 3534)	431.4

Furthermore, the response speed of the standard voltage detector was evaluated analogously as for the proposed voltage monitoring circuit and a propagation delay equal to 11.3 $\mathsf{\mu }\mathrm{s}$ in typical conditions was found, which, although 3.69 times larger than the one of the proposed voltage monitor, is still several orders of magnitude smaller than the typical rise time of the supply voltage in energy-harvesting-powered systems and therefore not critical.

For completeness, the proposed voltage monitoring circuit was also designed using only standard devices. In this case, in order to obtain a nominal 800 mV trigger voltage, three additional diode-connected NMOS were added in the second stage, and the sizes of $M_{N1}$, $M_{P5}$ and $M_{P6}$ were adjusted accordingly. In particular, $M_{N1}$ featured a 7.2 $\mathsf{\mu }\mathrm{m}$ width, a 180 nm length and a multiplicity equal to 24; $M_{P5}$ featured a 1.8 $\mathsf{\mu }\mathrm{m}$ width, a 250 nm length, and a multiplicity equal to 48; and $M_{P6}$ featured a 440 nm width, a 8.8 $\mathsf{\mu }\mathrm{m}$ length, and a multiplicity equal to 1. The simulated trigger voltage and current consumption for the proposed standard-devices-only voltage monitoring circuit are reported in Table 7 and Table 8, respectively. The obtained trigger voltage spread is analogous to the one of the solution with a triple-well device implementing $M_{N1}$, but the current consumption is larger: this is expected as larger size devices were employed, thus giving rise to increased leakage. Nevertheless, the current consumption is still significantly reduced with respect to the standard solution.

Table 7. Simulated Trigger Voltage for the Proposed Voltage Monitoring Circuit When Employing Only Standard Devices (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean [V]	Standard Deviation [mV]
10	740.5	8.4
25	809.6	9.3
40	886.1	12.9

Table 8. Simulated Current Consumption for the Proposed Voltage Monitoring Circuit When Employing Only Standard Devices (500 Monte Carlo runs for each temperature).

Temperature [°C]	Mean (w/o Inverters) [pA]	Standard Deviation (w/o Inverters) [pA]	Mean (w/ Inverters) [pA]	Standard Deviation (w/ Inverters) [pA]
10	148.4	49.5	171.5 (worst = 1405)	117.5
25	314.6	130.0	343.4 (worst = 4133)	433
40	695.5	311.8	733.4 (worst = 8268)	1187

Comparing the performance of the proposed and standard solution, although their implemented trigger voltage and its variation with temperature, process, and mismatch are roughly the same, as expected, the proposed voltage monitoring circuit clearly outperforms the standard voltage detector in terms of power consumption by orders of magnitude. Indeed, when considering the worst case for a 1.8 V $V_{IN}$, the standard solution features a 3534 nA current consumption, whereas the proposed solution offers 2.035 nA and 8.268 nA for the triple-well and standard-devices-only implementations, respectively, thus featuring 1736× and a 427× power savings, respectively. The reported power consumption values take into account the inverter’s static power consumption, as the voltage monitor output needs to interface the system control logic and therefore requires being restored to rail-to-rail; hence, the inverter’s power consumption is a direct consequence of the voltage monitor implementation and of its output. Only static power consumption is considered, as the voltage monitor switching event in energy harvesting systems typically happens only during start-up and therefore very rarely; hence, the dynamic power consumption is negligible.

Furthermore, an area estimation (excluding the cascaded inverters) was performed relying on the Cadence LayoutXL dedicated tool, supposing 60% area utilization: the standard 3T structure featured a 75 $\mathsf{\mu }\mathrm{m}$ × 75 $\mathsf{\mu }\mathrm{m}$ area, whereas the proposed voltage detector circuit employing a triple-well device for $M_{N1}$ resulted in a 38.1 $\mathsf{\mu }\mathrm{m}$ × 38.1 $\mathsf{\mu }\mathrm{m}$ area occupation, thus featuring a 3.87× reduction; the proposed voltage monitor circuit realized only with standard devices, instead, resulted in a 74.1 $\mathsf{\mu }\mathrm{m}$ × 74.1 $\mathsf{\mu }\mathrm{m}$ area, only slightly smaller than the standard solution case.

The proposed novel voltage monitor, as well as the standard solution, are compared with the state-of-the-art in Table 9. Typical conditions are considered, as the other reported works do not provide an assessment under process/mismatch and temperature variations. The proposed solution is outperformed in terms of power consumption only by [2], which, however, does not feature the same versatility of the proposed voltage monitoring circuit: indeed, as explained in Section 2, reference [2] requires performing several iterations of numerical simulations in order to properly size the transitors, whereas the transistors’ sizing for the proposed voltage detector can be implemented relying on simple closed-form expressions.

Table 9. State-Of-The-Art Comparison.

	This Work Novel Solution	This Work Standard Solution	[21]	[1]	[2]	[3]	[4]
Trigger Voltage [mV]	802.2	806.2	520	∼600	600	<450	1.75
Current Consumption [nA] (Supply Voltage)	0.3434 (1.8 V)	142.2 (1.8 V)	3.5 (0.7 V)	<5 (NA)	∼0.025 (1 V)	NA	157.2 (1.8 V)

The proposed design example implemented a 800 mV trigger voltage, but any trigger voltage up to the employed transistors voltage rating can be implemented when relying on a triple-well device for realizing $M_{N1}$: it is sufficient to stack as many diode-connected MOSs in the first stage as required, provided that the obtained trigger voltage does not excess the voltage rating under temperature, process and/or mismatch variations. If only standard devices are used, then the maximum achievable trigger voltage is imposed by the maximum desired area occupation, as the only way to counteract the degradation due to the body effect on $M_{N1}$ is to increase the transistor sizes and/or increase the number of diode-connected transistors in the second stage.

5. Conclusions

This paper has featured a detailed overview of the state of the art for voltage detector circuits used in energy-harvesting-powered applications, highlighting their limitations. In order to address the drawbacks of solutions currently available in the literature, this paper has proposed a novel voltage monitoring circuit solution, relying on cascading PMOS-based and NMOS-based voltage detectors. The proposed voltage monitoring circuit enables power consumption minimization and allows implementing a wide range of trigger voltages, supporting easy tunability without requiring several iterations of numerical simulations. With respect to a standard 3T voltage monitor with the same trigger voltage, the designed 800 mV voltage detector employing a triple-well device exhibits up to a 1736× power consumption reduction while featuring 3.87× less area occupation (considering a preliminary area estimation), whereas the proposed standard-devices-only solution does not offer a significant area advantage but allows reducing the power consumption up to 427 times. The proposed voltage monitoring solution thus clearly outperforms the state of the art when considering ultra-low-power energy harvesting applications.