In the original publication [1], the data in Table 2 should be corrected due to typographical mistakes. A correction has been made to Table 2:
Original table:
Table 2.
Count signals for 3–5 level DWT.
Table 2.
Count signals for 3–5 level DWT.
| cnt3[3:0] | cnt4[1:0] | cnt5[1:0] | Level | Module |
|---|---|---|---|---|
| 0–3 | × | × | 3 | 1 |
| 4–7 | × | × | 3 | 2 |
| 8–11 | × | × | 3 | 3 |
| 9–12 | 1 | × | 4 | 1 |
| 9–12 | 2 | × | 4 | 2 |
| 9–12 | 3 | × | 4 | 3 |
| 9–12 | 4 | 1 | 5 | 1 |
| 9–12 | 4 | 2 | 5 | 2 |
| 9–12 | 4 | 3 | 5 | 3 |
| 9–12 | 4 | 4 | N | N |
Corrected table:
Table 2.
Count signals for 3–5-level DWT.
Table 2.
Count signals for 3–5-level DWT.
| cnt3[3:0] | cnt4[1:0] | cnt5[1:0] | Level | Module |
|---|---|---|---|---|
| 0–3 | × | × | 3 | 1 |
| 4–7 | × | × | 3 | 2 |
| 8–11 | × | × | 3 | 3 |
| 12–15 | 0 | × | 4 | 1 |
| 12–15 | 1 | × | 4 | 2 |
| 12–15 | 2 | × | 4 | 3 |
| 12–15 | 3 | 0 | 5 | 1 |
| 12–15 | 3 | 1 | 5 | 2 |
| 12–15 | 3 | 2 | 5 | 3 |
| 12–15 | 3 | 3 | N | N |
Additionally, some numbers in paragraph 2 in Section 3, Subsection 3.4 that are based on Table 2 should be corrected:
Original: “When cnt3 ranges from 12 to 15, the fourth-level DWT is executed for the first, second, and third tile blocks, contingent upon cnt4 values of 1, 2, and 3, respectively. Likewise, with cnt3 ranging from 12 to 15 and cnt4 set to 4, the fifth-level DWT is performed on the first, second, and third tile blocks based on cnt5 values of 1, 2, and 3. No calculations are conducted when cnt3 is between 12 and 15 and both cnt4 and cnt5 are set to 4”.
Corrected: “When cnt3 ranges from 12 to 15, the fourth-level DWT is executed for the first, second, and third tile blocks, contingent upon cnt4 values of 0, 1, and 2, respectively. Likewise, with cnt3 ranging from 12 to 15 and cnt4 set to 3, the fifth-level DWT is performed on the first, second, and third tile blocks based on cnt5 values of 0, 1, and 2. No calculations are conducted when cnt3 is between 12 and 15 and both cnt4 and cnt5 are set to 3”.
The authors state that the scientific conclusions are unaffected. This correction was approved by the Academic Editor. The original publication has also been updated.
Reference
- Li, Q.; Zhang, W.; Wu, Z.; Dai, Y.; Liu, Y. An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules. Electronics 2024, 13, 4668. [Google Scholar] [CrossRef]
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