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Article

Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control

1
State Grid Heilongjiang Electric Power Research Institute, Harbin 150032, China
2
College of New Energy, Harbin Institute of Technology, Weihai 264200, China
*
Author to whom correspondence should be addressed.
Electronics 2025, 14(24), 4888; https://doi.org/10.3390/electronics14244888
Submission received: 5 November 2025 / Revised: 3 December 2025 / Accepted: 10 December 2025 / Published: 12 December 2025
(This article belongs to the Section Power Electronics)

Abstract

This paper presents a novel approach to reduce harmonic distortion and mitigate zero-sequence circulating current (ZSCC) in parallel active power filters (APFs). By employing Dual-Comparison One-Cycle Control (DC-OCC), this method effectively reduces harmonics. Carrier asynchronization among inverter modules in parallel configurations leads to the generation of ZSCC, which distorts output waveforms and reduces system efficiency. A mathematical model is developed to decompose ZSCC into low-, medium-, and high-frequency components, revealing how these components are influenced by carrier-phase deviations. Based on this model, a ZSCC extraction and compensation scheme is proposed. This method enables effective suppression of ZSCC without requiring additional components, communication links, or sensors. Simulation and experimental results demonstrate that the proposed approach achieves significant harmonic suppression, improved power factor, and a peak efficiency of 98.7%, confirming the effectiveness of the control strategy in practical applications.

1. Introduction

The proliferation of nonlinear loads in modern power systems has significantly increased harmonic pollution, leading to deteriorated power quality, additional losses, and potential equipment damage. APFs have emerged as an effective solution for harmonic suppression and reactive power compensation [1,2]. Among various topologies, the parallel inverter configuration is particularly suitable for high-power and high-capacity APF systems [3,4].
Recent developments in APF control strategies have shifted toward stability-aware and decentralized approaches. An admittance-based control method has been proposed to reshape harmonic control loops, significantly improving current sharing performance in multi-parallel systems [5]. Subsequent research has further advanced decentralized control strategies, with comprehensive overviews highlighting communication-less solutions for enhanced system robustness [6,7,8].
However, a critical challenge in such parallel systems is the occurrence of ZSCC caused by carrier asynchronization among modules. These circulating currents increase switching losses, distort output waveforms, and severely degrade harmonic suppression performance [9,10]. This persistent issue underscores the need for integrated solutions that address both external harmonic compensation and internal circulating current behavior.
One-Cycle Control (OCC) has gained attention as a viable alternative to conventional voltage-oriented control, offering simplified implementation through its single-loop, sensorless architecture [11]. Conventional OCC (C-OCC) regulates the current by comparing the instantaneous input current with a sawtooth carrier within each switching cycle [12]. However, C-OCC suffers from inherent limitations including light-load instability and steady-state dc offset, which lead to asymmetric current waveforms and increased low-frequency harmonics. Modified OCC schemes [12] have been proposed to alleviate these drawbacks, for example, by injecting a fictitious current or using additional sensing and digital processing. While effective, these schemes typically retain a single-comparator structure, often implement bipolar PWM, and usually require grid-voltage sensors or more complex digital controllers, thereby increasing implementation complexity.
The DC-OCC scheme, originally developed for grid-connected converters, represents a substantial improvement over C-OCC. By introducing a second comparator with an inverted carrier, DC-OCC regulates both the peak and valley inductor currents within each switching period [13]. This dual-point regulation inherently eliminates dc offset and light-load instability, produces symmetric current waveforms, and realizes unipolar PWM without grid-voltage sensing [13,14,15].
When OCC-based strategies are applied to parallel APF systems, circulating currents remain a significant challenge that is not explicitly addressed by existing OCC variants. Current suppression methods can be categorized into three approaches. Hardware-based methods utilize isolation transformers, coupled inductors, or interphase reactors to block circulating-current paths [16,17], but at the expense of increased size, cost, and losses. Modulation-based methods rely on carrier interleaving and specialized PWM patterns, such as interleaved discontinuous PWM and modified interleaving techniques [18,19], which are effective for high-frequency circulating-current reduction but depend critically on precise carrier synchronization. Control-based approaches include virtual-impedance methods [20,21], observer-based estimation techniques [22], and decentralized control strategies [23]; while flexible, they often involve nontrivial controller design, sensitive dynamic interactions, and sometimes inter-module communication [23].
While valuable, existing methods typically require additional components, precise synchronization, complex dynamics, or inter-module communication. These limitations motivate an integrated solution that leverages DC-OCC’s advantages while providing effective circulating-current suppression without additional complexity.
This paper makes the following contributions:
(1)
DC-OCC is employed as the inner current controller of each shunt APF module. Compared with conventional and modified OCC schemes, the proposed system eliminates steady-state dc offset and light-load instability, inherently realizes unipolar PWM without grid-voltage sensing, and achieves symmetric, low-distortion compensation currents with high efficiency and near-unity power factor in a multi-module configuration.
(2)
A unified circulating-current model is established that decomposes the ZSCC into low-, medium-, and high-frequency components as a function of carrier-phase deviation, providing new insight into circulating-current generation mechanisms in parallel APF systems.
(3)
A ZSCC extraction and compensation scheme is proposed. By adapting the emulated resistance of each module based on the extracted ZSCC component, the method suppresses circulating currents without additional magnetic components, explicit virtual-impedance synthesis, or inter-module communication.
The paper is organized as follows: Section 2 presents the principles of One-Cycle Control. Section 3 discusses the formation and characteristics of circulating currents caused by carrier asynchronization. Section 4 provides the simulation results that validate the proposed method. Section 5 presents the experimental results. Finally, Section 6 provides the conclusions.

2. One-Cycle Control

The corresponding controller structure for C-OCC are shown in Figure 1. Under the standard assumptions outlined in [24], the control law of the C-OCC can be expressed as:
i s R s = V m ( 1 2 d )
where V m = V dc R s / R e , is is the input current, Rs is the current sensing gain, Vdc is the DC bus voltage, d is the duty ratio of switches S3 and S4, and Re is the emulated resistance.
In C-OCC, the instantaneous error between the sensed input current and the carrier signal is integrated within each switching cycle. The comparator output then determines the switching instants of the power devices such that, over every switching period, the average inductor current equals the reference current scaled by the emulated resistance. As a result, the input current is shaped to follow the grid voltage, enabling near-sinusoidal current injection and almost unity power factor without explicit grid-voltage sensing. These features make the control structure compact.
Figure 2a illustrates the inductor current under C-OCC over one carrier cycle, where imn0, imx0, and imn1 denote the current at the beginning, the peak, and the end of the cycle, respectively. Due to the asymmetric current trajectory, the waveform inherently exhibits a steady-state dc offset and, under light-load conditions, suffers from pronounced distortion near the zero-crossing region. These behaviors directly degrade the harmonic suppression capability of C-OCC. Despite its simplicity and fast transient response, C-OCC has two inherent drawbacks underlying the above behaviors. First, under light-load conditions, the falling slope of the inductor current can become steeper than that of the carrier waveform, so that the current no longer has a well-defined intersection with the carrier within a switching period. This loss of a proper intersection point leads to small-signal instability and severe current distortion near the zero-crossing region. Second, because C-OCC regulates only the peak current within each switching cycle, any asymmetry in the carrier waveform or in the integrator reset process produces a steady-state dc offset in the current waveform. This offset causes waveform asymmetry and additional low-frequency harmonics, thereby degrading the overall power quality.
To overcome these drawbacks, the DC-OCC scheme synthesizes a modified inductor-current waveform within each carrier cycle. The control objective is to ensure that the average inductor current equals the grid voltage scaled by the emulated resistance, i.e., iavg = vs/Re, while maintaining negligible ripple error. This is accomplished by introducing a second comparator, which detects the valley of the current in addition to its peak, thereby guaranteeing two intersection points between the sensed current and the carrier waveform within each switching cycle. The resulting current trajectories for the positive and negative half-cycles of the grid voltage are shown in Figure 2b and Figure 2c, respectively. When the switching frequency is much higher than the grid frequency and the dc-link voltage remains nearly constant within one switching period, imn0imn1, indicating that the average output current is essentially free of steady-state dc offset.
The synthesized current waveform required by DC-OCC is shown in Figure 2b. During the positive half-cycle, the inductor current consists of two rising segments, with slopes m1p and m3p, and one falling segment, with slope m2p. The admissible values of these slopes are determined by the converter switching states: the rising slopes correspond to vs/Ls or (vs + Vdc)/Ls, whereas the falling slope corresponds to (vsVdc)/Ls. For the negative half-cycle [Figure 2c], the slopes m1n, m2n, and m3n satisfy the same relationships with opposite polarity.
The switching states associated with each slope are summarized as follows:
(1)
For a slope of vs/Ls, either switches 2 and 4 or 1 and 3 must be turned ON.
(2)
For a slope of (vs + Vdc)/Ls, switches 3 and 4 must be turned ON.
(3)
For a slope of (vsVdc)/Ls, switches 1 and 2 must be turned ON.
The switching sequence summarized in Table 1 is selected to realize these slopes while minimizing the number of transitions within each carrier cycle, thereby improving efficiency and reducing switching losses. A key outcome of this optimized sequence is that the outer current segments (m1p, m3p, m1n, m3n) exhibit identical slopes in the positive and negative half-cycles of the grid voltage. This symmetry ensures a smooth transition of the current across the zero-crossing and helps to suppress low-frequency distortion as well as steady-state dc offset.
The same switching sequence can be implemented in two equivalent ways by processing either the current waveform or the carrier waveform together with their respective inverses, as illustrated in Figure 3a,b. Both implementations generate identical PWM signals for the bridge switches. An additional advantage of the DC-OCC configuration is that it inherently realizes unipolar PWM, in contrast to the bipolar PWM in C-OCC. Under unipolar modulation, the bridge output voltage switches among +Vdc, 0, and −Vdc, which effectively doubles the apparent switching frequency of the current ripple and shifts the dominant ripple components to higher frequencies. As a result, the THD of the input current is reduced without the need for grid-voltage sensing.
The average current corresponding to the waveform in Figure 2b is subsequently derived as:
i avg = i mn 0 + 1 T s ( i mx 0 i mn 0 ) ( t 1 + t x ) 2 1 T s ( i mn 0 i mn 0 ) ( t 3 + t y ) 2
i avg = i mn 0 + i mx 0 2
At intersection points:
i mx 0 R s = V m 1 2 t 1 T s
i mx 0 R s = V m 1 2 ( T s t 3 ) T s
Using (3), (4) and (5)
i avg = V m R s 1 t 1 + t 3 T s
Applying volt-second balance to the boost inductor, Ls
v s t 1 + ( v s V d c ) t 2 + v s t 3 = 0
where
t 1 + t 2 + t 3 = T s
v s V d c = 1 t 1 + t 3 T s
Using (6) and (9)
i avg = v s R e
Although the above derivation is presented for the positive half-cycle of the grid voltage, an analogous procedure for the negative half-cycle yields the same result as (10), confirming that the DC-OCC scheme produces identical average behavior in both polarities and eliminates any steady-state dc component in the fundamental input current.
The fundamental improvement of the DC-OCC scheme lies in its refined control objective. By synthesizing the current waveform shown in Figure 2b, the controller shifts from the C-OCC approach—where only the peak current is regulated—to a dual-point regulation of both the peak and valley currents. This dual-comparison mechanism directly controls the cycle-averaged inductor current, ensuring that the relationship in (10) holds in every switching period. As a result, DC-OCC inherently eliminates the steady-state dc offset present in conventional OCC and achieves accurate resistive emulation with the desired emulated resistance Re over the entire load range.
Moreover, the inclusion of a second comparator guarantees two intersection points between the sensed current and the carrier (or its inverse) within each switching period. By comparing signals with opposing slopes, the system establishes stable and deterministic switching instants, which mitigates current distortion and improves dynamic response. The resulting symmetrical switching behavior not only enhances waveform linearity but also reduces the harmonic content of the input current.
A practical consideration in DC-OCC operation is the double-switching event that occurs at the boundary between consecutive carrier cycles, as illustrated in Figure 3a,b. At this transition, the converter state toggles between “11” and “00,” both of which apply zero voltage across the bridge terminals. Consequently, this transition is functionally redundant and does not introduce additional switching loss or output distortion.
To realize this control sequence in hardware, a simple digital logic circuit is employed. The desired switching states for switches 1 and 3 during the nth and (n + 1)th carrier cycles are summarized in Table 1. The logic implementation also utilizes an auxiliary input Q, which is generated by a D flip-flop clocked at the switching frequency fsw and driven by the same signal that resets the current integrator in Figure 3. As a result, Q toggles at fsw/2 with a 50% duty ratio. Using Karnaugh maps, the desired states of all switches are simplified to the Boolean expressions in (11) and (12).
g 1 = Q ¯ B + Q A     g 4 = g ¯ 1
g 3 = Q ¯ A + Q B     g 2 = g ¯ 3

3. Zero-Sequence Circulating Current Analysis and Mitigation

3.1. Analysis of Zero-Sequence Circulating Current

Parallel APFs are widely employed in high-power systems for harmonic suppression and power quality enhancement. However, a significant challenge in such systems is the emergence of ZSCC caused by carrier asynchronization among inverter modules. These circulating currents distort the output current waveforms, reduce system efficiency, and degrade the overall filtering performance. To address this issue, a detailed mathematical model is developed that decomposes the circulating current into low-, medium-, and high-frequency components as explicit functions of the carrier-phase deviation. This model reveals how carrier asynchronization and parameter mismatches among modules generate ZSCC, even under interleaved operation. Figure 4 illustrates the equivalent circuit model for the dual-module parallel inverters. Here, UA1N denotes the midpoint voltage of phase A in Module 1; L is the inverter-side inductance; Lg is the grid-side inductance; iA1 is the inductor current of phase A in Module 1; and ia1 refers to the grid current of phase A in Module 1. The subscript J = A, B, C and j = a, b, c denote three-phase quantities, whereas n = 1, 2, corresponds to Module 1 and Module 2, respectively.
The circulating current in phase A, denoted by Iah, is defined as:
I ah = 1 2 i a 1 i a 2
The zero-sequence circulating current Iz is then obtained as:
I z = I ah + I bh + I ch = i a 1 + i b 1 + i c 1 = i a 2 i b 2 i c 2
The voltage difference between the bridge midpoints of phase A in the two modules, which drives the phase-A circulating current, is given by:
U ah = U AlN U A 2 N = 2 L + L g d I ah d t + L d i Ca 1 i Ca 2 d t
where iCa1 represents the phase A current of the filter capacitor in Module 1. the corresponding zero-sequence voltage difference is expressed as
U z = U ah + U bh + U ch
This equation indicates that the circulating current is fundamentally governed by the voltage difference between the bridge midpoints. Therefore, a mathematical model is developed from the perspective of the carrier-phase discrepancy and the resulting bridge-arm voltage difference to systematically analyze the influence of carrier asynchronization on circulating currents.

3.1.1. High-Frequency Component-Carrier Analysis

The derivation begins by assuming that the carrier frequency is much higher than the modulation frequency, so that the modulation wave can be regarded as quasi-static within a single carrier period.
U a = M sin ω s t + U sv
where M is the modulation index, ωs is the angular frequency of the modulating signal, and Usv is the zero-sequence component injected by SVPWM.
The interaction between the phase-A modulating signal Ua and the carrier waveform leads to three distinct operating modes within a switching period. For a given carrier-phase displacement θ (0 ≤ θ ≤ π), and using the normalized modulating signal Ua ∈ [0, 1], the three modes can be defined as
  • Mode 1: Ua ∈ [0, θ/2π];
  • Mode 2: Ua ∈ [θ/2π, 1 − θ/2π];
  • Mode 3: Ua ∈ [1 − θ/2π, 1].
The carrier-phase difference θ directly determines the boundaries of these three operating regions. Different values of θ therefore lead to different voltage differences between the bridge midpoints and, consequently, to different high-frequency circulating-current patterns. The mechanism by which the carrier-phase difference θ produces the bridge-arm midpoint voltage difference in each mode is illustrated in Figure 5.
According to the volt–second balance principle, and assuming a constant DC-link voltage, the amplitude of the high-frequency circulating current is determined by the duration of the positive or negative voltage pulses within each carrier cycle. A longer pulse duration results in a proportionally higher circulating current amplitude.
This relationship can be quantitatively described by the following expression, which links the pulse width of the bridge-arm midpoint voltage difference to the carrier-phase displacement θ:
t = 0 θ 2 π 2 π U a d U a + θ 2 π 1 θ 2 π θ d U a + 1 θ 2 π U m 2 π 1 U a d U a = θ ( 1 θ 2 π ) + π 2 U m 1 U m 2
It is noteworthy that the derived model focuses on the ZSCC components directly generated by carrier asynchrony. Although the harmonic content of the modulation waveform used for load compensation may complicate the low-frequency spectrum, the high-frequency circulating-current component remains a direct and isolated indicator of the carrier-phase difference θ.

3.1.2. Low-Frequency Component—Modulation Wave Analysis

This subsection develops a model for the low-frequency circulating current arising from carrier asynchronization. In contrast to the high-frequency analysis, the variation in the modulation waveform over a carrier cycle must be taken into account for the low-frequency components. As shown in Figure 6, the amplitude of this low-frequency circulating current is determined by the net volt–second area generated by the positive and negative voltage pulses at the bridge-arm midpoints over one fundamental period.
Based on a quasi-linear approximation of the modulation signal within each carrier cycle and by extending the three-mode framework used in the high-frequency analysis, the operating conditions are further refined into five distinct modes. This refined categorization, illustrated in Figure 7, is determined by the initial phase relationship between the carrier and the modulating waveform, which can be characterized by the normalized parameters θ/π and U0, where U0 denotes the normalized initial value of the modulating signal. To quantify the volt–second area that governs the low-frequency circulating current, the time difference between the positive and negative voltage pulses at the bridge-arm midpoint must be evaluated for each mode. Taking Mode 1 as a representative case, the key time instants (t1,t2,t3,t4) marking the pulse transitions and the resulting duration difference Δt1 are derived as
U t 1 + U 0 = t 1 π , U t 2 + U 0 = t 2 θ π U t 3 + U 0 = t 3 θ π , U t 4 + U 0 = t 4 2 π π Δ t 1 = 2 π t 4 + t 1 t 3 t 2 = 2 U θ π U π 1 / U 2 1 π 2
while the duration differences for Modes 2–5 are given by:
Δ t 2 = 2 π t 4 + t 2 t 3 t 1 = 2 U θ π U π 1 / U 2 1 π 2 Δ t 3 = 2 π t 3 + t 1 2 π t 4 + t 2 = 2 U θ π / U 2 1 π 2 Δ t 4 = 2 π t 3 + t 2 t 4 t 1 = 2 U θ π U π 1 / U 2 1 π 2 Δ t 5 = 2 π t 2 + t 1 2 π t 4 + t 3 = 2 U θ π / U 2 1 π 2
Based on (19) and (20), the net difference between the positive and negative pulse durations at the bridge-arm midpoint is integrated with respect to the modulation waveform over the interval [0, Um]. This integral quantifies the net volt–second effect and yields the effective voltage-pulse duration T, which characterizes the low-frequency circulating-current component.
When θ < 2π/3, the effective pulse duration T corresponding to the low-frequency circulating current is given by
T = 0 θ 2 π 2 U θ / π U π 1 U 2 ( 1 / π ) 2 d U a + θ 2 π θ π 2 U θ / π U π 1 U 2 1 / π 2 d U a + θ π 1 θ 2 π 2 U θ / π U 2 1 / π 2 d U a + 1 θ 2 π U m 2 U θ / π U 2 1 / π 2 d U a
When θ ≥ 2π/3, the voltage pulse duration T corresponding to the low-frequency circulating current is given by:
T = 0 θ 2 π 2 U θ / π U π 1 U 2 1 / π 2 d U a + θ 2 π 1 θ 2 π 2 U θ / π U π 1 U 2 1 / π 2 d U a + 1 θ 2 π θ π 2 U θ / π U π 1 U 2 1 / π 2 d U a + θ π U m 2 U θ / π U 2 1 / π 2 d U a
By combining the above relationships, the following expression is obtained:
T = 0 θ π 2 U θ π U π 1 U 2 1 π 2 d U a + θ π U m 2 U θ π U 2 1 π 2 d U a
Based on (23), the characteristic curve of the low-frequency circulating current induced by carrier asynchronization can be constructed. Figure 8a,b show the waveform profiles obtained from the theoretical analysis, while Figure 8c presents the corresponding simulation results. The close agreement between the theoretical and simulated waveforms validates the analytical model. The amplitude of this low-frequency circulating current, denoted as Ihm in Figure 8, varies with the carrier-phase difference θ, and the corresponding time duration associated with Ihm is determined by
t = 0 θ π 2 U θ π U π 1 U 2 1 π 2 d U a = 2 U θ π U π 1 U 2 1 π 2 θ π
From (24), and under the condition U’ << 1/π, the low-frequency components of both the phase-A circulating current and the zero-sequence circulating current exhibit distinct trends over different ranges of the carrier-phase difference θ. Specifically, these components increase approximately monotonically with θ in the range 0 ≤ θ ≤ π/2, and then decrease monotonically for π/2 ≤ θ ≤ π. This non-monotonic dependence implies that the magnitude of the low-frequency zero-sequence circulating current alone cannot be used as a reliable indicator of the carrier-phase difference.
By synthesizing the relationships established in (20) and (24), the overall mathematical representation linking the frequency components of the circulating current to the carrier-phase difference θ can be formulated as follows:
I h 1 = θ 1 θ 2 π + π 2 U m 1 U m 2 U d 2 Z I h 2 = 2 U θ π U π 1 U 2 1 π 2 θ π U d 2 Z I h = I h 1 + I h 2
where Ih1 represents the high-frequency component of the circulating current, Ih2 represents the low-frequency component, Ih denotes the combined high- and low-frequency circulating current, and Z is the equivalent impedance. The zero-sequence circulating current Iz can also be represented by (25), corresponding to the waveform curve shown in Figure 8c.

3.2. Extraction Method for Circulating Current Components

The preceding analysis reveals distinct and inconsistent characteristics between the high-frequency and low-frequency components of the ZSCC. Consequently, conventional methods that attempt to use the raw ZSCC directly for closed-loop carrier synchronization are likely to be ineffective, as the composite signal does not provide a consistent correlation with the carrier-phase difference.
To overcome this limitation, this section proposes a method for extracting specific circulating-current components that accurately reflect the carrier-phase discrepancy. The proposed extraction process, illustrated in Figure 9 and Figure 10, consists of two key steps. First, as summarized in Figure 9, the ZSCC is classified according to the monotonicity of its frequency components with respect to the carrier-phase shift. This yields three primary scenarios: (1) high-frequency monotonic and low-frequency non-monotonic (HF-M/LF-NM), (2) both high- and low-frequency components monotonic (HF-M/LF-M), and (3) high-frequency non-monotonic and low-frequency monotonic (HF-NM/LF-M). The mid-frequency components, which are mainly induced by system resonances, are excluded in this step. This monotonicity-based decomposition enables the identification of candidate ZSCC components suitable for closed-loop control.
On this basis, Figure 10 provides a secondary classification of the ZSCC based on the relative magnitudes of its frequency components, characterized by their attenuation coefficients. This analysis distinguishes three scenarios: (1) the high-frequency component significantly dominates the low-frequency component, (2) the low-frequency component significantly dominates the high-frequency component, and (3) both components are of a comparable order of magnitude. By combining the monotonicity classification in Figure 9 with the attenuation-based classification in Figure 10, a definitive selection criterion is established. This integrated framework enables the deterministic identification of the optimal ZSCC component—either high-frequency or low-frequency—to be used for calculating the carrier-phase compensation, thereby ensuring an effective and reliable feedback signal for synchronization.
Based on the proposed extraction method, the attenuation coefficients of the different frequency components within the ZSCC are quantitatively evaluated and compared for the given topology. To this end, an equivalent circuit model of the improved LCL filter, dedicated to characterizing the ZSCC path, is established, as shown in Figure 11. This model is used to derive the network impedance over a wide frequency range, thereby revealing the intrinsic attenuation characteristics of the high-frequency and low-frequency circulating-current components.
Using (25) together with the equivalent circuit in Figure 11, the transfer functions that characterize the high-frequency and low-frequency zero-sequence circulating currents can be derived as
I z 1 U d = 3 2 G LCL j ω c θ 1 θ 2 π I Z 2 U d = 3 2 G LCL j ω s 2 U θ π U π 1 U 2 1 π 2 θ π G LCL ( s ) = 1 2 s L + L g + L m + 2 s 3 L g + L m L C
where ωc is the angular frequency of the carrier. A comparison of the attenuation coefficients obtained from (26) reveals that while both the high- and low-frequency components exhibit similar orders of magnitude, the high-frequency component has a smaller attenuation. More importantly, the high-frequency component maintains a monotonic relationship with the carrier-phase shift, in contrast to the low-frequency component. As such, the extraction framework outlined earlier clearly identifies the high-frequency component of the ZSCC as the optimal choice for the subsequent PI control calculation, offering a more reliable and predictable feedback signal for carrier-phase compensation.
G LCL j ω c < G LCL j ω s 2 U ω s π ω c U 2 1 π 2
From (27), it can be concluded that, while both components have similar attenuation coefficients, the high-frequency component exhibits a monotonic relationship with the carrier-phase shift, making it the most suitable candidate for feedback. While (27) provides the analytical relation under ideal conditions, practical implementation must account for non-ideal effects such as dead time, parameter tolerances, and measurement noise. Nevertheless, the compensation strategy remains effective because the monotonic relationship between the carrier-phase error and the high-frequency ZSCC component holds under realistic operating conditions.
The high-frequency component of the zero-sequence circulating current thus serves as a direct and reliable indicator of the carrier-phase difference. Consequently, the circulating-current component extraction block in this work is specifically implemented as a high-frequency extraction unit. It incorporates a virtual notch filter to suppress the mid-frequency resonance peak, combined with a high-pass filter function to attenuate the low-frequency components. Here, G1(s) and G2(s) represent the high-frequency component extraction transfer functions for Module 1 and Module 2, respectively.
Carrier synchronization between modules is achieved through a dedicated control loop, as depicted in Figure 12. This loop samples the zero-sequence circulating current of each module and uses the error between the reference value Izref and the measured value Iz as its input. A high-frequency component extraction function is first applied to this error signal. By isolating the high-frequency component—which monotonically and reliably correlates with the carrier-phase discrepancy—the scheme uses this component as a feedback variable representing the phase misalignment. The extracted signal is then processed by a PI controller, which generates the required carrier-phase compensations Δθ1 and Δθ2. These compensation values are added to the TBPRD registers in the DSP, thereby adjusting the carrier period counter and dynamically aligning the carrier-phases of the parallel modules.

4. Simulation Results

Simulations were carried out using MATLAB/Simulink (version R2023b), and the system parameters along with component ratings are summarized in Table 2.
To validate the effectiveness of the proposed ZSCC suppression strategy, its performance is evaluated against three control schemes: (1) no carrier-phase control, (2) traditional carrier-phase control (without circulating-current component extraction), and (3) the improved carrier-phase control (with circulating-current component extraction). The comparative results, shown in Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17, demonstrate that the improved carrier-phase control, which integrates the novel circulating-current component extraction mechanism.
When the system experiences impedance mismatch and carrier asynchronization, the zero-sequence circulating current waveforms are shown in Figure 13.
As observed in Figure 14, the magnitude of the zero-sequence circulating current containing low- and medium-frequency components increases in the range of [0°, 90°] and decreases in the range of [90°, 180°]. In contrast, the circulating current containing only high-frequency components increases monotonically across the entire range of [0°, 180°]. These simulation results are consistent with the analytical trends predicted in Section 3, where the low-frequency ZSCC component exhibits a non-monotonic dependence on θ, whereas the high-frequency component increases monotonically with the carrier-phase shift. This agreement indirectly supports the attenuation characteristics summarized in (27).
The performance of a traditional carrier-phase control, which lacks the circulating current component extraction mechanism, was tested by activating it at t = 0.1 s. The resulting waveforms in Figure 16 demonstrate its limitations: the persistence of significant ZSCC amplitude indicates inadequate suppression capability, while the distorted phase-A current waveform reflects a failure to achieve proper carrier synchronization between the parallel modules.
In contrast, the proposed improved carrier-phase control strategy demonstrates remarkable performance enhancement when activated at t = 0.1 s. The subsequent dynamic response, shown in Figure 17, demonstrates significant performance improvement.
A quantitative analysis of the RMS values for different ZSCC components before and after control activation is provided in Table 3. The ZSCC amplitude, categorized into low-frequency (150 Hz), medium-frequency (2850 Hz), and high-frequency (16.2 kHz) components, serves as the metric for evaluating suppression capability. Concurrently, the reduction in phase-A circulating current validates the effectiveness of carrier synchronization.
Figure 18 shows the grid current before the APF was activated, which is severely distorted due to the nonlinear load, resulting in a high THD value of 2.05%. After applying the proposed control strategy, the grid current becomes nearly sinusoidal, with a significantly reduced THD of 0.96%. These measurements are critical for validating the effectiveness of the proposed approach in mitigating harmonic distortion.

5. Experimental Results

The experimental platform used for this study is shown in Figure 19. To validate the effectiveness of the proposed ZSCC suppression strategy, its performance was evaluated under three control strategies: (1) no carrier-phase control, (2) traditional carrier-phase control (without circulating-current component extraction), and (3) the improved carrier-phase control (with circulating-current component extraction). The experimental waveforms for circulating current and phase current under these three conditions are compared to assess the effectiveness of the proposed strategy.
During the actual operation of the parallel system, the carrier-phase difference between modules fluctuates within the range of 0–180° when no carrier synchronization control is applied, as shown in Figure 20 and Figure 21.
However, the experimental results for the low-frequency component of the zero-sequence circulating current do not fully align with the theoretical and simulation predictions, as clearly evidenced by comparing the idealized trends in Figure 21 with the more irregular experimental data in the subsequent figure. This discrepancy arises because the theoretical model is predicated on the assumption that carrier asynchrony is the sole influencing factor. In practice, the low- and medium-frequency components of the ZSCC are also susceptible to other non-ideal conditions, such as variations in device parameters, grid voltage fluctuations, and electromagnetic interference. This observed deviation in the low-frequency component further validates the strategic decision in our control design to rely on the high-frequency component for feedback, as the latter demonstrates a more stable and predictable relationship with the carrier-phase difference θ under real-world operating conditions.
The experimental waveforms without control are shown in Figure 22, where the RMS value of the single-phase circulating current is 11.72 A, and the RMS value of the high-frequency ZSCC is 0.343 A.
The experimental waveforms under traditional carrier-phase control are shown in Figure 23. The RMS value of the high-frequency ZSCC is 0.281 A, indicating partial suppression of the circulating current.
Under the improved control strategy, the experimental waveforms shown in Figure 24 reveal significant improvements. The RMS value of the single-phase circulating current is reduced to 3.61 A, while the RMS value of the high-frequency ZSCC is further suppressed to 0.174 A.
The RMS values of the circulating currents at different frequencies under the three control strategies are listed in Table 4.
As shown in Table 4, compared with the no-control case, the improved control strategy with circulating-current component extraction demonstrates strong ZSCC suppression capability: the high-frequency component is reduced by 49.3%, the medium-frequency component by 49.3%, the low-frequency component by 19%, and the single-phase circulating current by 69.2%. Compared with the traditional control strategy, the improved control shows even better performance: the high-frequency component is reduced by 38.1%, the medium-frequency component by 45%, the low-frequency component by 37.8%, and the single-phase circulating current by 62%. Despite practical limitations such as interference and delays, the improved control can effectively constrain the carrier-phase difference between modules within 30°. These experimental results verify the correctness of the mathematical model and the effectiveness of the circulating current component extraction and suppression method.
The load transient waveforms under the proposed DC-OCC scheme are shown in Figure 25. In Figure 25a, the output power steps from 300 W to 1000 W. During this load increase, the dynamic response time is approximately 260 ms. The maximum voltage undershoot is 9.58 V (2.395% of the output voltage), and the maximum overshoot is 10.36 V (2.590% of the output voltage). In Figure 25b, the load decreases from 1000 W to 300 W, with a corresponding response time of about 190 ms. The maximum overshoot and undershoot are 13.59 V (3.398%) and 5.90 V (1.475%), respectively. These results demonstrate that the proposed DC-OCC strategy provides fast and well-damped dynamic performance, maintaining a stable DC-link voltage with small overshoot and undershoot during rapid load transitions.
The grid current before and after compensation is now analyzed and compared. Figure 26 shows the grid current before the APF was activated, which is severely distorted due to the nonlinear load, resulting in a high THD value of 2.25%. After applying the proposed control strategy, the grid current becomes nearly sinusoidal, with a significantly reduced THD of 1.1%. These measurements are critical for validating the effectiveness of the proposed approach in mitigating harmonic distortion.
Figure 27 and Figure 28 compare the efficiency and power factor (PF) of the proposed DC-OCC scheme with those of conventional C-OCC under different load conditions. As shown in Figure 25, the converter achieves a peak efficiency of 98.7% and maintains efficiency above 96% across the entire load range. In contrast, the conventional C-OCC demonstrates lower efficiency, particularly under light-load conditions (below 20% of the rated power). Similarly, Figure 27 shows that the proposed control achieves a unity power factor (1.000) at rated power, while also significantly improving performance at light load (below 20% of the rated power).
At Po = 100 W (6.7% of the rated power), the DC-OCC achieves 10.8% higher efficiency and a 0.282 improvement in power factor compared with the conventional OCC method. These results confirm that the proposed control strategy effectively enhances both efficiency and power factor, particularly under light-load conditions, ensuring highly efficient, stable, and low-distortion operation across a wide load range.

6. Conclusions

The Dual-Comparison One-Cycle Control (DC-OCC) strategy proposed in this paper effectively mitigates zero-sequence circulating current (ZSCC) caused by carrier asynchronization in parallel active power filters (APFs), significantly improving harmonic suppression performance. By introducing a dual-comparator mechanism, DC-OCC simultaneously regulates the peak and valley values of the inductor current, eliminating steady-state DC offset, ensuring symmetrical current waveforms, and enhancing dynamic stability across the entire load range. A unified circulating-current model is also developed, analyzing the influence of carrier-phase deviations on the frequency components of ZSCC. Furthermore, a ZSCC extraction and compensation scheme is proposed that requires no additional components or inter-module communication. Simulation and experimental results validate the effectiveness of the proposed method, showing a significant reduction in circulating current amplitude, with a peak efficiency of 98.7% and a high power factor maintained across varying loads. This strategy provides a reliable, efficient, and easy-to-implement solution for circulating current suppression in multi-module APF systems.

Author Contributions

Conceptualization, S.R.; methodology, F.M.; software, J.C. and B.G.; validation, B.G., Z.M. and J.C.; formal analysis, B.G. and X.L.; investigation, Z.M.; data curation, S.Y. and J.G.; writing—original draft preparation, S.R., J.G. and K.Y.; writing—review and editing, P.Z. and K.Y.; visualization, J.C., S.Y. and B.G.; supervision, S.R. and F.M.; project administration, S.R.; funding acquisition, S.R. and F.M. All authors have read and agreed to the published version of the manuscript.

Funding

State Grid Corporation of China Technology Project, 52243725000C; National Natural Science Foundation of China, 51777042.

Data Availability Statement

The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflicts of interest.

Abbreviations

The following abbreviations are used in this manuscript:
APFActive Power Filter
OCCOne-Cycle Control
C-OCCConventional One-Cycle Control
VOCVoltage-oriented Control
DC-OCCDual-Comparison One-Cycle Control

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Figure 1. Controller structure of C-OCC.
Figure 1. Controller structure of C-OCC.
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Figure 2. Current in a carrier cycle for positive half-cycle of grid voltage (a) C-OCC, (b) DC-OCC, and (c) for negative half cycle of grid voltage, DC-OCC.
Figure 2. Current in a carrier cycle for positive half-cycle of grid voltage (a) C-OCC, (b) DC-OCC, and (c) for negative half cycle of grid voltage, DC-OCC.
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Figure 3. Carrier and current for two switching cycles: (a) current-inverted and (b) carrier-inverted modulation methods.
Figure 3. Carrier and current for two switching cycles: (a) current-inverted and (b) carrier-inverted modulation methods.
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Figure 4. Parallel equivalent model of dual module inverter.
Figure 4. Parallel equivalent model of dual module inverter.
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Figure 5. Voltage difference at the midpoint of the bridge arm generated by three modes. (a) Mode 1. (b) Mode 2. (c) Mode 3.
Figure 5. Voltage difference at the midpoint of the bridge arm generated by three modes. (a) Mode 1. (b) Mode 2. (c) Mode 3.
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Figure 6. Formation of low-frequency circulation.
Figure 6. Formation of low-frequency circulation.
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Figure 7. Five modes of low-frequency modulation wave variation.
Figure 7. Five modes of low-frequency modulation wave variation.
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Figure 8. Low-frequency circulation waveform curve. (a) Theoretical waveform of Ua. (b) Theoretical waveform of Ih. (c) Simulation results of Ih and Iz.
Figure 8. Low-frequency circulation waveform curve. (a) Theoretical waveform of Ua. (b) Theoretical waveform of Ih. (c) Simulation results of Ih and Iz.
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Figure 9. Determination of monotonicity of zero-sequence circulating current at different frequencies.
Figure 9. Determination of monotonicity of zero-sequence circulating current at different frequencies.
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Figure 10. Categorization of zero-sequence circulating current characteristics based on attenuation coefficients.
Figure 10. Categorization of zero-sequence circulating current characteristics based on attenuation coefficients.
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Figure 11. Equivalent model for zero-sequence circulating current of improved LCL filter.
Figure 11. Equivalent model for zero-sequence circulating current of improved LCL filter.
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Figure 12. Schematic diagram of zero-sequence circulating current-based carrier-phase synchronization control.
Figure 12. Schematic diagram of zero-sequence circulating current-based carrier-phase synchronization control.
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Figure 13. Simulation waveform under carrier asynchronization.
Figure 13. Simulation waveform under carrier asynchronization.
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Figure 14. Simulation Waveform without Control.
Figure 14. Simulation Waveform without Control.
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Figure 15. Simulation results of circulating current under different carrier-phase shifts θ. (a) ZSCC at different frequencies. (b) Circulating current in phase A.
Figure 15. Simulation results of circulating current under different carrier-phase shifts θ. (a) ZSCC at different frequencies. (b) Circulating current in phase A.
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Figure 16. Simulation waveform under traditional carrier-phase control without circulating-current component extraction. (a) ZSCC. (b) Phase current.
Figure 16. Simulation waveform under traditional carrier-phase control without circulating-current component extraction. (a) ZSCC. (b) Phase current.
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Figure 17. Simulation waveform under improved control.
Figure 17. Simulation waveform under improved control.
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Figure 18. Simulation waveforms of the grid current (a) before and (b) after applying the proposed control strategy.
Figure 18. Simulation waveforms of the grid current (a) before and (b) after applying the proposed control strategy.
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Figure 19. Experimental platform.
Figure 19. Experimental platform.
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Figure 20. Experimental waveforms of zero sequence circulating current with different phase differences.
Figure 20. Experimental waveforms of zero sequence circulating current with different phase differences.
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Figure 21. Experimental waveforms of ZSCC with different θ. (a) ZSCC at different frequencies. (b) Circulating current in phase A.
Figure 21. Experimental waveforms of ZSCC with different θ. (a) ZSCC at different frequencies. (b) Circulating current in phase A.
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Figure 22. Experimental waveform without control (θ = 180°). (a) Phase and circulating currents. (b) ZSCC.
Figure 22. Experimental waveform without control (θ = 180°). (a) Phase and circulating currents. (b) ZSCC.
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Figure 23. Experimental waveforms under traditional carrier-phase control. (a) Phase and circulating currents. (b) ZSCC.
Figure 23. Experimental waveforms under traditional carrier-phase control. (a) Phase and circulating currents. (b) ZSCC.
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Figure 24. Experimental waveform under improved control. (a) Phase and circulating currents. (b) ZSCC.
Figure 24. Experimental waveform under improved control. (a) Phase and circulating currents. (b) ZSCC.
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Figure 25. Load transient test waveforms. (a) Dynamic response under load increase. (b) Dynamic response under load decrease.
Figure 25. Load transient test waveforms. (a) Dynamic response under load increase. (b) Dynamic response under load decrease.
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Figure 26. Grid current (a) before and (b) after applying the proposed control strategy.
Figure 26. Grid current (a) before and (b) after applying the proposed control strategy.
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Figure 27. APF efficiency at different input voltage and power levels.
Figure 27. APF efficiency at different input voltage and power levels.
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Figure 28. APF power factor at different input voltage and power levels.
Figure 28. APF power factor at different input voltage and power levels.
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Table 1. Selected switching sequence for the DC-OCC.
Table 1. Selected switching sequence for the DC-OCC.
Grid VoltageTime and SlopeSwitch ONState of Converter
vs > 0t1, m1p = vs/Ls4, 20, 0
t2, m2p = (vsVdc)/Ls1, 21, 0
t3, m3p = vs/Ls1, 31, 1
vs < 0t1, m1n = vs/Ls4, 20, 0
t2, m2n = (vs + Vdc)/Ls4, 30, 1
t3, m3n = vs/Ls1, 31, 1
Table 2. Simulation and experimental parameters.
Table 2. Simulation and experimental parameters.
ParameterValue
Po1500 W
vs230 V
Vdc440 V
fs50 Hz
fsw16.2 KHz
Ls (mH, pu)8 mH, 0.095 pu
Cdc (uF, pu)1650 uF, 13.71 pu
Vb500 V
Ug230 V
Lg4.25 uH
Rg0.1 Ω
Rb13.2 Ω
Kp0.1
Ki0.01
Table 3. Simulation FFT RMS of Circulating Current.
Table 3. Simulation FFT RMS of Circulating Current.
ZCSSLowMiddleHighPhase A CC
45°0.287/0.0240.006/0.0060.112/0.0037.34/0.29
90°0.670/0.0250.034/0.0030.195/0.00211.51/0.26
135°0.336/0.0300.010/0.0050.246/0.00412.96/0.24
180°0.069/0.0870.003/0.0050.270/0.00213.41/0.25
Note: The data in Table 3 (e.g., 0.287/0.024) correspond to the cases without control/with control in Figure 15 and Figure 17, respectively.
Table 4. RMS values of circulating currents at different frequencies before and after applying the suppression strategy.
Table 4. RMS values of circulating currents at different frequencies before and after applying the suppression strategy.
Control MethodLF-ZSCC(A)MF-ZSCC (A)HF-ZSCC (A)Phase A Circulating Current(A)
without control0.2110.1520.34311.72
traditional control0.2750.140.2819.5
improved control0.1710.0770.1743.61
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MDPI and ACS Style

Rong, S.; Gu, B.; Meng, F.; Cui, J.; Mu, Z.; Lei, X.; Guan, J.; Ye, K.; Zhang, P.; Yong, S. Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control. Electronics 2025, 14, 4888. https://doi.org/10.3390/electronics14244888

AMA Style

Rong S, Gu B, Meng F, Cui J, Mu Z, Lei X, Guan J, Ye K, Zhang P, Yong S. Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control. Electronics. 2025; 14(24):4888. https://doi.org/10.3390/electronics14244888

Chicago/Turabian Style

Rong, Shuang, Bowen Gu, Fangang Meng, Jiapeng Cui, Zexin Mu, Xueting Lei, Jianan Guan, Kailai Ye, Pengju Zhang, and Shengren Yong. 2025. "Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control" Electronics 14, no. 24: 4888. https://doi.org/10.3390/electronics14244888

APA Style

Rong, S., Gu, B., Meng, F., Cui, J., Mu, Z., Lei, X., Guan, J., Ye, K., Zhang, P., & Yong, S. (2025). Harmonic Suppression and Circulating Current Mitigation in Parallel Active Power Filters Using Dual-Comparison One-Cycle Control. Electronics, 14(24), 4888. https://doi.org/10.3390/electronics14244888

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