1. Introduction
The proliferation of nonlinear loads in modern power systems has significantly increased harmonic pollution, leading to deteriorated power quality, additional losses, and potential equipment damage. APFs have emerged as an effective solution for harmonic suppression and reactive power compensation [
1,
2]. Among various topologies, the parallel inverter configuration is particularly suitable for high-power and high-capacity APF systems [
3,
4].
Recent developments in APF control strategies have shifted toward stability-aware and decentralized approaches. An admittance-based control method has been proposed to reshape harmonic control loops, significantly improving current sharing performance in multi-parallel systems [
5]. Subsequent research has further advanced decentralized control strategies, with comprehensive overviews highlighting communication-less solutions for enhanced system robustness [
6,
7,
8].
However, a critical challenge in such parallel systems is the occurrence of ZSCC caused by carrier asynchronization among modules. These circulating currents increase switching losses, distort output waveforms, and severely degrade harmonic suppression performance [
9,
10]. This persistent issue underscores the need for integrated solutions that address both external harmonic compensation and internal circulating current behavior.
One-Cycle Control (OCC) has gained attention as a viable alternative to conventional voltage-oriented control, offering simplified implementation through its single-loop, sensorless architecture [
11]. Conventional OCC (C-OCC) regulates the current by comparing the instantaneous input current with a sawtooth carrier within each switching cycle [
12]. However, C-OCC suffers from inherent limitations including light-load instability and steady-state dc offset, which lead to asymmetric current waveforms and increased low-frequency harmonics. Modified OCC schemes [
12] have been proposed to alleviate these drawbacks, for example, by injecting a fictitious current or using additional sensing and digital processing. While effective, these schemes typically retain a single-comparator structure, often implement bipolar PWM, and usually require grid-voltage sensors or more complex digital controllers, thereby increasing implementation complexity.
The DC-OCC scheme, originally developed for grid-connected converters, represents a substantial improvement over C-OCC. By introducing a second comparator with an inverted carrier, DC-OCC regulates both the peak and valley inductor currents within each switching period [
13]. This dual-point regulation inherently eliminates dc offset and light-load instability, produces symmetric current waveforms, and realizes unipolar PWM without grid-voltage sensing [
13,
14,
15].
When OCC-based strategies are applied to parallel APF systems, circulating currents remain a significant challenge that is not explicitly addressed by existing OCC variants. Current suppression methods can be categorized into three approaches. Hardware-based methods utilize isolation transformers, coupled inductors, or interphase reactors to block circulating-current paths [
16,
17], but at the expense of increased size, cost, and losses. Modulation-based methods rely on carrier interleaving and specialized PWM patterns, such as interleaved discontinuous PWM and modified interleaving techniques [
18,
19], which are effective for high-frequency circulating-current reduction but depend critically on precise carrier synchronization. Control-based approaches include virtual-impedance methods [
20,
21], observer-based estimation techniques [
22], and decentralized control strategies [
23]; while flexible, they often involve nontrivial controller design, sensitive dynamic interactions, and sometimes inter-module communication [
23].
While valuable, existing methods typically require additional components, precise synchronization, complex dynamics, or inter-module communication. These limitations motivate an integrated solution that leverages DC-OCC’s advantages while providing effective circulating-current suppression without additional complexity.
This paper makes the following contributions:
- (1)
DC-OCC is employed as the inner current controller of each shunt APF module. Compared with conventional and modified OCC schemes, the proposed system eliminates steady-state dc offset and light-load instability, inherently realizes unipolar PWM without grid-voltage sensing, and achieves symmetric, low-distortion compensation currents with high efficiency and near-unity power factor in a multi-module configuration.
- (2)
A unified circulating-current model is established that decomposes the ZSCC into low-, medium-, and high-frequency components as a function of carrier-phase deviation, providing new insight into circulating-current generation mechanisms in parallel APF systems.
- (3)
A ZSCC extraction and compensation scheme is proposed. By adapting the emulated resistance of each module based on the extracted ZSCC component, the method suppresses circulating currents without additional magnetic components, explicit virtual-impedance synthesis, or inter-module communication.
The paper is organized as follows:
Section 2 presents the principles of One-Cycle Control.
Section 3 discusses the formation and characteristics of circulating currents caused by carrier asynchronization.
Section 4 provides the simulation results that validate the proposed method.
Section 5 presents the experimental results. Finally,
Section 6 provides the conclusions.
2. One-Cycle Control
The corresponding controller structure for C-OCC are shown in
Figure 1. Under the standard assumptions outlined in [
24], the control law of the C-OCC can be expressed as:
where
,
is is the input current,
Rs is the current sensing gain,
Vdc is the DC bus voltage,
d is the duty ratio of switches S
3 and S
4, and
Re is the emulated resistance.
In C-OCC, the instantaneous error between the sensed input current and the carrier signal is integrated within each switching cycle. The comparator output then determines the switching instants of the power devices such that, over every switching period, the average inductor current equals the reference current scaled by the emulated resistance. As a result, the input current is shaped to follow the grid voltage, enabling near-sinusoidal current injection and almost unity power factor without explicit grid-voltage sensing. These features make the control structure compact.
Figure 2a illustrates the inductor current under C-OCC over one carrier cycle, where
imn0,
imx0, and
imn1 denote the current at the beginning, the peak, and the end of the cycle, respectively. Due to the asymmetric current trajectory, the waveform inherently exhibits a steady-state dc offset and, under light-load conditions, suffers from pronounced distortion near the zero-crossing region. These behaviors directly degrade the harmonic suppression capability of C-OCC. Despite its simplicity and fast transient response, C-OCC has two inherent drawbacks underlying the above behaviors. First, under light-load conditions, the falling slope of the inductor current can become steeper than that of the carrier waveform, so that the current no longer has a well-defined intersection with the carrier within a switching period. This loss of a proper intersection point leads to small-signal instability and severe current distortion near the zero-crossing region. Second, because C-OCC regulates only the peak current within each switching cycle, any asymmetry in the carrier waveform or in the integrator reset process produces a steady-state dc offset in the current waveform. This offset causes waveform asymmetry and additional low-frequency harmonics, thereby degrading the overall power quality.
To overcome these drawbacks, the DC-OCC scheme synthesizes a modified inductor-current waveform within each carrier cycle. The control objective is to ensure that the average inductor current equals the grid voltage scaled by the emulated resistance, i.e.,
iavg =
vs/
Re, while maintaining negligible ripple error. This is accomplished by introducing a second comparator, which detects the valley of the current in addition to its peak, thereby guaranteeing two intersection points between the sensed current and the carrier waveform within each switching cycle. The resulting current trajectories for the positive and negative half-cycles of the grid voltage are shown in
Figure 2b and
Figure 2c, respectively. When the switching frequency is much higher than the grid frequency and the dc-link voltage remains nearly constant within one switching period,
imn0 ≈
imn1, indicating that the average output current is essentially free of steady-state dc offset.
The synthesized current waveform required by DC-OCC is shown in
Figure 2b. During the positive half-cycle, the inductor current consists of two rising segments, with slopes
m1p and
m3p, and one falling segment, with slope
m2p. The admissible values of these slopes are determined by the converter switching states: the rising slopes correspond to
vs/
Ls or (
vs +
Vdc)/
Ls, whereas the falling slope corresponds to (
vs −
Vdc)/
Ls. For the negative half-cycle [
Figure 2c], the slopes
m1n,
m2n, and
m3n satisfy the same relationships with opposite polarity.
The switching states associated with each slope are summarized as follows:
- (1)
For a slope of vs/Ls, either switches 2 and 4 or 1 and 3 must be turned ON.
- (2)
For a slope of (vs + Vdc)/Ls, switches 3 and 4 must be turned ON.
- (3)
For a slope of (vs − Vdc)/Ls, switches 1 and 2 must be turned ON.
The switching sequence summarized in
Table 1 is selected to realize these slopes while minimizing the number of transitions within each carrier cycle, thereby improving efficiency and reducing switching losses. A key outcome of this optimized sequence is that the outer current segments (
m1p,
m3p,
m1n,
m3n) exhibit identical slopes in the positive and negative half-cycles of the grid voltage. This symmetry ensures a smooth transition of the current across the zero-crossing and helps to suppress low-frequency distortion as well as steady-state dc offset.
The same switching sequence can be implemented in two equivalent ways by processing either the current waveform or the carrier waveform together with their respective inverses, as illustrated in
Figure 3a,b. Both implementations generate identical PWM signals for the bridge switches. An additional advantage of the DC-OCC configuration is that it inherently realizes unipolar PWM, in contrast to the bipolar PWM in C-OCC. Under unipolar modulation, the bridge output voltage switches among +
Vdc, 0, and −
Vdc, which effectively doubles the apparent switching frequency of the current ripple and shifts the dominant ripple components to higher frequencies. As a result, the THD of the input current is reduced without the need for grid-voltage sensing.
The average current corresponding to the waveform in
Figure 2b is subsequently derived as:
Applying volt-second balance to the boost inductor,
Ls
where
Although the above derivation is presented for the positive half-cycle of the grid voltage, an analogous procedure for the negative half-cycle yields the same result as (10), confirming that the DC-OCC scheme produces identical average behavior in both polarities and eliminates any steady-state dc component in the fundamental input current.
The fundamental improvement of the DC-OCC scheme lies in its refined control objective. By synthesizing the current waveform shown in
Figure 2b, the controller shifts from the C-OCC approach—where only the peak current is regulated—to a dual-point regulation of both the peak and valley currents. This dual-comparison mechanism directly controls the cycle-averaged inductor current, ensuring that the relationship in (10) holds in every switching period. As a result, DC-OCC inherently eliminates the steady-state dc offset present in conventional OCC and achieves accurate resistive emulation with the desired emulated resistance Re over the entire load range.
Moreover, the inclusion of a second comparator guarantees two intersection points between the sensed current and the carrier (or its inverse) within each switching period. By comparing signals with opposing slopes, the system establishes stable and deterministic switching instants, which mitigates current distortion and improves dynamic response. The resulting symmetrical switching behavior not only enhances waveform linearity but also reduces the harmonic content of the input current.
A practical consideration in DC-OCC operation is the double-switching event that occurs at the boundary between consecutive carrier cycles, as illustrated in
Figure 3a,b. At this transition, the converter state toggles between “11” and “00,” both of which apply zero voltage across the bridge terminals. Consequently, this transition is functionally redundant and does not introduce additional switching loss or output distortion.
To realize this control sequence in hardware, a simple digital logic circuit is employed. The desired switching states for switches 1 and 3 during the
nth and (
n + 1)th carrier cycles are summarized in
Table 1. The logic implementation also utilizes an auxiliary input
Q, which is generated by a D flip-flop clocked at the switching frequency
fsw and driven by the same signal that resets the current integrator in
Figure 3. As a result, Q toggles at
fsw/2 with a 50% duty ratio. Using Karnaugh maps, the desired states of all switches are simplified to the Boolean expressions in (11) and (12).
4. Simulation Results
Simulations were carried out using MATLAB/Simulink (version R2023b), and the system parameters along with component ratings are summarized in
Table 2.
To validate the effectiveness of the proposed ZSCC suppression strategy, its performance is evaluated against three control schemes: (1) no carrier-phase control, (2) traditional carrier-phase control (without circulating-current component extraction), and (3) the improved carrier-phase control (with circulating-current component extraction). The comparative results, shown in
Figure 13,
Figure 14,
Figure 15,
Figure 16 and
Figure 17, demonstrate that the improved carrier-phase control, which integrates the novel circulating-current component extraction mechanism.
When the system experiences impedance mismatch and carrier asynchronization, the zero-sequence circulating current waveforms are shown in
Figure 13.
As observed in
Figure 14, the magnitude of the zero-sequence circulating current containing low- and medium-frequency components increases in the range of [0°, 90°] and decreases in the range of [90°, 180°]. In contrast, the circulating current containing only high-frequency components increases monotonically across the entire range of [0°, 180°]. These simulation results are consistent with the analytical trends predicted in
Section 3, where the low-frequency ZSCC component exhibits a non-monotonic dependence on
θ, whereas the high-frequency component increases monotonically with the carrier-phase shift. This agreement indirectly supports the attenuation characteristics summarized in (27).
The performance of a traditional carrier-phase control, which lacks the circulating current component extraction mechanism, was tested by activating it at
t = 0.1 s. The resulting waveforms in
Figure 16 demonstrate its limitations: the persistence of significant ZSCC amplitude indicates inadequate suppression capability, while the distorted phase-A current waveform reflects a failure to achieve proper carrier synchronization between the parallel modules.
In contrast, the proposed improved carrier-phase control strategy demonstrates remarkable performance enhancement when activated at
t = 0.1 s. The subsequent dynamic response, shown in
Figure 17, demonstrates significant performance improvement.
A quantitative analysis of the RMS values for different ZSCC components before and after control activation is provided in
Table 3. The ZSCC amplitude, categorized into low-frequency (150 Hz), medium-frequency (2850 Hz), and high-frequency (16.2 kHz) components, serves as the metric for evaluating suppression capability. Concurrently, the reduction in phase-A circulating current validates the effectiveness of carrier synchronization.
Figure 18 shows the grid current before the APF was activated, which is severely distorted due to the nonlinear load, resulting in a high THD value of 2.05%. After applying the proposed control strategy, the grid current becomes nearly sinusoidal, with a significantly reduced THD of 0.96%. These measurements are critical for validating the effectiveness of the proposed approach in mitigating harmonic distortion.
5. Experimental Results
The experimental platform used for this study is shown in
Figure 19. To validate the effectiveness of the proposed ZSCC suppression strategy, its performance was evaluated under three control strategies: (1) no carrier-phase control, (2) traditional carrier-phase control (without circulating-current component extraction), and (3) the improved carrier-phase control (with circulating-current component extraction). The experimental waveforms for circulating current and phase current under these three conditions are compared to assess the effectiveness of the proposed strategy.
During the actual operation of the parallel system, the carrier-phase difference between modules fluctuates within the range of 0–180° when no carrier synchronization control is applied, as shown in
Figure 20 and
Figure 21.
However, the experimental results for the low-frequency component of the zero-sequence circulating current do not fully align with the theoretical and simulation predictions, as clearly evidenced by comparing the idealized trends in
Figure 21 with the more irregular experimental data in the subsequent figure. This discrepancy arises because the theoretical model is predicated on the assumption that carrier asynchrony is the sole influencing factor. In practice, the low- and medium-frequency components of the ZSCC are also susceptible to other non-ideal conditions, such as variations in device parameters, grid voltage fluctuations, and electromagnetic interference. This observed deviation in the low-frequency component further validates the strategic decision in our control design to rely on the high-frequency component for feedback, as the latter demonstrates a more stable and predictable relationship with the carrier-phase difference
θ under real-world operating conditions.
The experimental waveforms without control are shown in
Figure 22, where the RMS value of the single-phase circulating current is 11.72 A, and the RMS value of the high-frequency ZSCC is 0.343 A.
The experimental waveforms under traditional carrier-phase control are shown in
Figure 23. The RMS value of the high-frequency ZSCC is 0.281 A, indicating partial suppression of the circulating current.
Under the improved control strategy, the experimental waveforms shown in
Figure 24 reveal significant improvements. The RMS value of the single-phase circulating current is reduced to 3.61 A, while the RMS value of the high-frequency ZSCC is further suppressed to 0.174 A.
The RMS values of the circulating currents at different frequencies under the three control strategies are listed in
Table 4.
As shown in
Table 4, compared with the no-control case, the improved control strategy with circulating-current component extraction demonstrates strong ZSCC suppression capability: the high-frequency component is reduced by 49.3%, the medium-frequency component by 49.3%, the low-frequency component by 19%, and the single-phase circulating current by 69.2%. Compared with the traditional control strategy, the improved control shows even better performance: the high-frequency component is reduced by 38.1%, the medium-frequency component by 45%, the low-frequency component by 37.8%, and the single-phase circulating current by 62%. Despite practical limitations such as interference and delays, the improved control can effectively constrain the carrier-phase difference between modules within 30°. These experimental results verify the correctness of the mathematical model and the effectiveness of the circulating current component extraction and suppression method.
The load transient waveforms under the proposed DC-OCC scheme are shown in
Figure 25. In
Figure 25a, the output power steps from 300 W to 1000 W. During this load increase, the dynamic response time is approximately 260 ms. The maximum voltage undershoot is 9.58 V (2.395% of the output voltage), and the maximum overshoot is 10.36 V (2.590% of the output voltage). In
Figure 25b, the load decreases from 1000 W to 300 W, with a corresponding response time of about 190 ms. The maximum overshoot and undershoot are 13.59 V (3.398%) and 5.90 V (1.475%), respectively. These results demonstrate that the proposed DC-OCC strategy provides fast and well-damped dynamic performance, maintaining a stable DC-link voltage with small overshoot and undershoot during rapid load transitions.
The grid current before and after compensation is now analyzed and compared.
Figure 26 shows the grid current before the APF was activated, which is severely distorted due to the nonlinear load, resulting in a high THD value of 2.25%. After applying the proposed control strategy, the grid current becomes nearly sinusoidal, with a significantly reduced THD of 1.1%. These measurements are critical for validating the effectiveness of the proposed approach in mitigating harmonic distortion.
Figure 27 and
Figure 28 compare the efficiency and power factor (PF) of the proposed DC-OCC scheme with those of conventional C-OCC under different load conditions. As shown in
Figure 25, the converter achieves a peak efficiency of 98.7% and maintains efficiency above 96% across the entire load range. In contrast, the conventional C-OCC demonstrates lower efficiency, particularly under light-load conditions (below 20% of the rated power). Similarly,
Figure 27 shows that the proposed control achieves a unity power factor (1.000) at rated power, while also significantly improving performance at light load (below 20% of the rated power).
At Po = 100 W (6.7% of the rated power), the DC-OCC achieves 10.8% higher efficiency and a 0.282 improvement in power factor compared with the conventional OCC method. These results confirm that the proposed control strategy effectively enhances both efficiency and power factor, particularly under light-load conditions, ensuring highly efficient, stable, and low-distortion operation across a wide load range.