Bit Synchronization-Assisted Frequency Correction in Low-SNR Wireless Systems

Abstract

In wireless communication systems, traditional frequency synchronization methods struggle to effectively track carrier frequency in low signal-to-noise ratio (SNR) environments, leading to degraded demodulation performance and severely impacting the stability and reliability of communication systems. To address this challenge, an innovative frequency synchronization framework is introduced, enhancing frequency synchronization accuracy and robustness in low-SNR environments through bit synchronization techniques. Specifically, the approach constructs a “bit synchronization-frequency synchronization” joint correction mechanism, where clock offset information extracted during the bit synchronization process is utilized to estimate frequency offset. This method enables an indirect measurement and compensation of carrier frequency offset, forming a hierarchical error compensation system. Furthermore, to overcome the limited convergence speed of the classical Gardner algorithm under significant phase offset conditions, an improved error feedback structure is proposed, accelerating bit synchronization convergence and reducing timing synchronization errors, thereby enhancing overall system performance. The effectiveness of the proposed method is validated through theoretical analysis and simulation experiments. Simulation results demonstrate that, compared to conventional frequency synchronization schemes, the proposed method achieves higher frequency correction accuracy in low-SNR scenarios, thereby improving the robustness and anti-interference capability of wireless communication systems in complex environments.

1. Introduction

In wireless communication systems, frequency synchronization is a critical process to ensure accurate signal demodulation and reliable data recovery. Particularly in low signal-to-noise ratio (SNR) environments, traditional frequency synchronization methods often suffer from insufficient precision, slow convergence, or even synchronization failure, severely affecting the stability of the communication link. Carrier frequency offset (CFO), a key factor that influences communication system performance, is typically caused by Doppler effects, hardware mismatches, or clock drift, leading to an increased bit error rate (BER) and degraded signal quality. Therefore, developing a frequency synchronization method suitable for low-SNR environments is of paramount importance.

Existing frequency synchronization methods can be broadly categorized into data-aided and non-data-aided algorithms. Data-aided synchronization algorithms, such as the Kay algorithm [1], L&W algorithm [2], and L&R algorithm [3], exhibit superior synchronization accuracy and acquisition speed under high-SNR conditions. However, these methods rely on pilot signals, which reduce transmission efficiency and make adaptation to complex channel environments challenging. In contrast, non-data-aided synchronization algorithms, such as frequency offset estimation using FFT [4,5], Costas loops [6,7], and decision-directed loops [8], do not require pilot signals and perform stably in high-SNR scenarios. However, in low-SNR environments, these methods are highly susceptible to noise interference, leading to increased frequency estimation errors and potential synchronization failures. To address these challenges, this paper proposes an improved bit synchronization-assisted frequency correction method that enhances synchronization accuracy and robustness in low-SNR conditions.

Furthermore, bit synchronization is a crucial technology in wireless communication systems [9,10,11,12] and faces its own set of challenges. For instance, frame synchronization algorithms relying on data-aided methods can introduce phase offsets under significant frequency deviations, exposing the limitations of error feedback mechanisms in bit synchronization, such as the Gardner algorithm. The slow feedback convergence of bit synchronization further restricts its direct application in frequency synchronization. Several optimization strategies have been proposed to address these issues, including improved interpolation filters [13], pre-filtering methods [14,15], and compensation techniques [16,17]. In [18], a hardware-based improved loop filter was designed to enhance transmission efficiency. However, these methods often suffer from high computational complexity or offer limited performance improvements. To fully exploit the potential of bit synchronization in frequency synchronization, this paper proposes a bit synchronization-assisted frequency correction method and introduces an enhanced Gardner algorithm to improve its convergence performance, ensuring synchronization accuracy and stability in low-SNR environments.

Specifically, this study extracts clock offset information between the transmitter and receiver during the bit synchronization process to indirectly estimate frequency offset. The estimated value is then used for frequency compensation before entering the conventional frequency synchronization stage, thereby alleviating the burden on Costas loops or phase-locked loops (PLLs). Additionally, to address the slow convergence of the Gardner algorithm under large frequency offsets, an improved algorithm is proposed, optimizing the error feedback mechanism to enhance convergence speed and stability.

The primary contributions of this paper are as follows. First, a bit synchronization-assisted frequency synchronization method is proposed, demonstrating superior noise resilience in low-SNR environments and significantly improving frequency synchronization accuracy. Second, the Gardner algorithm is enhanced to improve its convergence performance under large frequency offsets. Finally, a comprehensive theoretical analysis and algorithmic framework is established, thoroughly investigating the robustness and convergence properties of the proposed method.

This research not only presents a novel solution for frequency synchronization in low-SNR environments but also provides theoretical support and practical engineering value for the efficient synchronization design of future wireless communication systems. The remainder of this paper is structured as follows. Section 2 reviews the system model for bit synchronization, Section 3 and Section 4 describe the proposed frequency synchronization method and the improvements to the Gardner algorithm, respectively. Section 5 evaluates the proposed method through simulations and experimental results. Section 6 presents further discussion. Finally, conclusions are drawn in Section 7.

2. System Modeling

2.1. Timing Synchronization Feedback Model

Whether using a phase-locked loop (PLL)-based frequency synchronization method or a data-aided (DA) approach that employs training sequences for frequency estimation, the performance of these methods deteriorates significantly as the signal-to-noise ratio (SNR) decreases. In low-SNR environments, frequency estimation based on training sequences is highly susceptible to noise interference, leading to substantial estimation bias. Meanwhile, PLL-based frequency synchronization methods may suffer from false locking or an inability to track carrier frequency offset. Furthermore, under the same SNR and loop noise bandwidth conditions, timing synchronization loops generally exhibit stronger noise resistance than frequency synchronization loops and can effectively correct bit synchronization deviations.

On the other hand, in wireless communication systems, carrier frequency offset is influenced not only by channel conditions and Doppler effects but also by the inherent oscillator inaccuracies of the transmitter and receiver devices [19]. Based on this observation, this paper extends the existing timing synchronization module to extract timing offset information and further compute the frequency offset, thereby achieving more accurate frequency synchronization. This method effectively improves frequency synchronization accuracy in low-SNR environments and improves system robustness.

After downconversion, the received BPSK/QPSK signal is first passed through a matched filter and then sampled according to the local sampling frequency $f_s=1/T_s$. The sampled signal is then fed into the timing recovery loop. The output signal of the matched filter can be expressed as follows:

$$y\left(t\right)=\sum _{n}y\left(nT\right)h(t-nT-{\tau }_n)+n\left(t\right)$$

(1)

where $y\left(nT\right)$ represents the received symbol sequence, $h\left(t\right)$ is the impulse response of the matched filter, and $n\left(t\right)$ denotes additive noise. T is the symbol period, and n is the index of the transmitted symbols. ${\tau }_n$ represents the timing offset caused by the mismatch between the receiver and transmitter sampling periods. By sampling the matched filter output signal $y\left(t\right)$ at intervals of $m{T}_s$ (where m = 0, 1, 2, …), the second sampling value at $t=m{T}_s$ can be expressed as

$$y\left(t\right)=\sum _{m}y\left(m{T}_s\right)h(t-m{T}_s-{\tau }_s)+n\left(m{T}_s\right)$$

(2)

where $T_s$ is the clock period of the receiver’s fixed sampling rate, T is the symbol period, and ${\tau }_s$ represents the timing delay caused by the discrepancy between the receiver’s local sampling clock period and the transmitter’s sampling period.

To compensate for synchronization deviations caused by timing delays, time synchronization is required for signals sampled at the local sampling clock frequency $f_s$. This process is achieved through a time synchronization module.

The time synchronization module is a closed-loop system comprising an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator (NCO). Specifically, the interpolation filter employs a polyphase decomposition interpolation algorithm based on the Farrow structure. It generates interpolation coefficients through polynomial fitting and performs fractional interval resampling on the input signal.

In the timing synchronization and bit synchronization module, the interpolation filter is used to perform fractional interval resampling on the signal $y\left(k{T}_s\right)$, thereby recovering the signal values at the optimal sampling instants.

To generate the desired optimal interpolated signal, $y\left(t\right)$ can be represented as a resampled signal at intervals of $k{T}_i$ (where k = 0, 1, 2, …). The interpolation at the kth instance, occurring at $t=k{T}_i$, can be expressed as

$$y\left(k{T}_i\right)=\sum _{m}y\left(m{T}_s\right)h(k{T}_i-m{T}_s)+n\left(k{T}_i\right)$$

(3)

After passing through the interpolation filter, the interpolation timing $t_k$ of the kth symbol can be expressed as $t_k=k{T}_s-{\tau }_s$, where ${\tau }_s$ represents the timing offset estimation of the kth symbol.

The timing error detector employs the Gardner algorithm. The classical Gardner algorithm calculates the timing error signal based on the error characteristics of adjacent I/Q symbol samples, with the error function expressed as

$$\begin{array}{cc}\hfill e\left(k\right)& =e^I\left(k\right)+e^Q\left(k\right)\hfill \\ \hfill & =y_I(k-1/2)[y_I\left(k\right)-y_I(k-1)]\hfill \\ \hfill & +y_Q(k-1/2)[y_Q\left(k\right)-y_Q(k-1)]\hfill \end{array}$$

(4)

where $y_I\left(k\right)$ and $y_Q\left(k\right)$ denote the resampled in-phase (I) and quadrature (Q) components of the k-th symbol, respectively. The terms $e^I\left(k\right)$ and $e^Q\left(k\right)$ represent the timing errors in the I and Q branches. $y_I\left(k\right)$ and $y_I(k-1)$ correspond to the optimal sampling points of the I branch, while $y_I(k-1/2)$ represents the intermediate sample between two optimal sampling points. The value of $y_I(k-1/2)$ is proportional to the timing error in the I branch, while $y_I\left(k\right)-y_I(k-1)$ determines the timing error adjustment direction. The same principles apply to the Q branch.

The loop filter is responsible for smoothing $e\left(k\right)$ and filtering out noise, which determines the loop stability and the time required to establish synchronization. In this work, an ideal integrating loop filter is utilized to effectively track the phase and frequency offset between the local clock and the transmitted symbol clock. The output of the loop filter controls the numerically controlled oscillator (NCO) through the control word $w\left(m\right)$, which can be expressed as

$$\begin{array}{cc}\hfill f_p& =C1\ast e\left(k\right)\hfill \end{array}$$

(5)

$$\begin{array}{cc}\hfill w(m+1)& =w\left(m\right)+C2\ast e\left(k\right)+f_p\hfill \end{array}$$

(6)

In the bit synchronization module, the NCO is responsible for generating clock overflow events, which determine the interpolation reference point $m_k$ and simultaneously compute the fractional interval $u_k$ for interpolation.

$$\eta (m+1)=\left[\eta \right(m)-w(m\left)\right]mod1$$

(7)

where $\eta \left(m\right)$ represents the content of the NCO register at the m-th clock cycle, and $w\left(m\right)$ is the NCO control word, both of which are positive fractional values. Since the NCO operates at a cycle of $T_s$, while the interpolator operates at a cycle of $T_i$, the loop filter adjusts $w\left(m\right)$ to ensure that the NCO overflows precisely at the optimal sampling instants. When the loop reaches equilibrium, $w\left(m\right)$ approximately stabilizes to a constant value. At this point, the NCO register overflows once every $1/w\left(m\right)$ cycles of $T_s$, on average. Therefore, the interpolation period is given by

$$T_i=T_s/w\left(m\right)$$

(8)

which leads to

$$w\left(m\right)=T_s/T_i$$

(9)

The variation of the NCO register content over time is illustrated in the following figure.

In Figure 1, $m_k{T}_s$ represents the sampling clock pulse point, which precedes the k-th interpolation instant $k{T}_i$, This interpolation instant corresponds to the zero-crossing point of the curve, marking the overflow moment of the numerically controlled oscillator (NCO). The recursive relationship governing interpolation control can be derived by expressing two consecutive interpolation instants as follows:

$$\begin{array}{cc}\hfill k{T}_i& =(m_k+u_k)T_s\hfill \end{array}$$

(10)

$$\begin{array}{cc}\hfill (k+1)T_i& =(m_{k+1}+u_{k+1})T_s\hfill \end{array}$$

(11)

where $m_k$ and $m_{k+1}$ are integers. Subtracting these two equations yields the recursive formula

$$m_{k+1}=m_k+T_i/T_s+u_k-u_{k+1}$$

(12)

From Figure 1, by applying the principle of similar triangles, the following relationship is obtained:

$${\displaystyle \frac{u_k}{\eta \left(m_k\right)}}={\displaystyle \frac{\left(1-u_k\right)T_s}{1-\eta (m_k+1)}}$$

(13)

Thus, the fractional interval can be expressed as

$$u_k={\displaystyle \frac{\eta \left(m_k\right)}{w\left(m_k\right)}}$$

(14)

Once the interpolation basepoint $m_k$ and the fractional interval $u_k$ are determined, the bit synchronization feedback system utilizes these values to compute the correct interpolation point. The corresponding clock timing error is then calculated based on the interpolation point. This error is processed by the loop filter to update the step size $w\left(m\right)$, which is subsequently fed into the controller to compute $m_k$ and $u_k$. The entire system continuously adjusts through feedback to determine the optimal interpolation point, thereby outputting the best sampling data.The feedback system is illustrated in Figure 2.

2.2. Common Source Characteristics of Sampling and Carrier Clocks

In wireless communication systems, the sampling clock $f_s^{tx\_clk}$ and carrier clock $f_c^{tx\_clk}$ are derived from a common reference clock $f_{ref}$ through phase-locked loop (PLL) frequency multiplication, ensuring signal synchronization and coherence. Their mathematical relationship is expressed as

$$\left\{\begin{array}{c}{f}_s^{tx\_clk}=N_s\ast f_{ref}\hfill \\ f_c^{tx\_clk}=N_c\ast f_{ref}\hfill \end{array}\right.$$

(15)

where $N_s$ and $N_c$ represent the frequency multiplication factors for the sampling and carrier clocks, respectively. Ideally, both $f_s^{tx\_clk}$ and $f_c^{tx\_clk}$ are determined solely by $f_{ref}$ and their respective multiplication factors. However, in practical systems, non-ideal PLL characteristics introduce frequency deviations, primarily due to the following factors.

2.2.1. Reference Clock Drift

Due to temperature variations, component aging, and other environmental factors, the actual reference clock frequency deviates by $\Delta f_{ref}$, leading to shifts in the multiplied clock frequencies:

$$\left\{\begin{array}{c}{f}_s^{tx\_cl{k}^{\prime }}=N_s\ast (f_{ref}+\Delta f_{ref})=f_s^{tx\_clk}+N_s\ast \Delta f_{ref}\hfill \\ f_c^{tx\_cl{k}^{\prime }}=N_c\ast (f_{ref}+\Delta f_{ref})=f_c^{tx\_clk}+N_c\ast \Delta f_{ref}\hfill \end{array}\right.$$

(16)

When $N_s\ne N_c$, the minor deviation $\Delta f_{ref}$ is amplified by the multiplication factors, resulting in an accumulated frequency error between the sampling and carrier clocks, which adversely affects synchronization performance.

2.2.2. Relative Offset Between Sampling and Carrier Clocks

In practical implementations, the PLLs at the transmitter and receiver may have different loop parameters, such as loop bandwidth $B_L$ and gain K, leading to inconsistencies in their output clock signals. If the transmitter and receiver PLLs introduce additional frequency $\Delta f_{PLL}$, the estimated carrier frequency offset $\Delta f_c$ and sampling clock offset $\Delta f_{clk}$ at the receiver can be expressed as

$$\begin{array}{cc}\hfill \Delta f_{clk}& =f_s^{tx\_cl{k}^{\prime }}-f_s^{tx\_clk}=N_s\ast \Delta f_{ref}+\Delta f_{PLL}\hfill \end{array}$$

(17)

$$\begin{array}{cc}\hfill \Delta f_c& =f_c^{tx\_cl{k}^{\prime }}-f_c^{tx\_clk}=N_c\ast \Delta f_{ref}+\Delta f_{PLL}\hfill \end{array}$$

(18)

Since both clocks originate from the same reference frequency, their offsets are related by

$$\Delta f_c={\displaystyle \frac{N_c}{N_s}}\ast \Delta f_{clk}$$

(19)

Thus, when the PLL multiplication factors differ ($N_s\ne N_c$), the sampling clock frequency deviation is proportionally mapped to the carrier frequency deviation by a factor of ${\displaystyle \frac{N_c}{N_s}}$, affecting subsequent carrier synchronization and demodulation accuracy.

In summary, the sampling and carrier clocks are both derived from the reference clock $f_{ref}$ via PLL frequency multiplication, with their deviations primarily influenced by reference clock drift, PLL errors, and noise accumulation effects. When the multiplication factors differ, minor reference clock deviations are magnified, leading to increased frequency errors at the receiver, necessitating compensation via synchronization modules.

3. Carrier Frequency Offset Estimation

To track the frequency offset caused by clock drift, the receiver utilizes a Gardner-based timing recovery loop to estimate symbol timing offset. The key system parameters are defined as follows:

• $\mathit{sample}$: Receiver upsampling factor;
• $N_c$: Ratio of carrier frequency to sampling clock frequency ($N_c=f_c^{\mathrm{tx}\_\mathrm{clk}}/f_s^{\mathrm{tx}\_\mathrm{clk}}$);
• $N_s$: Ratio of symbol rate to sampling rate ($N_s=f_s^{\mathrm{tx}\_\mathrm{clk}}/R_s$ where $R_s$ is symbol rate).

As the accumulated timing error over multiple frames reflects the underlying clock offset between the transmitter and receiver, the linear trend (slope) of this timing drift is extracted. This estimated drift slope is then mapped to a coarse frequency offset, which is used for pre-compensation prior to fine carrier synchronization using a phase-locked loop (PLL). A loop filter is employed to smooth the clock offset estimation, ensuring robustness to noise while maintaining sensitivity to time-varying drift.

During the bit synchronization process, the optimal sampling point data is obtained, along with key interpolation parameters. The interpolation parameters are defined as

• $m_k$: Interpolation basepoint index (integer part of timing offset);
• $u_k$: Fractional interval ($0\le u_k<1$);
• $k{T}_i$: Ideal symbol-spaced sampling instant where k is the symbol index.

In the clock synchronization process based on the Gardner algorithm, the timing error detector (TED) requires two samples per symbol. Therefore, during the bit synchronization stage, the original signal $y\left(m{T}_s\right)$ is downsampled using a stride index $m_e$ = (0, 2, 4, …) that selects every second sample, corresponding to sampling instants:

$$t=m_e{T}_s$$

(20)

In practical scenarios, sampling clock offsets exist between the transmitter and receiver, causing the receiver’s sampling instants to gradually drift away from the optimal sampling points. To quantify this deviation, the accumulated clock error $\Delta T_{accu}\left(k\right)$ between receiver samples and ideal symbol instants is defined as

$$\begin{array}{cc}\hfill \Delta T_{accu}\left(k\right)& =m_e{T}_s-k{T}_i\hfill \end{array}$$

(21)

$$\begin{array}{cc}\hfill k{T}_i& =(m_k+u_k)T_s\hfill \end{array}$$

(22)

where $m_e{T}_s$ represents the sampling instant of the received signal when two samples per symbol are taken based on the receiver’s clock, while $k{T}_i$ denotes the interpolation instant generated by the bit synchronization module. The accumulated clock error $\Delta T_{accu}\left(k\right)$ captures the cumulative effect of clock drift between the transmitter and receiver.

To analyze the temporal evolution of this accumulated error, two reference indices ($N1$ and $N2$, where $N2>N1$) and a time window $N_{window}$. At these two reference indices, the mean accumulated clock error is computed as follows:

$$\begin{array}{cc}\hfill \Delta T_{lock}& =mean(\Delta T_{accu}(N2:N2+N_{window}))\hfill \\ \hfill & -mean(\Delta T_{accu}(N1:N1+N_{window}))\hfill \end{array}$$

(23)

where $mean(•)$ represents the averaging operation over multiple measurements to mitigate noise and enhance estimation accuracy. The actual time interval between the two reference indices is given by

$$\Delta t_{lock}=(N2-N1)\ast T_s$$

(24)

From the accumulated clock error difference $\Delta T_{lock}$ and the actual time interval $t_{lock}$, the clock drift rate can be estimated as

$$R_{drift}=\Delta T_{lock}/\Delta t_{lock}$$

(25)

This parameter quantifies the rate of clock offset between the transmitter and receiver. Given the receiver’s upsampling factor $sample$ and the sampling clock period $T_s$, the clock frequency offset between the transmitter and receiver can be calculated as

$$\Delta f_{clk}=R_{drift}/(T_s\ast sample)$$

(26)

where $\Delta f_{clk}$ denotes the relative clock frequency offset between the transmitter and receiver.

In wireless communication systems, the carrier frequency $f_c^{tx\_clk}$ is derived from the transmitter’s clock $f_s^{tx\_clk}$. Thus, clock frequency offset induces a corresponding carrier frequency offset:

$$\Delta f_c=f_c^{tx\_clk}\ast {\displaystyle \frac{\Delta f_{clk}}{f_s^{tx\_clk}}}\approx {\displaystyle \frac{N_c}{N_s}}\ast \Delta f_{clk}$$

(27)

where $\Delta f_c$ represents the carrier frequency offset caused specifically by the clock frequency offset. This equation highlights that even small discrepancies in the transmitter and receiver clocks can be significantly amplified at high carrier frequencies, thereby increasing carrier frequency error.

To ensure robust carrier synchronization, the lock state of the phase-locked loop (PLL) is evaluated based on the relative motion between the transmitter and receiver. Let $\Delta f_{\mathrm{PLL}\_c}$ denote the PLL’s estimated frequency offset after convergence. In typical terrestrial mobile communication scenarios, Doppler-induced frequency shifts generally range from 0 Hz to approximately 1000 Hz. If the absolute difference between these two values, $|\Delta f_{\mathrm{PLL}\_c}-\Delta f_c|$, exceeds 1000 Hz, the system declares a carrier synchronization failure, as this deviation is unlikely to result from normal Doppler variation and more likely indicates tracking loss or acquisition error.

Upon detecting carrier synchronization failure, a secondary frequency compensation process is performed to achieve frequency alignment. The compensation strategy involves the following:

• Coarse Frequency Correction—The optimal sampled data undergoes frequency offset compensation using a digital down-conversion approach to obtain a coarsely corrected signal;
• Fine Frequency Correction via PLL—The coarse frequency-compensated signal is further refined using a PLL, which tracks and adjusts the residual frequency error;
• Phase Ambiguity Resolution—The fine frequency-compensated signal is further processed to resolve phase ambiguity, thereby completing the frequency synchronization process.

This approach ensures accurate carrier synchronization, mitigating the impact of clock-induced frequency errors in wireless communication systems.The flowchart of the proposed frequency synchronization method is shown in Figure 3, and the detailed framework is illustrated in Figure 4.

4. Modified Timing Synchronization Loop

In the classical Gardner algorithm (denoted as the GA algorithm), if the adjacent sampled symbols $y\left(k\right)$ and $y(k-1)$ exhibit the same polarity, the intermediate sampling value $y(k-{\displaystyle \frac{1}{2}})$ may deviate from zero, even when the timing error has been corrected. This deviation introduces system self-noise, adversely affecting the accuracy of timing error estimation and thereby degrading synchronization performance.

To enhance clock error detection and timing recovery, countermeasures must be implemented when adjacent symbol polarities are identical to mitigate the impact of system self-noise.

Compared to the GA algorithm, an improved method proposed in [17], referred to as the mGA1 algorithm, inverts $e^I\left(k\right)$ and $e^Q\left(k\right)$ when adjacent symbol polarities in the I or Q channels are identical. However, its bit error rate (BER) performance in a high-bandwidth wireless communication link model remains comparable to that of the GA algorithm.

Building on this, an extended non-data-aided detector, denoted as the mGA2 algorithm, was introduced in [20]. This method demonstrates superior timing jitter performance over the mGA1 detector under ideal phase recovery conditions. Nevertheless, when carrier frequency offset is present, the mGA2 algorithm can introduce greater timing noise errors, increasing the risk of bit synchronization failure.

Additionally, an enhanced Gardner algorithm with self-noise suppression capabilities, referred to as the mGA3 algorithm, was proposed in [21]. This method significantly outperforms other improved Gardner algorithms in terms of timing noise error reduction. However, its synchronization speed is relatively slow.

Addressing these challenges, this study integrates the strengths of various improved Gardner algorithms and proposes an optimized detection method based on phase compensation and complex signal joint decision-making. This approach aims to reduce timing jitter, accelerate synchronization convergence, and minimize timing noise errors.

4.1. Self-Noise Suppression in Error Detection

Based on the mGA3 algorithm, self-noise in the error detection mechanism is reduced. The error function is expressed as

$$e^{mGA3}\left(k\right)=e_I^{mGA3}\left(k\right)+e_Q^{mGA3}\left(k\right)$$

(28)

Expanding this yields

$$\begin{array}{cc}\hfill & e^{mGA3}\left(k\right)=\left\{y_I\left(k-{\displaystyle \frac{1}{2}}\right)-{\displaystyle \frac{h(-\frac{T}{2})}{h\left(0\right)}}\left[y_I\left(k\right)+y_I(k-1)\right]\right\}\hfill \\ \hfill & \times \left[y_I\left(k\right)-y_I(k-1)\right]\hfill \\ \hfill & +\left\{y_Q\left(k-{\displaystyle \frac{1}{2}}\right)-{\displaystyle \frac{h(-\frac{T}{2})}{h\left(0\right)}}\left[y_Q\left(k\right)+y_Q(k-1)\right]\right\}\hfill \\ \hfill & \times \left[y_Q\left(k\right)-y_Q(k-1)\right]\hfill \end{array}$$

(29)

The term ${\displaystyle \frac{h\left(-\frac{T}{2}\right)}{h\left(0\right)}}={\displaystyle \frac{2cos(\alpha \pi /2)}{\pi (1-{\alpha }^2)}}$, where $\alpha$ represents the roll-off factor of the pulse shaping filter $h\left(t\right)$.

4.2. Optimization of the Error Function

Building upon the error function, a new optimized error function is defined as

$$e^{x1}\left(k\right)=e_I^{{\left(mGA3\right)}^{\prime }}\left(k\right)+e_Q^{{\left(mGA3\right)}^{\prime }}\left(k\right)$$

(30)

$$\begin{array}{cc}\hfill & e_I^{{\left(mGA3\right)}^{\prime }}\left(k\right)=\left\{\begin{array}{cc}-e_I^{\mathrm{x}}\left(k\right),\hfill & \mathrm{if}\mathrm{sign}\left(y_I\left(k\right)\right)\ne \mathrm{sign}\left(y_I(k-1)\right)\hfill \\ e^{\mathrm{x}}\left(k\right),\hfill & \mathrm{else}\hfill \end{array}\right.\hfill \\ \hfill & e_Q^{{\left(mGA3\right)}^{\prime }}\left(k\right)=\left\{\begin{array}{cc}-e_Q^{\mathrm{x}}\left(k\right),\hfill & \mathrm{if}\mathrm{sign}\left(y_Q\left(k\right)\right)\ne \mathrm{sign}\left(y_Q(k-1)\right)\hfill \\ e_Q^{\mathrm{x}}\left(k\right),\hfill & \mathrm{else}\hfill \end{array}\right.\hfill \end{array}$$

(31)

where $sign(•)$ extracts the sign of the signal.

Further considering the phase difference between adjacent symbols $\Delta \phi$, when $\Delta \phi \in [-\pi /4,\pi /4)$, a new error term is defined as

$$\begin{array}{cc}\hfill e^{x2}\left(k\right)& =-\alpha Re\left(\right|e^{jarg\left(y\right(k\left)\right)}-e^{jarg\left(y\right(k-1\left)\right)}|\hfill \\ \hfill & \ast conj\left(y\left(k-{\displaystyle \frac{1}{2}}\right)\right))\hfill \end{array}$$

(32)

where $\alpha$ is the roll-off factor, $Re(•)$ denotes the real part, and $conj(•)$ represents complex conjugation.

4.3. Final Expression of the mGA4 Algorithm

The final error detection mechanism of the mGA4 algorithm is formulated as

$$e^x\left(k\right)=\left\{\begin{array}{cc}{e}^{x_1\left(k\right)},\hfill & \mathrm{if}\Delta \phi \notin \left[-{\displaystyle \frac{\pi }{4}},{\displaystyle \frac{\pi }{4}}\right)\hfill \\ e^{x_2\left(k\right)},\hfill & \mathrm{if}\Delta \phi \in \left[-{\displaystyle \frac{\pi }{4}},{\displaystyle \frac{\pi }{4}}\right)\hfill \end{array}\right.$$

(33)

This method integrates the convergence speed of the mGA2 algorithm with the self-noise suppression capability of the mGA3 algorithm. By incorporating phase compensation and complex signal joint decision-making, the approach effectively enhances timing jitter performance, accelerates synchronization convergence, and reduces timing noise errors. As a result, it significantly improves synchronization performance in wireless communication systems.The flowchart of the proposed mGA4 algorithm is illustrated in Figure 5.

5. Simulation Results

To evaluate the proposed algorithm, a wireless communication link model was established for simulation analysis. The transmitted signal frame structure consists of a preamble, pilot symbols, and data symbols. The preamble, comprising 139 symbols, is constructed using a Zadoff–Chu (ZC) sequence to achieve frame synchronization. The pilot segment, consisting of 460 symbols, is modulated using binary phase-shift keying (BPSK) and serves to resolve phase ambiguities introduced by the carrier synchronization phase-locked loop. The data section spans 100,000 symbols and is modulated using quadrature phase-shift keying (QPSK). The baseband signal at the transmitter has a symbol rate of 30.72 MHz, with an upsampling factor of 8, resulting in a sampling clock frequency of 245.76 MHz. A root-raised cosine (RRC) filter is employed for pulse shaping, with a roll-off factor of $\alpha =0.5$. The system incorporates a clock frequency offset of 20 ppm. Considering the trade-off between computational complexity and interpolation accuracy, a cubic Lagrange interpolation filter is adopted for signal resampling.The overall baseband frame structure used in the simulation is illustrated in Figure 6.

5.1. Carrier Phase Noise and Jitter Modeling

To evaluate the robustness of the proposed synchronization algorithm under practical hardware impairments, we introduce phase jitter modeled from realistic local oscillator (LO) phase noise spectra. The phase noise is generated in the frequency domain according to a specified single-sideband (SSB) phase noise mask in dBc/Hz and converted into time-domain phase fluctuations through inverse Fourier transformation. The resulting complex-valued jitter signal is applied as a multiplicative term to the transmitted carrier as follows:

$$s_{\mathrm{jitter}}\left[n\right]=e^{j\varphi \left[n\right]},$$

(34)

where $\varphi \left[n\right]$ denotes the random phase sequence determined by the oscillator’s phase noise power spectral density.

The phase noise profiles used for jitter modeling were derived from a combination of ADIsimPLL simulations and empirical measurements of representative oscillator hardware, ensuring that the simulated jitter scenarios realistically capture practical operating conditions.

Two distinct jitter scenarios are simulated:

• Jitter1: Represents a typical high-performance oscillator (e.g., HMC830 PLL with 875 MHz output), with phase noise values:

  $$L\left(f\right)=\{0,-115,-115,-110,-120,-147,-162,-165,-165\}\mathrm{dBc}/\mathrm{Hz},$$

  (35)

  at frequency offsets $f=\{0,{10}^2,{10}^3,{10}^4,{10}^5,{10}^6,{10}^7,{10}^8,f_s/2\}$ Hz;
• Jitter2: Models a degraded oscillator, increasing the phase noise at all frequency offsets by approximately 10 dB compared to Jitter1, thus representing a more severe jitter condition.

The root-mean-square (RMS) phase jitter in radians is calculated by integrating the phase noise power spectrum:

$${\sigma }_{\varphi }=\sqrt{2\sum _{i=2}^k\Delta f_i·{10}^{L\left(f_i\right)/10}},$$

(36)

where $L\left(f_i\right)$ is the phase noise power at offset $f_i$, and $\Delta f_i$ denotes the bin width in the discrete frequency domain.

The resulting RMS jitter values and normalized phase jitter percentage (relative to $2\pi$) are summarized in

Table 1. Phase jitter parameters for simulation.

Scenario	RMS Phase Jitter (rad)	Jitter Percentage
Jitter1	∼0.0225	∼0.36%
Jitter2	∼0.0450	∼0.72%

.

5.2. Verification of Carrier Synchronization Performance

As shown in Figure 7a, the accumulated clock offset $\Delta T_{accu}\left(k\right)$ results from sampling clock deviations between the transmitter and receiver. This offset is measured after applying the bit synchronization feedback algorithm combined with a Farrow-structure interpolation filter. The interpolation filter, controlled by the timing error feedback, iteratively compensates for timing deviations, enabling rapid convergence and thus ensuring precise sampling alignment, which is critical for bit synchronization.

Statistical Analysis

All error metrics were computed from $N=100$ independent Monte Carlo trials. The 95% confidence intervals (CIs) were calculated using Student’s t-distribution with a significance level of $\alpha =0.05$. Significant performance differences between methods were inferred from non-overlapping CIs.

Figure 7b illustrates the impact of timing loop stability on frequency offset estimation accuracy under various SNR and jitter conditions. When $E_b/N_0$ falls below approximately −2 dB, the timing synchronization loop continues to converge; however, the accuracy of the timing estimates degrades due to increased noise, leading to bias and instability in the frequency offset estimation. In this regime, both the Costas-based and the proposed timing-aided methods exhibit estimation errors exceeding the 0.2% threshold. Nevertheless, the proposed method maintains significantly lower error rates and more stable performance compared to the Costas loop, which suffers from sharp degradation and pronounced sensitivity to jitter. These results indicate that the proposed approach remains more robust and reliable under extremely low-SNR conditions, demonstrating strong resilience to both noise and timing jitter.

Table 2. Frequency offset estimation errors (Mean ± 95% CI) of the Costas loop and the proposed method under various E_b/N₀ and jitter conditions (in %).

Eb/N0 (dB)	Conventional Costas Loop			Proposed Method
	No Jitter	Jitter1	Jitter2	No Jitter	Jitter1	Jitter2
−6	39.25 ± 0.12	39.35 ± 0.15	39.01 ± 0.18	4.77 ± 0.03	4.71 ± 0.04	4.81 ± 0.05
−5	49.61 ± 0.21	49.19 ± 0.19	49.17 ± 0.22	5.41 ± 0.07	5.28 ± 0.06	5.50 ± 0.08
−4	5.73 ± 0.09	5.94 ± 0.11	6.46 ± 0.13	0.72 ± 0.02	0.67 ± 0.02	0.75 ± 0.03
−3	3.52 ± 0.07	3.42 ± 0.06	3.61 ± 0.08	0.49 ± 0.01	0.49 ± 0.01	0.51 ± 0.01
−2	1.60 ± 0.05	1.55 ± 0.06	1.81 ± 0.07	0.23 ± 0.01	0.24 ± 0.01	0.24 ± 0.01
−1	1.49 ± 0.04	1.36 ± 0.05	1.31 ± 0.05	0.13 ± 0.01	0.13 ± 0.01	0.14 ± 0.01
0	0.33 ± 0.03	0.32 ± 0.03	0.28 ± 0.03	0.10 ± 0.005	0.10 ± 0.005	0.10 ± 0.005
1	0.21 ± 0.02	0.21 ± 0.02	0.20 ± 0.02	0.10 ± 0.004	0.10 ± 0.004	0.10 ± 0.004
2	0.12 ± 0.02	0.12 ± 0.02	0.13 ± 0.02	0.06 ± 0.003	0.06 ± 0.003	0.06 ± 0.003
3	0.11 ± 0.02	0.11 ± 0.02	0.11 ± 0.02	0.07 ± 0.003	0.07 ± 0.003	0.07 ± 0.003
4	0.10 ± 0.01	0.10 ± 0.01	0.10 ± 0.01	0.05 ± 0.002	0.05 ± 0.002	0.05 ± 0.002
5	0.08 ± 0.01	0.08 ± 0.01	0.08 ± 0.01	0.06 ± 0.002	0.06 ± 0.002	0.06 ± 0.002
6	0.09 ± 0.01	0.09 ± 0.01	0.09 ± 0.01	0.04 ± 0.002	0.04 ± 0.002	0.04 ± 0.002
7	0.07 ± 0.01	0.07 ± 0.01	0.07 ± 0.01	0.04 ± 0.001	0.04 ± 0.001	0.04 ± 0.001
8	0.06 ± 0.01	0.06 ± 0.01	0.06 ± 0.01	0.04 ± 0.001	0.04 ± 0.001	0.04 ± 0.001
9	0.07 ± 0.01	0.07 ± 0.01	0.07 ± 0.01	0.03 ± 0.001	0.03 ± 0.001	0.03 ± 0.001
10	0.06 ± 0.01	0.06 ± 0.01	0.06 ± 0.01	0.03 ± 0.001	0.03 ± 0.001	0.03 ± 0.001
11	0.05 ± 0.01	0.06 ± 0.01	0.06 ± 0.01	0.03 ± 0.001	0.03 ± 0.001	0.03 ± 0.001

provides a comparative analysis of frequency offset estimation errors under various $E_b/N_0$ conditions for the conventional Costas loop and the proposed algorithm. To emulate practical wireless impairments, multiplicative jitter is introduced in the carrier signal generated by the transmitter’s PLL, with two distinct jitter scenarios (Jitter1 and Jitter2) evaluated to assess algorithm robustness and stability.

Results demonstrate that the proposed algorithm consistently outperforms the Costas loop, particularly in low-SNR regimes, achieving significantly lower estimation errors. Furthermore, both methods maintain stable estimation performance across the jitter conditions, indicating that phase jitter exerts only a minor influence on their accuracy.

Overall, these findings confirm the superior accuracy and robustness of the proposed approach under challenging SNR conditions. While jitter has a limited impact on both algorithms, the proposed method delivers clear performance advantages, making it well-suited for deployment in complex wireless communication systems requiring high-precision frequency synchronization.

5.3. Validation of the Improved Timing Recovery Algorithm Performance

Under specific simulation settings, the convergence behavior of the fractional interval $u_k$ and timing error $e\left(k\right)$ was analyzed to evaluate synchronization performance. Each algorithm was assessed over 100 independent runs, and

Table 3. Comparison of timing error standard deviations (Mean ± Std) across 100 trials.

${\mathit{e}}^{\mathbf{GA}}\left(\mathit{k}\right)$	${\mathit{e}}^{\mathbf{mGA}2}\left(\mathit{k}\right)$	${\mathit{e}}^{\mathbf{mGA}3}\left(\mathit{k}\right)$	${\mathit{e}}^{\mathbf{mGA}4}\left(\mathit{k}\right)$
$0.0918\pm 0.0015$	$0.0916\pm 0.0014$	$0.0687\pm 0.0012$	$0.0700\pm 0.0013$

reports the standard deviation of the TED outputs.

At $E_b/N_0=12$ dB, the proposed method ($e^{mGA4}\left(k\right)$) achieved a standard deviation of $0.0700\pm 0.0013$, notably lower than that of the conventional Gardner algorithm ($0.0918\pm 0.0015$). For comparison, $e^{mGA2}\left(k\right)$ and $e^{mGA3}\left(k\right)$ yielded $0.0916\pm 0.0014$ and $0.0687\pm 0.0012$, respectively.

Figure 8 further illustrates the influence of roll-off factor, interpolation filter order, and symbol rate on frequency offset estimation (subfigures a−c), and compares TED performance (subfigure d). All results are averaged over 100 trials, with error bars denoting standard deviations and 95% confidence intervals.

Figure 9 illustrates two key performance aspects of the proposed timing recovery algorithm. Subfigure (a) shows the evolution of the NCO output $u_k$, where the mGA4 algorithm achieves significantly faster convergence compared to baseline methods, requiring fewer symbols to reach synchronization. This accelerated convergence shortens the acquisition period and improves overall timing stability. Subfigure (b) further validates the practical impact by comparing the received signal amplitude after bit synchronization correction under conditions of frame synchronization offsets and insufficient pilot symbols due to large frequency deviations. While GA, mGA2, and mGA3 exhibit initial bit errors—even under high SNR—mGA4 rapidly converges and maintains a zero bit error rate, demonstrating superior robustness and synchronization reliability under challenging conditions.

5.4. Evaluation of System Reliability and Efficiency

To ensure a fair and accurate performance evaluation of the communication system, the bit error rate (BER) and packet error rate (PER) were calculated exclusively over the data symbol segment, explicitly excluding both the preamble and pilot sections. Since the pilot symbols are used for synchronization and phase ambiguity resolution rather than conveying actual payload data, including them in BER/PER statistics would bias the results and overestimate system performance. Specifically, the BER (high SNR, initial 10 k) metric reflects the error rate over the first 10,000 data symbols, while BER (high SNR, full 500 k) represents the error rate over the entire 500,000-symbol data section.

To provide a more comprehensive system-level evaluation beyond synchronization performance, we further analyzed three key metrics: bit error rate (BER), packet error rate (PER), and data throughput. These system-level metrics provide insight into the actual reliability and efficiency of the communication link under each timing recovery scheme, beyond the synchronization layer.

As summarized in

Table 4. Performance comparison of genetic algorithms in communication systems (BER/PER exclude preamble and pilot symbols).

Algorithm	Timing Convergence Symbols	BER (Initial 10 k)	BER (Full 500 k)	PER (%)	Throughput (Mbps)
GA	198	$7\times {10}^{-4}$	$2\times {10}^{-4}$	2	60.21
mGA2	135	$2\times {10}^{-5}$	<${10}^{-6}$	1	60.85
mGA3	193	$7\times {10}^{-4}$	$2\times {10}^{-4}$	2	60.21
mGA4 (proposed)	102	<${10}^{-6}$	<${10}^{-6}$	0.6	61.44

Note: QPSK modulation with a symbol rate of 30.72 Msps.

, the proposed mGA4 algorithm achieves the lowest BER and PER values across both short-term and long-term transmissions. Specifically, mGA4 attains a BER below ${10}^{-6}$ over 500k payload bits and a PER of only 0.6%, outperforming all baseline algorithms. Furthermore, due to its faster convergence (within 102 symbols), mGA4 enables earlier data recovery and achieves the highest effective throughput of 61.44 Mbps. These results demonstrate that improving synchronization accuracy not only stabilizes symbol timing but also significantly enhances overall system robustness and spectral efficiency.

In addition, the “Timing Convergence Symbols” metric quantifies the number of symbols required for the timing recovery loop to reach steady-state convergence after frame detection. A smaller value indicates faster synchronization and reduced vulnerability during the symbol acquisition phase. For instance, the proposed mGA4 algorithm achieves convergence within 102 symbols, significantly improving the timing recovery responsiveness and enhancing the overall robustness of the communication system.

To further validate system robustness under practical conditions, the BER performance was quantitatively evaluated across various SNR levels and synchronization scenarios. As illustrated in Figure 10, the proposed mGA4 algorithm consistently outperforms GA, mGA2, and mGA3 in terms of BER, particularly in the presence of frame synchronization offsets and limited pilot symbols. These improvements are attributed to faster timing convergence, which effectively reduces the vulnerability window during the initial phase of symbol recovery.

5.5. Bit Error Rate Optimization

By integrating the proposed optimization algorithm, the system achieves a bit error rate (BER) that closely aligns with the optimal theoretical error curve, even under low signal-to-noise ratio (SNR) conditions. Compared to the non-optimized system, the BER performance improves by approximately 2 to 3 orders of magnitude, as illustrated in Figure 11a.

To further evaluate the effectiveness of the proposed mGA4 algorithm in realistic mobile communication scenarios, additional simulations incorporated multipath fading and Doppler effects, which are representative impairments in outdoor wireless environments involving user mobility, such as urban or suburban mobile terminals.

The multipath fading channel was modeled with four distinct propagation paths, having relative delays of [0, 110, 190, 410] ns and corresponding power levels of [0, −9.7, −19.2, −22.8] dB, simulating signal reflections from nearby buildings and terrain. To emulate user movement at moderate speeds (e.g., 30–60 km/h), Doppler shifts were applied to the multipath components, resulting in time-varying frequency offsets at the receiver. This setup realistically reflects the dynamic channel behavior experienced in typical mobile wireless environments, such as vehicular communications or handheld devices in motion.

The results, presented in Figure 11b, demonstrate that the mGA4 algorithm maintains reliable performance under these challenging conditions. Despite inter-symbol interference (ISI) and time-selective fading, the proposed method achieves stable timing error convergence and yields a significantly lower BER compared to the classical Gardner algorithm. These findings confirm the robustness and suitability of mGA4 for mobile communication systems operating in dynamic, multipath-rich environments.

5.6. Computational Complexity Analysis

To evaluate the implementation feasibility of the proposed modified Gardner algorithm with polarity-based gating (mGA4) and two-layer drift correction, we analyze the computational complexity per received symbol and per frame.

The mGA4 algorithm extends the classical Gardner detector by introducing a gating mechanism based on polarity checks. This includes the computation of sign functions and XOR logic to suppress ineffective timing updates. The operations per symbol are constant and summarized as follows:

• 4 sign evaluations (2 for in-phase and 2 for quadrature components);
• 2 XOR logical operations;
• 1 conditional timing error update.

A phase-based decision strategy is employed to improve timing accuracy. For each of the M candidate interpolated symbols (typically $M=4$), the phase difference is computed and an error energy metric is evaluated. This involves the following:

• 2 subtractions (real and imaginary);
• 2 multiplications (for squaring);
• 1 addition (error accumulation);
• 1 comparison (minimum error selection).

The interpolation module uses cubic Lagrange interpolation with fixed coefficients, leading to the following:

• 6 multiplications;
• 6 additions.

These values are per interpolated point, regardless of the actual signal values.

The second-layer drift correction is performed via a linear regression over a sliding window of fixed length N (e.g., $N=32$). The complexity includes the following:

• N multiplications;
• $2N$ additions;
• 1 division.

All operations in the algorithm are fixed and do not grow with the length of the input sequence. The summary of operation counts and complexity is shown in

Table 5. Operation count and complexity of mGA4 algorithm.

Module	Operation Type	Count	Complexity
Polarity-Based Gating	Sign, XOR, gating	4 sign + 2 XOR	$\mathcal{O}\left(1\right)$
Phase-Based Decision	Sub, Mul, Add, Min	8 mult + 8 add + 4 cmp	$\mathcal{O}\left(1\right)$
Lagrange Interpolation	Mult, Add	6 mult + 6 add	$\mathcal{O}\left(1\right)$
Drift Estimation (per frame)	Mult, Add, Div	N mult + $2N$ add + 1 div	$\mathcal{O}\left(1\right)$

.

As all modules perform a fixed number of operations per symbol or per frame, and no recursive or variable-size operations are involved, we conclude that the proposed enhancements introduce a small, constant overhead, making them feasible for real-time implementation on DSP and FPGA platforms, as are common in wireless receivers. Sign comparisons, conditional logic, phase computations, and slope estimations are well-suited for efficient digital logic mapping. Moreover, the fixed number of operations in cubic interpolation can be pipelined using MAC units on modern FPGA or SoC devices.

Given the consistent $O\left(1\right)$ complexity per symbol and frame, real-time processing at high sampling rates is achievable. Therefore, the proposed scheme is both computationally efficient and practical for deployment in SDR-based receivers such as those using ADRV9009 or USRP platforms.

To bridge the gap between simulation and deployment, preliminary hardware resource estimations have also been conducted, suggesting that the proposed synchronization logic can fit within mid-scale FPGAs. Furthermore, future work will proceed in two phases: (1) HDL-level prototyping and timing simulation, and (2) over-the-air testing on ADRV9009/USRP SDR platforms under realistic low-SNR and fading conditions.

6. Discussion

While the Costas loop is adopted as the baseline for performance evaluation in this study, we acknowledge the existence of more advanced frequency synchronization methods, including the Moose estimator, Schmidl & Cox (S&C) algorithm, Kim’s frequency offset estimator, Kalman filter-based approaches, and maximum likelihood (ML)-based synchronization techniques.

Among these, the Moose, S&C, Kim, and ML-based estimators typically rely on long, known training sequences and often require extensive correlation or search operations. This reliance can significantly increase computational complexity and bandwidth overhead, limiting their practicality in continuous transmission scenarios or resource-constrained environments such as IoT or deep-space systems.

In contrast, the proposed bit synchronization-assisted frequency correction method does not require any additional training sequences, as it derives frequency offset information directly from the clock offset obtained during the timing recovery process. This makes our method lightweight and well-suited for low-SNR and real-time systems.

Moreover, our method is not mutually exclusive with model-based approaches such as Kalman filtering. On the contrary, it can serve as a coarse initial estimator that provides a reliable frequency offset estimate, which can be recursively refined by Kalman-based filters. This layered combination is expected to improve convergence speed and robustness, particularly in dynamically varying channels. This will be investigated in our future work.

The classical Gardner timing recovery algorithm, although originally designed for QPSK modulation, has been demonstrated to be extendable to higher-order modulation formats like 16QAM and 64QAM. Our improved Gardner algorithm similarly maintains this extensibility, enabling accurate timing offset estimation for a range of modulation schemes.

In addition to the timing synchronization, the proposed two-layer synchronization framework employs clock offset information derived from the improved Gardner algorithm to estimate frequency offset. This frequency offset estimation mechanism is inherently modulation-agnostic and thus can also be extended to higher-order modulation formats.

Nonetheless, higher-order constellations feature closer symbol spacing, making them more vulnerable to residual synchronization errors, particularly timing inaccuracies. Such vulnerabilities can cause performance degradation, especially under low-SNR conditions or multipath fading channels.

To overcome these challenges, future work will focus on further optimizing both the improved Gardner timing recovery and the frequency offset estimation mechanism. Potential enhancements include decision-directed synchronization schemes, adaptive loop filters, and error-correction-assisted synchronization strategies, aiming to maintain robust synchronization performance across a broad range of modulation formats.

7. Conclusions

This work proposes a bit synchronization-assisted frequency correction method tailored for low-SNR wireless communication scenarios. By estimating the frequency offset through clock drift information and applying coarse correction before PLL tracking, the approach enhances frequency synchronization accuracy while maintaining low complexity. Experimental results demonstrate reduced convergence time and improved BER performance compared to the traditional Costas loop.

The proposed scheme is well-suited for real-time deployment in software-defined radios and embedded platforms due to its constant per-symbol complexity and hardware-friendly operations. Future efforts will focus on extending this method to more complex modulation schemes and benchmarking against state-of-the-art synchronization algorithms to validate its broader applicability and performance advantages.