Effects of Fe Contamination on the Reliability of Gate Oxide Integrity in Advanced CMOS Technology

Abstract

Fe contamination has always been one of the most critical issues in the integrated circuit (IC) industry due to its catastrophic effect on device reliability and electrical characteristics. With complementary metal oxide semiconductor (CMOS) technology scaling down, this issue has been attracting more attention. In this paper, the impact of Fe impurity on the reliability of gate oxide integrity (GOI) in advanced CMOS technology is investigated. Intentional contamination of polysilicon gates was conducted in both boron- and phosphorus-doped devices. Failure analysis of the gate oxide was conducted with high-resolution transmission electron microscopy (HRTEM) and the energy dispersive X-ray (EDX) technique. The experimental results disclose that the properties of PMOS are much more sensitive to Fe contamination than those of NMOS. It is suggested that the reason for the above phenomena is that Fe precipitates at the PMOS gate/oxide interface but dissolves uniformly in the NMOS poly gate due to lower formation energy of the FeB pair (0.65 eV) in PMOS than that of the P4-Fe cluster (3.2 eV) in NMOS.

1. Introduction

Fe is one of the most common elements, and it is extremely difficult to eliminate completely from the integrated circuit (IC) industry. Unintentional contamination sources include silicon substrate, various chemical reagents, processing equipment, material delivery systems, etc. [1,2,3]. As a deep-level impurity, Fe can significantly reduce the minority carrier lifetime and concentration [4,5], whereas Fe acts as an effective minority carrier generation site [2] in the depletion regions of metal oxide semiconductor (MOS) devices. Its incorporation in gate oxides or precipitation at Si/SiO₂ interfaces has catastrophic effects [1,6] on gate oxide integrity (GOI) and MOS yields. Henley [7] et al. disclosed that a reduction in oxide thickness from 200 Å to 100 Å requires a reduction in the Fe contamination limit by 100 times. When the complementary metal oxide semiconductor (CMOS) process reaches 45 nm and beyond, a high-κ replacement metal gate (RMG) is widely used to further improve the device performance. However, dummy poly-Si gate deposition is still an important process in the technology. The precipitation of Fe at the dummy poly-Si gate/high-κ interface or the dummy poly-Si gate/active area (AA) interface may deteriorate channel and high-κ film dielectric reliability. It is of great significance to investigate the influence of Fe contamination on the reliability of GOI and device performance in advanced CMOS technology. Although there have been some papers [7,8,9,10] about the relationship between Fe impurity and GOI, the study of the effect of Fe contamination on the ultrathin oxide layer in PMOS/NMOS and the sensitivity of GOI performance in advanced CMOS technology has not been carried out in the previous literature.

In this work, we selected planar MOSFETs with a gate oxide thickness of 34 Å as the test vehicle and investigated the different effects of intentional Fe contamination on GOI performance between NMOS and PMOS. The related failure mechanism has also been discussed.

2. Experimental Methods

To clarify the effects of Fe impurity on ultrathin gate oxide, we selected planar MOSFETs with a gate oxide layer thickness of 34 Å as the test platform, which was measured using spectroscope ellipsometry. Figure 1a shows the schematic cross-section of the device structures with a local magnified image near the gate oxide. In this experiment, the MOSFETs with intentional Fe contamination from the polysilicon gate were prepared using the standard CMOS technology. The flow of the sample preparation process is shown in Figure 1b. Gate oxide with a thickness of 34 Å was grown in a furnace at 870 °C in a dry oxygen environment. Subsequently, the polysilicon gate was deposited by low-pressure chemical vapor deposition. The gate with a thickness of 1800 Å was then patterned by dry etching. Afterward, a specific wafer was intentionally contaminated with Fe by immersion in a “tainted” [7] SC1 (H₂O₂/NH₄OH/H₂O = 2:1:50 in volume) solution for 20 min and then spun dry at 25 °C. The “tainted” solution was prepared by dissolving predetermined amounts of FeCl₃ to a level of 0.01 ppm in weight. The polysilicon gate was then doped along with lightly doped drain (LDD) and source/drain implantation; the dopant elements were boron and phosphorus for the PMOS and NMOS, respectively. Rapid thermal annealing (RTA) at 1025 °C for 30 s was then used to activate the implants to achieve a homogeneous distribution. After the formation of CoSi₂ salicide and tungsten contact via, a standard Cu dual-damascene process was adopted to define metallic interconnections. The reference wafer underwent the same process conditions as the contaminated one except for Fe contamination. The thicknesses of the gate oxide and polysilicon gate were characterized by spectroscope ellipsometry, a fast, contactless, and nondestructive technique that is widely used for the in-line monitoring of film thickness in the microelectronics industry. The MOS capacitor test structures (oxide area = 100 × 60 μm²) for the below investigations are located at the scribe line. The distance between the NMOS and PMOS test structures was only about 380 μm.

To evaluate the influence of Fe contamination on MOS capacitor properties, the breakdown voltage (V_bd) of the device was measured by the voltage ramp (V-Ramp) method, which was performed by an Agilent 4072 parametric test system with a voltage ramp rate of 5 MV/cm/sec at 25 °C. The maximum voltage was set to be 12.9 V. The breakdown voltage was determined in the accumulation mode when the gate leakage current exceeded 1 μA, which means that a significant deviation from Fowler–Nordheim tunneling has occurred. Here, 71 devices per wafer were selected for analysis for every doping type. To determine the failure position precisely, a laser hot spot was scanned around the test structure area with a method reported by K. Nikawa et al. [11]. The leakage limit was set to 40 nA to avoid damage on the gate oxide. The cross-section of the gate/oxide/substrate interface at the failure position was made by using a focused ion beam (FIB). The samples were then thinned, and the cross-section was analyzed by high-resolution transmission electron microscopy. The elements of related precipitate were determined by the energy dispersive X-ray analysis technique.

3. Results and Discussion

Figure 2 shows the current vs. voltage (I_G-V_G) curves of the contaminated and reference samples for both the PMOS and NMOS. Different colors represent different test samples; 71 devices per wafer were selected for analysis for every doping type. It can be seen that the I_G-V_G curves of the contaminated PMOS show a bi-model nature in Figure 2a. The leakage rates of eight of the early fail samples start to rise sharply at a relatively low voltage (around 0.5 V), which indicates the presence of a leakage path across the gate oxide induced by the contaminated Fe during the wafer process. However, the rest of the samples of the contaminated PMOS exhibit I_G-V_G curves comparable with those of the reference samples in Figure 2b. This phenomenon can be explained by the limited defect detection ability of the relatively small V-Ramp test key area (6000 μm² per wafer shot). In contrast, it can be seen that the Fe contamination in the above manner had a negligible effect on the I_G-V_G curves of the contaminated NMOS according to Figure 2c,d. As is well known, F-N conduction dominates the leakage conduction mode for gate oxide thickness from 7 nm to 3 nm. Therefore, the I_G-V_G curves of both PMOS and NMOS in this study can be expressed by the following F-N equation:

$$J_{F-N}=A{E}_{OX}^{2}exp\left[-\frac{B}{E_{OX}}\right]$$

(1)

where E_ox is the electric field across the oxide, and A and B are constants related to the Si/SiO₂ electron effective mass and the barrier height, respectively.

The different effects of Fe contamination on PMOS and NMOS gate oxide reliability became even more apparent when the breakdown voltage was analyzed. Figure 3 illustrates the V-Ramp data on the cumulative failure rates of normal distribution versus the breakdown voltage. The breakdown voltage was derived from the I_G-V_G curves with the criteria of the gate leakage current exceeding 1 μA. All 71 V_bd data points measured from every experimental split were ranked from the smallest to the largest value. A normal distribution plot was then made with the cumulative failure rates on the Y axis and V_bd on the X axis. The unbiased estimation of the cumulative failure rate was calculated by the following formula:

$$Cunulative Failure Rate=\frac{Cumulative Number of Failures-0.3}{Sample Size+0.4}$$

(2)

The V_bd specification (4.14 V) was set to be 2.3 times the operation voltage (1.8 V) for both the NMOS and PMOS. This is a crucial parameter for CMOS gate oxide reliability, as chips constructed from gate oxide with a breakdown voltage lower than this value may exhibit early product failure or extrinsic reliability failure during the product’s lifetime. The V_bd distribution data show that the uncontaminated PMOS and NMOS from the reference wafer presented a clean distribution with a V_bd of 5.16 V. It is clear that the contaminated NMOS exhibited a comparable performance (V_bd = 5.15 V) with that of the uncontaminated one. In contrast, although the majority of the contaminated PMOS show a V_bd of 5.13 V, the obvious early failure (failure ratio: 8/71) with a V_bd lower than 1.5 V is likely the deleterious effect of Fe contamination. Therefore, the V-Ramp data show that the PMOS was much more sensitive to Fe contamination than the NMOS.

To investigate the root cause of PMOS failure, failure analysis was conducted on contaminated PMOS (V_bd failure samples), with contaminated NMOS as a reference. The laser hot spot images of PMOS presented in Figure 4a show that there were several bright spots on the test structure with a random distribution. The failure point at the upper left corner marked by a dashed circle was then analyzed. The TEM image (Figure 4b) shows obvious gate oxide burnout at the failure point, which was a result of high leakage across the gate oxide during the V-ramp test.

Figure 5a displays the EDX mapping image of the gate/oxide/substrate cross-section of contaminated PMOS. It should be noted that a pyramidal-shaped precipitate with a diameter up to 66 nm was formed at the gate/oxide interface. According to the previous literature [6,12,13,14], the Fe-related precipitates in MOS devices usually appear at the Si/SiO₂ interface and can be classified into two types based on their shape. Wong-Leung [12] and Luca [13] have identified the rod-like precipitate as α-FeSi₂ and the pyramidal precipitate as β-FeSi₂ using the electron diffraction method. It is quite clear that the precipitate in Figure 5a shows a similar shape and size [12,13,14] to that of β-FeSi₂. In addition, the elemental analysis results verify the presence of Fe elements, and no obvious oxygen signal was detected on the precipitate. Therefore, it can be inferred that the precipitate on the contaminated PMOS was β-FeSi₂. However, neither an Fe precipitate nor Fe signal was detected near the gate oxide burnout area on the contaminated NMOS, as illustrated in Figure 5b. It can be concluded that the failure analysis on the contaminated NMOS revealed an intrinsic gate oxide breakdown failure mode, and Fe contamination exhibited negligible effects on the NMOS gate oxide reliability. Therefore, the failure analysis results are consistent with those of the V-Ramp test.

To the best of our knowledge, reports about the relationship between device doping type and GOI performance after Fe contamination are unavailable, whereas the diffusion and precipitation mechanism of Fe impurity in polysilicon solar cells has been widely investigated in the past few decades. Based on these investigations [1,4,15], the interesting phenomenon of Fe contamination exhibiting different effects on the GOI performance of PMOS and NMOS could be clarified.

The different behaviors of Fe impurity in PMOS and NMOS are illustrated in Figure 6. In the boron-doped polysilicon gate of PMOS, Fe can form unstable FeB pairs (formation energy = 0.65 eV) with B acceptors by electrostatic attraction. FeB pairs can be easily dissociated by annealing at a temperature above 200 °C, or by shining bright white light on the wafer [16,17]. Meanwhile, for NMOS, Fe in phosphorus-doped Si can be stably bound in the form of P₄-Fe clusters with a formation energy of 3.2 eV [18], which is difficult to separate even at a high temperature. Therefore, phosphorus-doped layers are a common method to getter Fe efficiently into polysilicon solar cells [19,20]. It is well known that the Si/SiO₂ interface acts as a sink for Fe impurity [1,21,22]. Therefore, a larger amount of Fe in PMOS than in NMOS could diffuse and segregate to the gate/oxide interface during the high-temperature process stages. Fe impurity around the interface in PMOS would be oversaturated [2,16] when cooled down, and it would react with Si and form thermally stable β-FeSi₂ with the help of oxygen precipitates [1,23,24]. If β-FeSi₂ precipitate grows to a certain extent, it reduces the oxide thickness and enhances the local electric field, which results in a poor GOI performance of PMOS [7].

4. Conclusions

In conclusion, NMOS and PMOS were intentionally contaminated with Fe from a polysilicon gate. The GOI V-Ramp test results show that Fe contamination resulted in the early failure of PMOS due to β-FeSi₂ precipitates at the gate/oxide interface. However, Fe contamination only had a negligible effect on the V-Ramp performance of NMOS, and no obvious Fe signal was detected around its gate/oxide interface. The reason for the above phenomena is likely that the thermal stability of the FeB pairs (formation energy = 0.65 eV) in PMOS is less than that of the P₄-Fe clusters (formation energy = 3.2 eV) in NMOS. Therefore, it can be concluded that PMOS is much more sensitive to Fe contamination than NMOS.