# A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface

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## Abstract

**:**

## 1. Introduction

_{SW1}and M

_{SW2}are connected in series, and the substrate can be prevented from being turned on when the switch is turned off. In practice, M

_{SW1}is used for the current limit protection while M

_{SW2}is employed to protect against the reverse current. The voltage stabilization loop used to control M

_{SW2}is similar to the LDO structure, but the difference from the traditional LDO is that the dropout voltage of the loop needs to be reduced (<100 mV) to avoid the power loss of the switch itself [2,3,4,5,6,7,8,9,10,11]. Under such a low dropout voltage, the working state of the M

_{SW2}transistor is approximately in the linear region. It should be noted that according to the protocol requirements of USB3.X, the current flowing through the switch varies from 0 A to several amperes corresponding to the change of the load on the output terminal of the switch, which poses difficulties for the compensation of the loop stability [1].

## 2. Traditional Regulation Circuit with Pole–Zero Tracking Compensation

_{RZ}and C

_{C}circuits. The current sensor mirrors and tracks the output current and realizes 1/K current scaling by adjusting the mirror ratio of M

_{SWB}and M

_{SW2}. The drain voltages of M

_{SWB}and M

_{SW2}are equal through the function of OP1, achieving accurate copying of the current, which is subsequently output through the current mirror composed of M

_{N3}and M

_{N4}. The current of M

_{P5}is the output of M

_{P2}and M

_{P3}current mirrors. As a result, the V

_{GS}voltage of M

_{P5}is proportional to the output current. In addition, M

_{RZ}and C

_{C}form a zero, and the gate–source voltages of M

_{RZ}and M

_{P5}are the same, which makes the on-resistance of M

_{RZ}proportional to the output current. When the output current decreases, the output pole (P

_{o}) and the V

_{GS}voltage of M

_{P5}decrease. With a larger impedance of M

_{RZ}, the frequency of the zero formed by M

_{RZ}and C

_{C}is lowered, realizing the tracking compensation of the output pole. The compensated voltage stabilizing loop has only one dominant pole at the output of EA1, which makes the entire loop stable.

_{OUT}and EA1 in the traditional circuit with varying load current. In addition, the P

_{o}at the V

_{OUT}terminal will change with the varying load current. For example, with a small output current, R

_{L}>> R

_{MSW2}(meanwhile, R

_{MSW1}<< R

_{MSW2}), and the output impedance at the V

_{OUT}terminal is:

_{GS}voltage of M

_{P5}is calculated as:

_{GS}values of M

_{RZ}and M

_{P5}are the same, and M

_{RZ}is operating in the linear region, the on-resistance of M

_{RZ}is:

_{RZ}and C

_{C}can be expressed as:

_{MP5}and L

_{MP5}are the channel width and length of the M

_{P5}transistor. The frequency compensation can be achieved by using Z

_{C}to cancel out P

_{o}. However, due to the different dependence of P

_{o}(Equation (2)) and Z

_{C}(Equation (5)) on R

_{L}, Z

_{C}cannot track the change of P

_{o}well when R

_{L}varies in a large range. This can further result in a large change in bandwidth as well as a deterioration in stability.

## 3. Proposed Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation

_{1}~P

_{3}, P

_{o}) and a zero (Z

_{C}) in the circuit illustrated in Figure 3.

_{SW1}and M

_{SW2}are represented and labeled by M

_{SW}for a better description). The linear pole–zero tracking voltage generator is composed of OP2, M

_{N5}and R

_{B}. The voltage potential at points A and B are clamped to be equal though OP2, which makes the V

_{DS}voltage of M

_{N5}equal to the voltage across R

_{B}, V

_{DSN5}= V

_{RB}. M

_{N5}can be modulated to work in the linear region through V

_{RB}making V

_{DSN5}= V

_{RB}= V

_{drop}. The output of OP2 also functions as the gate voltage of both M

_{RZ}and M

_{N5}.

_{N5}is in the linear region, and the drain–source current of M

_{N5}is:

_{N5}and the output current due to the current mirror:

_{GS}of M

_{N5}transistor is:

_{GS}values of M

_{RZ}and M

_{N5}are the same, and both work in the linear region, the on-resistance of M

_{RZ}can be obtained by:

_{o}and Z

_{C}are in a first-order linear relationship to R

_{L}, as indicated by Equations (9) and (16), respectively, realizing the linear tracking and compensation of Z

_{C}with a different loading current.

## 4. Simulation and Experimental Test Results

_{1}as the dominant pole and P

_{o}as the first nondominant pole. P

_{2}and P

_{3}are far away from P

_{1}due to the small equivalent input capacitance and equivalent output impedance, and do not affect the stability of the loop. Then, we can plot the location of the poles of the proposed regulation circuit as shown in Figure 6. From Equations (9) and (16), it can be seen that both Z

_{C}and P

_{o}have a first-order linear proportional relationship with I

_{O}. When the load changes, Z

_{C}can be used to track and compensate for the change of P

_{o}linearly. Thus, we can obtain a high-stability loop in a wide current range.

^{2}.

_{O}shows undershoot and overshoot voltages of −187.6 mV and 175.4 mV, respectively. The 0.5% settling times are 175 μs and 177 μs, respectively. The test result indicates an enhanced working stability of the entire loop.

_{o}(max). From the comparison result, it is found that within the full load range, the bandwidth change of the regulation circuit proposed in this paper is the smallest, the stability of the system is better and a smaller drop voltage can be achieved.

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- He, F. USB Port and power delivery: An overview of USB port interoperability. In Proceedings of the 2015 IEEE Symposium on Product Compliance Engineering (ISPCE), Chicago, IL, USA, 18–20 May 2015; pp. 1–5. [Google Scholar]
- Kwok, K.C.; Mok, P.K.T. Pole-zero tracking frequency compensation for low dropout regulator. In Proceedings of the I 002 IEEE International Symposium on Circuits and Systems (ISCAS), Phoenix-Scottsdale, AZ, USA, 26–29 May 2002; pp. 735–738. [Google Scholar]
- Rajput, S.K.; Hemant, B.K. Two-stage high gain low power OpAmp with current buffer compensation. In Proceedings of the 2013 IEEE Global High Tech Congress on Electronics, Shenzhen, China, 17–19 November 2013; pp. 121–124. [Google Scholar]
- Ho, M. A CMOS Low-Dropout Regulator with Dominant-Pole Substitution. IEEE Trans. Power Electron.
**2016**, 31, 6362–6371. [Google Scholar] [CrossRef] - Duan, Q.; Li, W.; Huang, S.; Ding, Y.; Meng, Z.; Shi, K. A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load. Electronics
**2019**, 8, 1143. [Google Scholar] [CrossRef] [Green Version] - Jiang, Y.; Wang, L.; Wang, Y.; Wang, S.; Guo, M. A High-Loop-Gain Low-Dropout Regulator with Adaptive Positive Feedback Compensation Handling 1-A Load Current. Electronics
**2022**, 11, 949. [Google Scholar] [CrossRef] - Duong, Q.H.; Nguyen, H.H.; Kong, J.W.; Shin, H.S.; Ko, Y.S.; Yu, H.Y.; Lee, Y.H.; Bea, C.H.; Park, H.J. Multiple-loop design technique for high-performance low dropout regulator. In Proceedings of the 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, 7–9 November 2016; pp. 217–220. [Google Scholar]
- Sobhan Bhuiyan, M.A.; Hossain, M.R.; Minhad, K.N.; Haque, F.; Hemel, M.S.K.; Md Dawi, O.; Ibne Reaz, M.B.; Ooi, K.J. CMOS Low-Dropout Voltage Regulator Design Trends: An Overview. Electronics
**2022**, 11, 193. [Google Scholar] [CrossRef] - Nozahi, M.; Amer, A.; Torres, J.; Entesari, K.; Sanchez-Sinencio, E. High PSR Low Drop-Out Regulator with Feed-Forward Ripple Cancellation Technique. IEEE J. Solid-State Circuits
**2010**, 45, 565–577. [Google Scholar] [CrossRef] - Huang, C.; Ma, Y.; Liao, W. Design of a Low-Voltage Low-Dropout Regulator. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
**2014**, 22, 1308–1313. [Google Scholar] [CrossRef] - Cao, H.; Yang, X.; Li, W.; Ding, Y.; Qu, W. An Impedance Adapting Compensation Scheme for High Current NMOS LDO Design. IEEE Trans. Circuits Syst. II Express Briefs
**2021**, 68, 2287–2291. [Google Scholar] [CrossRef]

**Figure 3.**Proposed structure of regulation circuit with the adaptive linear pole−zero tracking compensation. (R

_{Z}is the equivalent impedance of the NMOS M

_{RZ}; I

_{Bias}and I

_{Bias1}are bias currents. V

_{PUMP}is the high−level supply voltage in the USB interface protecting circuit.)

**Figure 5.**The detailed structure of the linear adaptive pole–zero compensation voltage regulation circuit.

**Figure 9.**Measurement output voltage V

_{O}and output current I

_{O}waveforms under load transitions between 0.2 A and 1 A.

Ref. [6] | Ref. [9] | Ref. [10] | Ref. [11] | This Work | |
---|---|---|---|---|---|

Technology (nm) | 180 | 130 | 90 | 180 | 180 |

Power MOS | PMOS | PMOS | PMOS | PMOS | PMOS |

Output cap. (μF) | 4.7 | 4 | 1 | 17 | 10 |

Supply voltage (V) | 1.6~5.5 | >1.15 | 1 | 1.5~3.3 | 4.5~5.5 |

Quiescent current (μA) | 424 | 50 | 46 | 790 | 100 |

Output current (A) | 1 | 0.025 | 0.1 | 6 | 2 |

Dropout voltage (mV) | 200 | >150 | 150 | 110 | 75 |

GBW range | - | - | - | 26.5~1.48 MHz | 45~135 kHz |

PM range | 35~95° | - | - | 14.9–61° | 61~80° |

Area (mm × mm) | 1.4 | 0.049 | 0.0041 | 6.3 | 0.24 |

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**MDPI and ACS Style**

Tang, H.; Wang, Y.; Zhang, D.W.
A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface. *Electronics* **2022**, *11*, 2121.
https://doi.org/10.3390/electronics11142121

**AMA Style**

Tang H, Wang Y, Zhang DW.
A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface. *Electronics*. 2022; 11(14):2121.
https://doi.org/10.3390/electronics11142121

**Chicago/Turabian Style**

Tang, Hua, Yuanfei Wang, and David Wei Zhang.
2022. "A High-Stability Regulation Circuit with Adaptive Linear Pole–Zero Tracking Compensation for USB Type-C Interface" *Electronics* 11, no. 14: 2121.
https://doi.org/10.3390/electronics11142121