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Open AccessFeature PaperCommunication

An Efficient Connected Component Labeling Architecture for Embedded Systems

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Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, 87036 Rende, Italy
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Department of Mechanical, Energy and Management Engineering, University of Calabria, 87036 Rende, Italy
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Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2018, 8(1), 7; https://doi.org/10.3390/jlpea8010007
Received: 26 January 2018 / Revised: 1 March 2018 / Accepted: 3 March 2018 / Published: 6 March 2018
Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of the previous published algorithms have been designed for implementation by software. However, due to the large number of memory accesses and compare, lookup, and control operations when executed on a general-purpose processor, they do not satisfy the speed performance required by the next generation high performance computer vision systems. In this paper, we present the design of a new Connected Component Labeling hardware architecture suitable for high performance heterogeneous image processing of embedded designs. When implemented on a Zynq All Programmable-System on Chip (AP-SOC) 7045 chip, the proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than 18,000 LUTs and 5000 FFs, dissipating about 620 μJ. View Full-Text
Keywords: Connected Component Labeling; Heterogeneous SoC; FPGAs Connected Component Labeling; Heterogeneous SoC; FPGAs
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Spagnolo, F.; Frustaci, F.; Perri, S.; Corsonello, P. An Efficient Connected Component Labeling Architecture for Embedded Systems. J. Low Power Electron. Appl. 2018, 8, 7.

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