# Integrated Control and Protection Architecture for Islanded PV-Battery DC Microgrids: Design, Analysis and Experimental Verification

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## Abstract

**:**

## 1. Introduction

## 2. Proposed PV-Battery Islanded DC Microgrid

#### 2.1. PV System, Battery and Capacitor Bank Modeling

_{3}inductor current, and the C

_{1}and C

_{2}capacitors voltage, respectively. The control input $-1\le {u}_{1}\left(t\right)\le 1$ is a voltage, to control the output voltage of the PV system. The battery is also connected to a dc bus through a dc-dc converter. The measured variables are ${I}_{{L}_{6}}\left(t\right),{V}_{{C}_{4}}\left(t\right)$ and ${V}_{{C}_{5}}\left(t\right)$, that are L

_{6}inductor current, C

_{4}and C

_{5}capacitors voltage, respectively. The control input $-1\le {u}_{2}\left(t\right)\le 1$ is also a voltage, to control the battery output voltage. The capacitor bank is also connected to a dc bus through a dc-dc converter. The measured variables are ${I}_{{L}_{8}}\left(t\right)$ and ${V}_{{C}_{7}}\left(t\right)$, that are L

_{8}current and C

_{7}voltage, respectively. The control input $-1\le {u}_{3}\left(t\right)\le 1$ is also a voltage to control the output voltage of the capacitor bank.

#### 2.2. DC Microgrid Modeling

## 3. Proposed SDRE Nonlinear Observer-Controller

#### 3.1. SDRE Controller

#### 3.2. SDRE Observer

## 4. Simulation Results

^{−4}, and automatic minimum step size.

#### 4.1. SDRE Controller

_{pv}, the battery voltage V

_{B}, the capacitance bank voltage V

_{S}, and the load variations. It should be noted that in the following, it is assumed that these disturbances are independently altered, and their curves are given in Figure 3 and Figure 4.

_{1}and C

_{4}voltage, the SDRE controller was able to maintain the stability of the system after disturbances.

_{PV}and V

_{B}in the presence of the SDRE controller. As can be seen, the voltage and current of the PV system and the battery were controlled within a few seconds and restored to their equilibrium state.

#### 4.2. SDRE Observer

_{1}capacitor and another fault in 3.5 s in the C

_{4}capacitor. As shown in Figure 10, at this time, the C

_{1}voltage decreased from 300 V to 10 V, and the voltage of the C

_{4}capacitor decreased from 400 to 10 V, and correspondingly, in Figure 11, the output current of the PV system and the battery decreased. According to Figure 10, the fault detection time for the proposed SDRE method is 30 ms. Meanwhile, the fault detection system compares the actual system output with the output of the SDRE observer and formed a non-zero residual current, as shown in Figure 12, which, with the definition of the appropriate threshold—here the threshold is assumed 50 mA—makes it possible to detect the fault. As mentioned, among the most important issues in the field of fault detection is to not identify disturbances as faults. As shown in the previous section, despite the above-mentioned disturbances, Figure 11 shows that the fault occurrence system did not trip any of these times.

_{7}capacitor, and another in 4.5 s had occurred on the load bus. As shown in Figure 13 and Figure 14, at a moment of 2.5 s, the capacitor voltage C

_{7}decreased from 1000 to 500 V and the load bus voltage reduced from 1000 to 500 V. In this case, as shown in Figure 15, the capacitor-bank output current has increased. As it can be seen from Figure 16, the fault detection time for the proposed SDRE method is 30 ms. It is apparent in Figure 16, that the threshold was considered 50 mA which was feasible for fault detection.

_{1}capacitor within 0.4 ms. As can be seen from Figure 17, by selecting a threshold value of 50, the fault occurrence warning is not activated at this time.

_{1}is less than 3 mA in the disturbance condition, whereas the non-zero residual current of the C

_{1}is about 700 mA when the fault occurs. As a result, in order to provide the margin of assurance of the performance of the protection system, the threshold value of the fault occurrence is considered as 50 mA, so that both the fault occurrence is quickly detected and the disturbance is not considered as a fault.

## 5. Experimental Verification

_{1}capacitors during the fault occurrence without protection, with differential protection, and with SDRE observer protection. It is apparent, the transient three A fault current passes through the circuit without protection. While, by investigation of the SDRE-observer and the differential method figures, it can be deduced that the proposed SDRE observer protection detects the fault incidence more quickly. Obviously, the current value attains zero after the trip of IGBTs.

## 6. Discussion

_{2}and Δx

_{3}which is considered in the proposed method (Equation (9)). As a result, with the occurrence of uncertainty, the values of the state variables (Δx

_{2}and Δx

_{3}) will be changed and updated, and as a result, the proposed SDRE method can have the appropriate control and protection performance in this state. So, one of the merits of the proposed method is robustness against uncertainty.

## 7. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 5.**Voltage of C

_{1}and C

_{4}Capacitors in the presence of state-dependent Riccati equation (SDRE) controller.

**Figure 21.**Voltage of resistive load and the current of freewheeling in no protection, differential, and SDRE observer modes.

**Figure 22.**Voltage of IGBT breakers with snubber attendance in differential, and SDRE observer modes.

Parameters | Value | Parameters | Value | Parameters | Value |
---|---|---|---|---|---|

$0.033\mathrm{H}$ | ${L}_{3}$ | $0.1\mathsf{\Omega}$ | ${R}_{7}$ | $0.1\mathrm{F}$ | ${C}_{1}$ |

$0.033\mathrm{H}$ | ${L}_{6}$ | $0.01\mathsf{\Omega}$ | ${R}_{01}$ | $0.01\mathrm{F}$ | ${C}_{2}$ |

$0.0033\mathrm{H}$ | ${L}_{8}$ | $0.01\mathsf{\Omega}$ | ${R}_{02}$ | $0.1\mathrm{F}$ | ${C}_{4}$ |

$0.1\mathsf{\Omega}$ | ${R}_{2}$ | $0.01\mathsf{\Omega}$ | ${R}_{04}$ | $0.01\mathrm{F}$ | ${C}_{5}$ |

$0.1\mathsf{\Omega}$ | ${R}_{4}$ | $0.01\mathsf{\Omega}$ | ${R}_{05}$ | $0.01\mathrm{F}$ | ${C}_{7}$ |

$0.01\mathsf{\Omega}$ | ${R}_{5}$ | $0.01\mathsf{\Omega}$ | ${R}_{07}$ | $0.0001\mathrm{F}$ | ${C}_{9}$ |

$1000\mathrm{V}$ | ${V}_{bus}$ | $0.01\mathsf{\Omega}$ | ${R}_{08}$ | $0.1\mathsf{\Omega}$ | ${R}_{1}$ |

Equipment | Description |
---|---|

MASTECH HY3005-2, 30-V 3-A power supply, 2 channels | Utilized for 20 V V_{PV} and V_{B} |

MASTECH HY3005-2, 30-V 3-A power supply, 2 channels | Utilized for 20 V V_{S} |

10 Ω, 30-Watt resistor | Utilized for resistive dc load |

Three 15 μH inductor | Utilized for the inductance of V_{PV}, V_{B} and V_{s} |

Six 220 pF capacitor | Utilized for capacitance of V_{PV}, V_{B} and V_{s} |

Two STGW38IH130D IGBT modules | Utilized to for circuit breaker |

One IKW40N120H3 IGBT | Utilized to employ the line to ground (LG) fault |

FEP30GP Diode, 2 Ω resistor | Utilized for freewheeling branches |

FEP30GP Diode, 10 μF capacitor, 12 Ω resistor | Utilized for Resistance Capacitance Diode (RCD) snubber |

ATMEGA8L-8PU Microcontroller | Implemented for the protective system |

Three ACS 712-30 and ADS1115 modules | Utilized for sampling current, 3rd low-pass filter, A/D |

Three TC427CPA microchips, ULN2003 APC buffer | Utilized for insulated-gate bipolar transistors (IGBTs) gate drivers |

Two HCPL-7840 optocoupler | Utilized for differentiation of analog and digital grounds, noise decrement, isolation |

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**MDPI and ACS Style**

Abdali, A.; Mazlumi, K.; Guerrero, J.M.
Integrated Control and Protection Architecture for Islanded PV-Battery DC Microgrids: Design, Analysis and Experimental Verification. *Appl. Sci.* **2020**, *10*, 8847.
https://doi.org/10.3390/app10248847

**AMA Style**

Abdali A, Mazlumi K, Guerrero JM.
Integrated Control and Protection Architecture for Islanded PV-Battery DC Microgrids: Design, Analysis and Experimental Verification. *Applied Sciences*. 2020; 10(24):8847.
https://doi.org/10.3390/app10248847

**Chicago/Turabian Style**

Abdali, Ali, Kazem Mazlumi, and Josep M. Guerrero.
2020. "Integrated Control and Protection Architecture for Islanded PV-Battery DC Microgrids: Design, Analysis and Experimental Verification" *Applied Sciences* 10, no. 24: 8847.
https://doi.org/10.3390/app10248847