Next Article in Journal
Personalizing the Fitting of Hearing Aids by Learning Contextual Preferences From Internet of Things Data
Next Article in Special Issue
Low Effort Design Space Exploration Methodology for Configurable Caches
Previous Article in Journal
Promises and Pitfalls of Computer-Supported Mindfulness: Exploring a Situated Mobile Approach
Article Menu
Issue 1 (March) cover image

Export Article

Open AccessFeature PaperArticle
Computers 2018, 7(1), 3; https://doi.org/10.3390/computers7010003

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

1
Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721, USA
2
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA
*
Author to whom correspondence should be addressed.
Received: 24 November 2017 / Revised: 19 December 2017 / Accepted: 20 December 2017 / Published: 22 December 2017
(This article belongs to the Special Issue Multi-Core Systems-On-Chips Design and Optimization)
Full-Text   |   PDF [1576 KB, uploaded 22 December 2017]   |  

Abstract

Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system’s temperature not only affects the system’s reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead. View Full-Text
Keywords: dynamic thermal management; low-power embedded systems; phase-based tuning; temperature-aware tuning; energy savings; dynamic optimization; configurable caches; dynamic voltage and frequency scaling dynamic thermal management; low-power embedded systems; phase-based tuning; temperature-aware tuning; energy savings; dynamic optimization; configurable caches; dynamic voltage and frequency scaling
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Adegbija, T.; Gordon-Ross, A. TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems. Computers 2018, 7, 3.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Computers EISSN 2073-431X Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top