You are currently viewing a new version of our website. To view the old version click .
MDPIMDPI
Search all articles
Micromachines
Download PDF
  • Perspective
  • Open Access

30 December 2025

Hardware Accelerators for Cardiovascular Signal Processing: A System-on-Chip Perspective

,
,
,
and
1
School of Computing and Information Science, Anglia Ruskin University, East Rd., Cambridge CB1 1PT, UK
2
Arm Ltd., Cambridge CB1 9NJ, UK
*
Authors to whom correspondence should be addressed.
Micromachines2026, 17(1), 51;https://doi.org/10.3390/mi17010051 
(registering DOI)
This article belongs to the Special Issue Advances in Field-Programmable Gate Arrays (FPGAs)
Version Notes
Order Reprints

Abstract

This study presents a comprehensive systematic analysis, investigating hardware accelerators specifically designed for real-time cardiovascular signal processing, focusing mainly on Electrocardiogram (ECG), Photoplethysmogram (PPG), and blood pressure monitoring systems. Cardiovascular Diseases (CVDs) represent the world’s leading cause of morbidity and mortality, creating an urgent demand for efficient and accurate diagnostic technologies. Following the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) guidelines, we systematically analysed 59 research papers on this topic, published from 2014 to 2024, categorising them into three main categories: signal denoising, feature extraction, and decision support with Machine Learning (ML) or Deep Learning (DL). A comprehensive performance benchmarking across energy efficiency, processing speed, and clinical accuracy demonstrates that hybrid Field Programmable Gate Array (FPGA)-Application Specific Integrated Circuit (ASIC) architectures and specialised Artificial Intelligence (AI) on Edge accelerators represent the most promising solutions for next-generation CVD monitoring systems. The analysis identifies key technological gaps and proposes future research directions focused on developing ultra-low-power, clinically robust, and highly scalable physiological signal processing systems. The findings provide guidance for advancing hardware-accelerated cardiovascular diagnostics toward practical clinical deployment.

1. Introduction

Over 17.9 million people die from Cardiovascular Diseases (CVDs) every year [1], making them one of the leading causes of morbidity and mortality worldwide. According to the American Heart Association [2], CVD-related deaths are projected to increase to 23 million by 2030. The economic burden is also significant: in 2019, 12% of total healthcare expenditures in the United States, amounting to USD 422 billion, were attributed to CVDs [3]. Globally, this figure is expected to rise to USD 1.44 trillion annually by 2050 [4]. Early diagnosis and treatment are essential in reducing this burden. Evidence shows a strong correlation between early detection and improved treatment outcomes [5]. In many cases, early intervention requires only minimally invasive measures or simple lifestyle changes [6].
Continuous real-time monitoring is critical for the early detection and diagnosis of CVDs, driving demand for efficient signal processing solutions [7]. Among the most widely used techniques are Electrocardiogram (ECG), Photoplethysmogram (PPG), and blood pressure monitoring [8]. These signals reflect the heart’s electrical and circulatory activities, enabling the detection of conditions like arrhythmias and myocardial infarctions. However, raw physiological signals require sophisticated processing to extract clinically actionable insights. Software-only processing approaches often struggle with speed, power efficiency, and portability constraints. These limitations become particularly apparent in real-time medical applications. While offering flexibility, software solutions typically require transmitting raw data to external devices or cloud servers, introducing latency and high energy consumption [9]. These inefficiencies become critical barriers for wearable devices and remote monitoring systems where timely intervention depends on low-latency processing [10].
Hardware accelerators like Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs), have emerged as compelling solutions by enabling parallel, on-chip processing. Three key advantages distinguish hardware approaches: superior processing speed through parallel logic architectures [11]; reduced power consumption via optimised resource allocation and slower clock speeds [12]; and enhanced portability through compact designs suitable for wearable applications [5]. For example, hardware implementations can outperform software in both speed and energy efficiency, even when operating at lower clock frequencies, making them ideal for continuous monitoring scenarios.
The rapid diversification of hardware approaches, from FPGA-based ECG analysers to ASIC-optimised PPG pipelines, reflects both innovation and fragmentation in the field. This diversity stems from varying clinical requirements, signal characteristics (e.g., the high data rate of ECG versus lower-bandwidth Heart Rate Variability (HRV) signals [5]), and implementation constraints. Such variation underscores the need for a comprehensive analysis that evaluates trade-offs in processing architectures, benchmarks performance metrics, and identifies optimal solutions for specific CVD monitoring applications.
Analysing hardware accelerators for cardiovascular signal processing is particularly relevant today, as it helps to contextualise these technologies within the wider spectrum of solutions addressing specific physiological and clinical needs. It also helps to understand the role of emerging enabler technologies that support their development and deployment. During the analysis we learned that the evolving landscape of healthcare needs demands efficient, real-time, and accurate diagnostic devices for CVDs. Progress in miniaturised electronics has led to the creation of compact, wearable, and even implantable devices for continuous heart monitoring. In addition, significant progress has been made in Artificial Intelligence (AI) and Machine Learning (ML) algorithms, particularly Deep Learning (DL), for signal analysis and anomaly detection. These algorithms are computationally demanding, but they are essential for advanced health monitoring. Furthermore, the demand for Edge computing, known as AI at Edge, driven by the need to shift data processing closer to the source, has provided essential benefits in terms of real-time performance, enhanced privacy, and improved energy efficiency. Such capabilities are particularly valuable for continuous cardiac health monitoring applications. The convergence of these advancements highlights the growing need to evaluate how hardware acceleration has impacted cardiovascular signal processing. This analytical review systematically examines hardware acceleration techniques for processing key cardiovascular signals, including ECG, PPG, and blood pressure waveforms. It focuses on acceleration methods used for noise reduction, feature extraction, and disease classification, such as arrhythmia detection, blood pressure estimation, and sleep stage analysis. The analysis surveys solutions implemented using FPGAs, ASICs, Graphics Processing Units (GPUs), and specialised embedded Digital Signal Processings (DSPs) or AI accelerators, specifically targeting real-time, low-power applications at the Edge. Our analysis includes 59 peer-reviewed academic publications that develop or implement dedicated hardware solutions for cardiovascular signal processing. These works fall into three primary categories: Decision support with ML or DL (9 publications), Feature extraction (22 publications), and Denoising/Filtering (28 publications). To synthesise these diverse contributions into a coherent framework, we introduce a dedicated taxonomy that links target function, hardware technology, and algorithmic approach. This taxonomy structures the organisation of the subsequent sections and enables a consistent comparison across the reviewed accelerator designs. Based on the structured results we highlight key trends, technological trade-offs, and research gaps in the field of hardware acceleration for cardiovascular applications.
This paper is structured as follows: Section 2 provides background on cardiovascular signals and processing needs. Section 3 presents the methodology adopted to perform the critical analysis. Section 4 discusses the results, while Section 5 explores current limitations and future research directions. Finally, Section 6 concludes with a summary of key findings and highlights open challenges and opportunities for future work.

2. Context and Background

Cardiovascular signal processing demands high computational efficiency to enable real-time diagnostics in clinical and wearable settings. Hardware accelerators, specialised circuits designed to outperform general-purpose processors, address these needs by optimising performance, power, and chip area requirements for specific tasks. For instance, FPGAs and ASICs have been deployed to process ECG and PPG signals in real time, overcoming the limitations of traditional algorithms in memory-constrained Internet of Things (IoT) environments [12,13].

2.1. Cardiovascular Signals and Processing Challenges

ECGs are the gold standard for diagnosing arrhythmias and ischemic events. These signals represents the electrical activity of the heart through time–voltage waveforms [14], whereas PPGs measure blood volume changes non-invasively, enabling continuous monitoring via wearable devices. Processing these signals involves computationally intensive operations: noise removal (e.g., motion artifacts and powerline interference), feature extraction (e.g., QRS complexes which can be used to establish RR intervals), and classification using ML techniques [15]. Real-time analysis is critical for the early detection of conditions like Atrial Fibrillation (AF) and hypertension [16,17], yet manual interpretation remains laborious and error-prone [18].

2.2. Hardware Accelerators for Signal Processing: FPGAs and ASICs

The rapid development of digital hardware has been profoundly shaped by two key technologies: FPGAs and ASICs. Both play an important role in the design and implementation of electronic systems. Modern accelerators use FPGAs and ASICs to balance flexibility and efficiency. FPGAs excel in prototyping, offering (Configurable Logic Blocks (CLBs)) and low-latency parallel processing for adaptive filtering and ML inference [19,20]. For example, Finite Impulse Response (FIR) filters implemented on FPGAs achieve 30% lower power consumption through reversible logic designs [21]. ASICs, meanwhile, provide ultra-low-power solutions for wearable devices by customising hardware for specific algorithms like Ternary Neural Networks (TNNs) [22,23]. However, FPGAs incur higher per-unit costs, while ASICs lack post-fabrication flexibility. Initially introduced in the 1980s as arrays of interconnected CLBs based on reprogrammable technologies such as Flash, EPROM, and SRAM [24], FPGAs have since developed into advanced platforms capable of supporting high-performance and resource-intensive industrial applications. Modern FPGA architectures are emerging as comprehensive System-on-Chip (SoC) platforms that integrate both microprocessor and DSP cores [25]. This integration addresses the traditional dilemma of selecting between hardware fabric and processor-based architectures [24]. Consequently, embedded SoCs have become one of the most sought-after hardware platforms for digital electronic controllers [26]. Moreover, the direct implementation of neural network hardware algorithms on FPGA platforms provides significant advantages in terms of processing efficiency and real-time performance [27].

2.3. Key Algorithms and Accelerator Functions

The functionalities of the accelerators are grouped into three main categories: Denoising, Feature Extraction, and ML-based Decision Support. These are briefly outlined in the following sections.

2.3.1. Denoising

Noise in ECG signals, such as baseline wander and muscle artifacts, necessitates robust filtering. FIR and Infinite Impulse Response (IIR) filters dominate hardware implementations due to their deterministic latency and resource efficiency [28,29].

2.3.2. Feature Extraction

Feature extraction, which is critical for arrhythmia detection, often employs wavelet transforms or the Pan-Tompkins algorithm to isolate morphological features (P-waves and QRS complexes) [30]. For PPG signals, statistical metrics (e.g., skewness and kurtosis) are extracted to classify conditions like hypertension [31].

2.3.3. Machine Learning for Decision Support

ML algorithms, including Support Vector Machines (SVMs) are increasingly deployed on accelerators for real-time inference. SVMs can achieve high accuracy in HRV analysis but require hardware optimisations to mitigate computational overhead [10]. DL models, such as Convolutional Neural Networks (CNNs) and Recurrent Neural Networks (RNNs), automate feature extraction and improve diagnostic reliability for sequential ECG data [32]. Recent work demonstrates ASIC-based Artificial Neural Networks (ANNs) for arrhythmia detection with sub-milliwatt power consumption [23].

2.4. Benchmarking and Databases

Evaluating accelerators requires standardised datasets. Widely used databases include:
  • MIT–BIH Arrhythmia Database: 48 half-hour ECG recordings (360 Hz) for arrhythmia classification [33].
  • PTB Diagnostic Database: 549 high-resolution ECG records (1000 Hz) for myocardial infarction detection [34].
  • PPG-BP Database: 657 synchronised PPG and blood pressure traces for hypertension analysis [35].
For a full comparison, see Table A1 in Appendix A.

3. Hardware Accelerators for Cardiovascular Signal Processing

3.1. Systematic Literature Review Protocol

This analytical review adhered to the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) guidelines to ensure methodological rigour. The flow diagram, shown in Figure 1, details the study selection process. The initial search across Google Scholar (83 records), Scopus (135), IEEE Xplore (135), and PubMed (20) yielded 373 unique publications on hardware accelerators for cardiovascular signal processing. After automated removal of 131 duplicate records, 242 studies underwent manual screening, which excluded 148 conference publications due to insufficient peer-review scrutiny. Table A2 in Appendix B provides the search terms used for the individual databases.
Figure 1. Identification of studies via databases and registers.
Of the remaining 94 studies selected for full-text retrieval, 7 were inaccessible through institutional subscriptions. The subsequent eligibility assessment of 87 articles applied stringent criteria: only peer-reviewed journal papers demonstrating physical implementations (FPGA, ASIC, or hybrid architectures) for ECG, PPG, or blood pressure processing were considered. This phase excluded 28 works comprising books, non-English publications, irrelevant studies, theses, and papers outside our defined taxonomy. The final synthesis incorporated 59 studies that met all quality and relevance thresholds.

3.2. Taxonomic Classification and Comparative Framework

To systematically analyse and compare the diverse landscape, we develop and adopt a three-axis taxonomy that structures the review. This taxonomy, complemented by a defined set of evaluation metrics, provides the structure for our subsequent analysis. It is built upon three independent classification axes that capture the essential characteristics of any accelerator design: its target function, its implementation technology, and its algorithmic approach. The structure of this taxonomy is depicted in Figure 2 and Figure 3.
Figure 2. Three-dimensional taxonomy overview for hardware accelerators. A specific accelerator is classified by its position along these three axes, defining its purpose (function), platform (technology), and core method (algorithm).
Figure 3. Detailed taxonomy of accelerator functionalities. This hierarchy provides the structure used to organise the reviewed works in the Section 4.

3.2.1. Taxonomic Axes

Figure 2 shows a three-dimensional coordinate system depicting the criteria with which the reviewed papers were analysed. Each axis is detailed in the following paragraphs.
Target Function
The primary purpose of the accelerator defines its highest-level classification. This axis categorises the stage of the cardiovascular signal processing pipeline that the hardware is designed to accelerate. The target function is used to structure the results presentation, which takes the form of one table each for Decision Support, Feature Engineering, and Denoising/Filtering in Section 4. The taxonomy, shown in Figure 3, introduces the subcategories within the target function.
  • Denoising and Filtering: The initial signal conditioning stage, focused on removing noise and artifacts to improve signal quality.
  • Feature Extraction: The process of identifying and isolating clinically relevant features from the cleaned signal.
  • Decision Support: The highest-level function, involving the classification of signals or extracted features to support diagnostic decisions.
Implementation Technology
This axis classifies the hardware platform on which the accelerator is implemented, which dictates its performance, power, and flexibility characteristics.
  • FPGA: Field-Programmable Gate Arrays offer reconfigurability and high parallelism, making them ideal for prototyping and research.
  • ASIC: Application-Specific Integrated Circuits provide the highest performance and lowest power consumption for a fixed function, making them suitable for mass-produced devices.
Algorithmic Approach
This axis categorises the core computational algorithm that the hardware is designed to execute efficiently.
  • Digital Filters: Includes finite/infinite impulse response (FIR/IIR) filters and adaptive filters (e.g., LMS).
  • Transform-Based Methods: Includes methods like the DFT with its efficient form known as the FFT and Wavelet transforms.
  • ML and DL: Encompasses models ranging from traditional classifiers like SVMs to deep learning architectures like CNNs and DCNs.

3.2.2. Comparative Analysis Framework

The taxonomy provides a categorical basis for comparison. To enable a quantitative cross-evaluation of works within and across these categories, we established a consistent comparative framework based on the following key metrics, which were extracted from each study:
  • Hardware-Centric Metrics: These metrics evaluate the physical efficiency and performance of the accelerator implementation.
    –
    Power Consumption (mW): Critical for wearable and implantable devices.
    –
    Area Efficiency (gate count or mm2): Measures the silicon footprint, which is directly related to cost.
    –
    Throughput (samples/s or inferences/s): Determines the capability for real-time processing.
  • Algorithm-Centric Metrics: These metrics evaluate the clinical efficacy and quality of the processing output. The specific metric is tied to the Target Function of the accelerator.
    –
    Denoising: Noise suppression ratio (dB) and Percentage Root-mean-square Difference (Percentage Root mean square Difference (PRD)).
    –
    Feature Extraction/Decision Support: Clinical accuracy (F1-score, sensitivity and specificity), benchmarked against gold-standard databases (MIT–BIH, PTB and PPG-BP).
This combined approach of taxonomic classification and metric standardisation allows us to establish a meaningful analysis of design trade-offs. For example, it enables the comparison of how different Algorithmic Approaches (e.g., LMS vs. Wavelet) within the same Target Function (Denoising) impact Hardware-Centric Metrics (power and area on an FPGA).
The subsequent Results section (Section 4) is structured primarily along the Target Function axis. The findings within each sub-section are analysed and discussed using this comparative framework, highlighting trends and performance across the dimensions of technology and algorithm.

4. Results

This section follows the taxonomy introduced in Section 3.2, structuring the findings along the target-function axis with cross-references to implementation technology and algorithmic method. The analysis of 59 studies reveals a diverse and evolving landscape of hardware accelerators for cardiovascular signal processing. The findings are structured according to the taxonomic framework established in Section 3.2, beginning with the primary classification by Target Function. The distribution of research efforts across these functions, illustrated in Figure 4, shows a historical focus on Denoising and Feature Extraction, with a marked increase in Decision Support research in recent years, coinciding with advancements in ML and DL. The next sections analyse the papers according to the Target Function. The analysis results are mutably exclusive, each reviewed paper has a unique target function.
Figure 4. Bar graph depicting the distribution of published papers over the years from 2014 to 2024. Each bar indicates the number of papers published in the fields of Denoising, Feature extraction, and Decision support, within one year.

4.1. Decision Support Systems

The reviewed Decision Support systems, summarised in Table 1, demonstrate the critical role of hardware acceleration in enabling complex classification tasks for cardiovascular diagnostics. These implementations are predominantly characterised by high clinical accuracy, with many systems achieving performance metrics exceeding 99% sensitivity and specificity on standardised datasets such as MIT–BIH and PTB. The algorithmic approach to establish decision support functionality is dominated by ML techniques, particularly SVMs and various neural network architectures including ANNs, TNNs, and DCNs. A notable trend is the technological split based on application requirements: FPGA-based implementations offer a flexible platform for prototyping and deploying sophisticated DL models, as evidenced by works from Aruna et al. [18] and Shanthi et al. [32], while ASIC-based solutions, such as those by Abubakar et al. [22] and Zhang et al. [23], are pursued for their ultra-low-power characteristics, essential for wearable and implantable long-term monitoring devices. The radar chart shown in Figure 5 effectively visualises the high accuracy benchmarks set by these systems, underscoring their readiness for clinical application. Note: Reference [36] addresses a seven-class disease classification problem (Normal, Diabetes, Cerebral infarction, Cerebrovascular disease, Hypertension, Hypertension and diabetes, and Diabetes and pre-hypertension), which is fundamentally more challenging than the binary classification tasks reported by other works in this table. Therefore, the 79.83% accuracy should not be directly compared with binary classification accuracies of 95% or higher reported elsewhere in the table. Reference [36] should not be considered lower performance; rather, it addresses a more complex and clinically valuable multi-class classification problem.
Table 1. Decision support.
Figure 5. Area Under the Curve (AUC) performance of ECG-based AF prediction [9,18,22,23,30,31,32,36].

4.2. Feature Extraction Accelerators

Feature Extraction, representing the largest category of works as shown in Table 2 and Figure 6, forms a bridge between raw signal processing and clinical decision-making. The primary focus of work in this domain lies in QRS complex and R-peak detection for ECG signals. A significant number of implementations achieve accuracy rates above 99%. The performance metrics for these systems highlight substantial improvements in processing speed and energy efficiency compared to software-based implementations. For instance, Lee et al. [13] demonstrated a 90% reduction in execution time, while Wang et al. [12] reported a 142-fold improvement in energy efficiency. From a technological perspective, FPGA platforms offer parallel processing capabilities, which render them well suited to meet the algorithmic demands of real-time wavelet transforms and Pan–Tompkins-based detection schemes. ASIC implementations, though less numerous, focus on minimising energy consumption per operation, as seen in the work of Pamula et al. [37], achieving up to a 30-fold power reduction. Work in this area demonstrates a mature understanding of hardware–software co-design, where algorithmic efficiency is meticulously mapped onto hardware resources.
Table 2. Feature extraction.
Figure 6. Synthetic comparison of FPGA, ASIC, and GPU.

4.3. Denoising and Filtering Functionality

The Denoising and Filtering functionality, detailed in Table 3, constitutes the foundational layer of the processing pipeline, ensuring signal integrity for subsequent stages. The algorithmic approaches within this category are primarily digital filters, including FIR, IIR, and adaptive LMS variants, alongside transform-based methods like FFT and Wavelet transforms. The evaluation metrics for these works emphasise hardware efficiency, such as power consumption, area reduction, and resource utilisation, alongside algorithm-centric metrics like signal-to-noise ratio improvement and PRD. A dominant theme is the optimisation of these classical algorithms for hardware implementation. For example, Kalamani et al. [56] achieved area reductions exceeding 90% for lattice LMS filters, while Jayashree et al. [21] demonstrated a 30% power reduction through reversible logic designs. The technological landscape is almost exclusively dominated by FPGA implementations, which provide the necessary reconfigurability and rapid prototyping environment for exploring various filter architectures and their hardware trade-offs. This suggests that, while denoising is a mature field algorithmically, significant innovation continues in optimising its hardware realisation for low-power, resource-constrained edge devices.
Table 3. Denoising.

5. Discussion

The field of hardware acceleration for cardiovascular signal processing is both rapidly evolving and important for improving public health, as evidenced by the increasing publication trend shown in Figure 4. This growth is driven by the urgent need for technologies that enable early detection and continuous monitoring of CVDs, moving clinical care from reactive treatment to proactive prediction. The reviewed works demonstrate significant progress in developing wearable ECG monitors, implantable loop recorders, and embedded systems for ambulances that can relay patient conditions to hospitals in real time via wireless technologies [5,15,23,32].

5.1. Synthesis of Taxonomic Findings

The multi-dimensional taxonomy developed for this analytical review provides a lens through which we analyse the landscape of hardware accelerators. A correlation exists between the Target Function of an accelerator and its optimal Algorithmic Approach. Digital filters and transform-based methods have proven to be reliable workhorses of the Denoising stage, providing deterministic performance and efficient hardware mapping. In contrast, Decision Support functionality is increasingly dominated by ML and DL algorithms, which offer superior accuracy for complex classification tasks like arrhythmia detection. Feature Extraction exhibits a hybrid approach, often utilising highly optimised digital signal processing algorithms, such as the Pan–Tompkins method for robust and efficient QRS complex detection. The temporal analysis of publications reflects this technological evolution, showing a noticeable shift from traditional denoising and feature extraction methods toward more complex ML-based decision support systems in recent years. This highlights the growing influence of AI in cardiovascular informatics.
This analysis also underscores the engineering trade-offs inherent in accelerator design, as revealed by our comparative framework. Within Denoising, for example, the choice between a simple FIR filter and a more complex adaptive LMS filter involves a direct trade-off between hardware resource consumption and denoising performance and flexibility. Similarly, in Decision Support, the high accuracy of DL models on FPGA platforms comes at the cost of higher power and area consumption compared to simpler SVM implementations on ASIC. These trade-offs underscore the paramount importance of a holistic design strategy that aligns the algorithmic approach and implementation technology with the specific clinical and operational requirements of the target application, whether a high-accuracy bedside monitor or an ultra-low-power wearable patch.

5.2. The State of Deep Learning in Hardware Accelerators

A key finding from our systematic search, detailed in Section 3, is the relative scarcity of hardware implementations incorporating DL for decision support within the final selection of 59 papers. While the broader field is actively exploring DL [79], its adoption in physically realised hardware accelerators appears to lag behind software-based research. This gap highlights a significant translation challenge. Although works like that of Tsoutsouras et al. [10] successfully demonstrate custom hardware for SVM acceleration with a 94% improvement in execution latency, they also reveal the complexities of balancing performance gains with resource utilisation. The current predominance of traditional ML models, like SVM, in implemented systems suggests that the high computational demands and large memory footprint of DL models remain a substantial barrier to their widespread deployment on resource-constrained hardware platforms, despite their potential for superior accuracy.

5.3. Limitations and Challenges

Despite the promising advantages of hardware-accelerated ML and DL, several formidable challenges persist. The need for large, diverse, and well-annotated datasets for training robust models remains a primary bottleneck. Furthermore, the chaotic and non-stationary nature of physiological signals like ECG and PPG complicates automated analysis and makes models susceptible to noise and artifacts [79]. Beyond algorithmic challenges, hardware limitations include power consumption constraints for wearable devices, the high non-recurring engineering costs of ASIC development, and the need for formal verification and regulatory approval for clinical use.

5.4. Latency Considerations for Clinical Relevance

Latency from signal acquisition to classification is a critical metric for cardiovascular monitoring, particularly for life-threatening events such as myocardial infarction, where delays of only a few seconds can affect patient survival. In contrast, non-dangerous arrhythmias (e.g., occasional premature ventricular contractions) tolerate longer processing times. Across the reviewed hardware implementations, most FPGA-based denoising and feature extraction pipelines achieve sub-millisecond to few-millisecond processing times per sample window, enabled by highly parallel filter structures and deeply pipelined architectures. Wavelet-based preprocessors and Haar-filter accelerators, for example, report extremely low-latency operation with efficient resource utilisation [28,61], while adaptive lattice-LMS and FIR-filter designs also demonstrate rapid streaming performance [56,57,71]. Similar real-time behaviour is seen in digital filter designs optimised for resource efficiency [66,72].
End-to-end classification systems generally exhibit slightly higher but still real-time latencies. Hardware implementations integrating beat detection or arrhythmia classification, such as SVM-like or threshold-based decision modules, typically achieve window-level inference times below 10–20 ms [74,76]. These values fall well within the real-time requirements for wearable and ambulatory monitors, where sampling rates are modest (125–500 Hz) and per-beat analysis windows span 200–300 ms.
However, only a minority of studies explicitly quantify acquisition-to-decision latency, with several works focusing primarily on accuracy or resource utilisation without reporting end-to-end timing [11,21]. This lack of consistent latency reporting remains an important gap, particularly for ultra-low-power or implantable devices where strict real-time guarantees are essential.

5.5. Future Directions

Future research should focus on bridging the gap between software-based DL innovation and its efficient hardware realisation. Promising directions include the development of novel model compression techniques (e.g., pruning, quantisation), hardware-aware neural architecture search, and the exploration of efficient DL architectures such as binary neural networks specifically designed for embedded deployment.
Beyond algorithmic efficiency, several emerging hardware trends warrant deeper investigation. Near-sensor and in-sensor computing offer the potential to reduce data movement and enable ultra-low-power preprocessing at the point of acquisition. Compute-in-memory architectures can alleviate the growing memory-access bottleneck in DL-based cardiovascular workloads, while event-driven or neuromorphic accelerators may better exploit the sparsity and intermittency of physiological signals. These approaches require new hardware–software co-design methodologies and rigorous real-world validation.
The field must also move beyond diagnosis towards true disease prediction. Future systems should aim to anticipate adverse cardiac events before symptoms manifest, fundamentally shifting the paradigm from reactive care to proactive health management [5]. This will likely involve multi-modal sensor fusion (e.g., ECG + PPG), edge–cloud collaborative processing, and lifelong learning algorithms that adapt to patient-specific physiology. Continued research in these directions will be essential to develop clinically robust, power-efficient, and scalable cardiovascular monitoring systems.

5.6. Integration into Commercial SoC Platforms

Modern wearable and implantable cardiovascular devices increasingly utilise heterogenous SoC architectures that integrate application processors such as the ARM Cortex-M or Cortex-A families with specialised subsystems to support system control, user interface, and wireless communication. These platforms incorporate dedicated hardware accelerators to offload computationally intensive signal processing and ML inference tasks, enabling real-time ECG and PPG analysis under strict energy constraints. In addition, contemporary SoCs integrate advanced power management units that provide fine-grained power gating and dynamic voltage/frequency scaling to extend battery life during continuous monitoring. Wireless communication blocks supporting both proprietary and standardised protocols are included to ensure reliable data transmission in clinical and consumer environments, while secure elements offer hardware-level encryption, authentication, and tamper resistance to safeguard sensitive patient data.

5.7. Bridging the DL-to-Hardware Gap: Model Optimisation Techniques

State-of-the-art DL models for cardiovascular signal processing face a fundamental challenge when deployed on resource constrained hardware. Although this review highlights the clear gap between software-based DL and its limited physical implementation on hardware accelerators, several well-established optimisation techniques can help bridge this divide by allowing efficient DL execution under tight computational and energy constraints. In order to bridge this gap, three primary model compression techniques are commonly used: Quantisation, Pruning, and Binarisation. Our analysis found that 78% of hardware-implemented DL accelerators employ at least one of these techniques. Quantisation enhances efficiency by representing weights and activations with reduced precision, which simplifies arithmetic units and allows more parallel operations within the same hardware budget. Pruning removes redundant connections which in turn reduces network size, lowering memory computation without significantly sacrificing accuracy. Finally, binarisation is an extreme form of quantisation in which full-precision operations are replaced with 1 bit or 2 bit weight representations. These models are highly compatible with ASIC design and provide a promising pathway for translating high-accuracy DL models into highly efficient hardware implementations suitable for edge-based cardiovascular monitoring systems.

6. Conclusions

This systematic analytical review has synthesised the current state-of-the-art in hardware accelerators for cardiovascular signal processing, analysing 59 studies through a novel multi-dimensional taxonomy based on target function, implementation technology, and algorithmic approach. The accelerating publication trend underscores the critical role of specialised hardware in enabling real-time, low-power, and accurate analysis of ECG and PPG signals, which is paramount for the next generation of wearable and implantable medical devices.
The primary contribution of this paper lies in its structured analysis, which reveals several key insights. Firstly, a clear correlation exists between the target function of an accelerator and its optimal algorithmic approach, with digital filters dominating denoising tasks while machine learning methods are increasingly central to decision support. Secondly, a fundamental trade-off between flexibility and efficiency is evident in the choice of implementation technology; FPGAs are favoured for research and prototyping due to their reconfigurability, whereas ASICs are pursued for ultra-low-power consumption in commercial wearable applications. Finally, this paper identifies a significant opportunity in bridging the gap between software-based deep learning innovation and its efficient hardware realisation, an area that remains underexplored in physically implemented systems.
Looking forward, the field presents positive and fertile ground for research. The path ahead involves the development of hybrid platforms that exploit the reconfigurability of FPGAs and the low-power properties of ASICs, to create viable solutions that exploit novel event-driven and asynchronous architectures. An important step in validating these solutions is the creation of more representative benchmarks for fair comparison. Future work must focus on hardware-optimised implementations of DL techniques and robust preprocessing strategies to combat noise and motion artifacts. By further integrating hardware and software co-design principles, the next wave of accelerators will not only enhance performance and efficiency but also improve resilience and reliability, ultimately enabling a transformative shift from intermittent diagnosis to continuous, predictive cardiovascular health management.
Despite these opportunities, important unresolved challenges remain. These include the need for more representative and standardised benchmarks, the difficulty of mapping complex DL models onto highly resource-constrained hardware, and the lack of robust real-world validation under noise, motion artefacts, and inter-patient variability. By addressing these gaps and further integrating hardware–software co-design principles, the next wave of accelerators will not only enhance performance and efficiency but also improve resilience and clinical reliability, ultimately enabling a transformative shift from intermittent diagnosis to continuous, predictive cardiovascular health management.

Author Contributions

Conceptualisation, R.H. and O.F.; methodology, R.H. and O.F.; software, R.H. and O.F.; validation, R.H. and O.F.; formal analysis, R.H. and O.F.; investigation, R.H. and O.F.; resources, R.H. and O.F.; data curation, R.H. and O.F.; writing—original draft preparation, R.H. and O.F.; writing—review and editing, All authors; visualisation, All authors; supervision, All authors; project administration, All authors; funding acquisition, All authors. All authors have read and agreed to the published version of the manuscript.

Funding

This research was made possible due to the facilities provided by Anglia Ruskin University and Arm Ltd.

Institutional Review Board Statement

Not applicable.

Data Availability Statement

No new data were created or analyzed in this study. Data sharing is not applicable to this perspective.

Conflicts of Interest

Author Khaled Benkrid was employed by the company Arm Ltd. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

Abbreviations

The following abbreviations are used in this manuscript:
AFAtrial Fibrillation
ANNArtificial Neural Network
AIArtificial Intelligence
ASICApplication Specific Integrated Circuit
DLDeep Learning
CLBConfigurable Logic Block
CNNConvolutional Neural Network
CRCompression Ratio
CVDCardiovascular Disease
DCNDeep Convolutional Network
DFTDiscrete Fourier Transform
DSPDigital Signal Processing
ECGElectrocardiogram
FFFlip Flop
FFTFast Fourier Transform
FIRFinite Impulse Response
FPGAField Programmable Gate Array
GPUGraphics Processing Unit
HRVHeart Rate Variability
IoTInternet of Things
IIRInfinite Impulse Response
LMSLeast Mean Square
LUTLookup Table
MLMachine Learning
MPUMicroprocessing Unit
PPGPhotoplethysmogram
PRISMAPreferred Reporting Items for Systematic Reviews and Meta-Analyses
PRDPercentage Root mean square Difference
RNNRecurrent Neural Network
SNRimpSingle Noise Reservoir Improvement
SoCSystem-on-Chip
SVMSupport Vector Machine
TNNTernary Neural Network
AUCArea Under the Curve

Appendix A. Benchmark Databases

Table A1. Databases used in benchmarking.
Table A1. Databases used in benchmarking.
Database NameRecords NumbersDurationSampling RateMeta Data
MIT–BIH Arrhythmia Database [33]48 ECG records.30 min per record.360 Hz.The data consists of 47 human subjects: 25 men aged 32 to 89 years, and 22 women aged 23 to 89 years.
MIT–BIH Noise Stress Test Database [80]12 ECG records and 3 records of noise.30 min per record.360 Hz.The data consists of 2 clean recordings (118 and 119) from the MIT–BIH Arrhythmia database.
MIT–BIH Normal Sinus Rhythm Database [81]18 long-term ECG records.10 min per record.128 Hz.The data consists of 5 men aged 26 to 45, and 13 women aged 20 to 50 years. It is widely used in ECG signal analysis as well as in training various ML algorithms for heartbeat analysis.
PTB Diagnostic Database [34]549 ECG records.10 min per record.1000 Hz.The data consists of 294 human subjects including healthy subjects and patients with a variety of heart diseases. The data consists of 209 men aged 17 to 87 years and 81 women with a mean age of 61.6 years. It is widely used in cardiac disease diagnosis and abnormality classification.
PPG-BP
Database [35]		657 records with PPG and blood pressure.2.1 s per record.125 Hz for PPG and 1000 Hz for blood pressure.The data consists of 219 adults, 104 men and 115 women, aged 21 to 86 years. Widely used for hypertension detection and blood pressure prediction as well as cardiovascular disease analysis.
CSE ECG
Database [82]		1000 ECG records.8 to 10 s per record.500 Hz.Widely used for arrhythmia detection and cardiovascular disease diagnosis.
AF Termination Challenge Database [83]60 ECG records.60 s per record.128 Hz.Widely used for the analysis of AF termination during cardioversion.
QT Database [84]105 ECG records.15 min per record.250 Hz.The data consists of ECG signals from the MIT–BIH Arrhythmia Database and several other ECG databases. Widely used in analysing QT intervals for arrhythmia prediction.
ECG-ID
Database [85]		310 ECG records.20 s per record.500 Hz.The data consists of 90 volunteers, 44 men and 46 women aged from 13 to 75 years. Widely used for biometric human identification based on ECG.

Appendix B. Search Terms

Table A2. Database search terms.
Table A2. Database search terms.
DatabaseSearch Strategy
Google Scholar through Publish or Perish.("Title words":FPGA AND ECG) OR ("Title words":Field Programmable Gate Array AND Electrocardiogram) OR ("Title words":FPGA AND Electrocardiogram) OR ("Title words":Field Programmable Gate Array AND ECG) OR ("Title words":FPGA AND PPG) OR ("Title words":Field Programmable Gate array AND Photoplethysmography) OR ("Title words":FPGA AND Photoplethysmography) OR ("Title words":Field Programmable Gate array AND PPG) OR ("Title words":ASIC AND ECG) OR ("Title words":Application Specific Integrated Circuit AND Electrocardiogram) OR ("Title words":ASIC AND Electrocardiogram) OR ("Title words":Application Specific Integrated Circuit AND ECG) OR ("Title words":ASIC AND PPG) OR ("Title words":Application Specific Integrated Circuit AND Photoplethysmography) OR ("Title words":ASIC AND Photoplethysmography) OR ("Title words":Application Specific Integrated Circuit AND PPG)
Scopus.("Article title":FPGA AND ECG) OR ("Article title":Field Programmable Gate Array AND Electrocardiogram) OR ("Article title":FPGA AND Electrocardiogram) OR ("Article title":Field Programmable Gate Array AND ECG) OR ("Article title":FPGA AND PPG) OR ("Article title":Field Programmable Gate array AND Photoplethysmography) OR ("Article title":FPGA AND Photoplethysmography) OR ("Article title":Field Programmable Gate array AND PPG) OR ("Article title":ASIC AND ECG) OR ("Article title":Application Specific Integrated Circuit AND Electrocardiogram) OR ("Article title":ASIC AND Electrocardiogram) OR ("Article title":Application Specific Integrated Circuit AND ECG) OR ("Article title":ASIC AND PPG) OR ("Article title":Application Specific Integrated Circuit AND Photoplethysmography) OR ("Article title":ASIC AND Photoplethysmography) OR ("Article title":Application Specific Integrated Circuit AND PPG)
PubMed.(ti =FPGA AND ECG) OR (ti =Field Programmable Gate Array AND Electrocardiogram) OR (ti =FPGA AND Electrocardiogram) OR (ti =Field Programmable Gate Array AND ECG) OR (ti =FPGA AND PPG) OR (ti =Field Programmable Gate array AND Photoplethysmography) OR (ti =FPGA AND Photoplethysmography) OR (ti =Field Programmable Gate array AND PPG) OR (ti =ASIC AND ECG) OR (ti =Application Specific Integrated Circuit AND Electrocardiogram) OR (ti =ASIC AND Electrocardiogram) OR (ti =Application Specific Integrated Circuit AND ECG) OR (ti =ASIC AND PPG) OR (ti =Application Specific Integrated Circuit AND Photoplethysmography) OR (ti =ASIC AND Photoplethysmography) OR (ti =Application Specific Integrated Circuit AND PPG)
IEEE Xplore.("Document title":FPGA AND ECG) OR ("Document title":Field Programmable Gate Array AND Electrocardiogram) OR ("Document title":FPGA AND Electrocardiogram) OR ("Document title":Field Programmable Gate Array AND ECG) OR ("Document title":FPGA AND PPG) OR ("Document title":Field Programmable Gate array AND Photoplethysmography) OR ("Document title":FPGA AND Photoplethysmography) OR ("Document title":Field Programmable Gate array AND PPG) OR ("Document title":ASIC AND ECG OR ("Document title":Application Specific Integrated Circuit AND Electrocardiogram) OR ("Document title":ASIC AND Electrocardiogram) OR ("Document title":Application Specific Integrated Circuit AND ECG) OR ("Document title":ASIC AND PPG) OR ("Document title":Application Specific Integrated Circuit AND Photoplethysmography) OR ("Document title":ASIC AND Photoplethysmography) OR ("Document title":Application Specific Integrated Circuit AND PPG)

References

  1. Paul, L.; Das, P.K.; Rahaman, A.T.; Nizamuddin, H.M.; Aushe, K.J. The silent Killer in your pantry-How sodium overload contributes to cardiovascular diseases. IOSR J. Dent. Med Sci. 2025, 24, 63–68. [Google Scholar] [CrossRef]
  2. Angell, S.Y.; McConnell, M.V.; Anderson, C.A.; Bibbins-Domingo, K.; Boyle, D.S.; Capewell, S.; Ezzati, M.; De Ferranti, S.; Gaskin, D.J.; Goetzel, R.Z.; et al. The American Heart Association 2030 impact goal: A presidential advisory from the American Heart Association. Circulation 2020, 141, e120–e138. [Google Scholar] [CrossRef]
  3. de Araújo, J.M.; Eufrosino de Alencar Rodrigues, R.; da Costa Pereira de Arruda Neta, A.; Leite Lima Ferreira, F.E.; Lira Formiga Cavalcanti de Lima, R.; Pinheiro de Toledo Vianna, R.; Vasconcelos Leitão Moreira, L.; Moreira da Silva Neto, J.; Moreira, P.V.L. The direct and indirect costs of cardiovascular diseases in Brazil. PLoS ONE 2022, 17, e0278891. [Google Scholar] [CrossRef]
  4. Rwebembera, J.; Marangou, J.; Mwita, J.C.; Mocumbi, A.O.; Mota, C.; Okello, E.; Nascimento, B.; Thorup, L.; Beaton, A.; Kado, J. 2023 World Heart Federation guidelines for the echocardiographic diagnosis of rheumatic heart disease. Nat. Rev. Cardiol. 2024, 21, 250–263. [Google Scholar] [CrossRef]
  5. Faust, O.; Hong, W.; Loh, H.W.; Xu, S.; Tan, R.S.; Chakraborty, S.; Barua, P.D.; Molinari, F.; Acharya, U.R. Heart rate variability for medical decision support systems: A review. Comput. Biol. Med. 2022, 145, 105407. [Google Scholar] [CrossRef] [PubMed]
  6. Fukumoto, Y. Lifestyle intervention for primary prevention of cardiovascular diseases. Eur. J. Prev. Cardiol. 2022, 29, 2250–2251. [Google Scholar] [CrossRef]
  7. Abo-Zahhad, M.; Zakaria, A.A.; Abozeid, A.M.; Abo-Zahhad, M.M. A Real-Time Health Monitoring System for Remote Cardiac Patients. In Proceedings of the 2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC), Alexandria, Egypt, 18–19 December 2023; IEEE: New York, NY, USA, 2023; pp. 110–114. [Google Scholar]
  8. Mishra, B.; Arora, N.; Vora, Y. An ECG-PPG wearable device for real time detection of various arrhythmic cardiovascular diseases. In Proceedings of the 2019 9th International Symposium on Embedded Computing and System Design (ISED), Kollam, India, 13–14 December 2019; IEEE: New York, NY, USA, 2019; pp. 1–5. [Google Scholar]
  9. Giorgio, A.; Guaragnella, C.; Rizzi, M. FPGA-based decision support system for ECG analysis. J. Low Power Electron. Appl. 2023, 13, 6. [Google Scholar] [CrossRef]
  10. Tsoutsouras, V.; Koliogeorgi, K.; Xydis, S.; Soudris, D. HLS code transformation strategies and directives exploration for FPGA accelerated ECG analysis. In Proceedings of the Workshop in Reconfigurable Computing, Prague, Czech Republic, 21 February 2016; Springer: Berlin/Heidelberg, Germany, 2016. [Google Scholar]
  11. Uttraphan, C.; Ardani, M.I.A.; Heng, C.W.; Ahmad, N.; Ching, K.B.; Raj, A.A.E. Hardware Implementation of FIR Filter for ECG Signal Processing: Design, Optimization, and Performance Analysis on an FPGA. J. Adv. Res. Appl. Sci. Eng. Technol. 2024, 40, 50–61. [Google Scholar] [CrossRef]
  12. Wang, X.; Zhu, Y.; Ha, Y.; Qiu, M.; Huang, T. An FPGA-based cloud system for massive ECG data analysis. IEEE Trans. Circuits Syst. II Express Briefs 2016, 64, 309–313. [Google Scholar] [CrossRef]
  13. Lee, D.; Lee, S.; Oh, S.; Park, D. Energy-efficient FPGA accelerator with fidelity-controllable sliding-region signal processing unit for abnormal ECG diagnosis on IoT edge devices. IEEE Access 2021, 9, 122789–122800. [Google Scholar] [CrossRef]
  14. Goldberger, A.L.; Goldberger, Z.D.; Shvilkin, A. Goldberger’s Clinical Electrocardiography-E-Book: A Simplified Approach; Elsevier Health Sciences: Amsterdam, The Netherlands, 2023. [Google Scholar]
  15. Karataş, F.; Koyuncu, I.; Tuna, M.; Alçın, M.; Avcioglu, E.; Akgul, A. Design and implementation of arrhythmic ECG signals for biomedical engineering applications on FPGA. Eur. Phys. J. Spec. Top. 2022, 231, 869–884. [Google Scholar] [CrossRef]
  16. Luo, D.Y.; Zhang, Z.W.; Sibomana, O.; Izere, S. Comparison of diagnostic accuracy of electrocardiogram-based versus photoplethysmography-based smartwatches for atrial fibrillation detection: A Systematic Review and Meta-Analysis. Ann. Med. Surg. 2025, 87, 2307–2323. [Google Scholar] [CrossRef]
  17. Whelton, P.K.; Williams, B. The 2018 European society of cardiology/European society of hypertension and 2017 American college of cardiology/American heart association blood pressure guidelines: More similar than different. JAMA 2018, 320, 1749–1750. [Google Scholar] [CrossRef]
  18. Aruna, V.B.K.L.; Chitra, E.; Padmaja, M. Accelerating deep convolutional neural network on FPGA for ECG signal classification. Microprocess. Microsyst. 2023, 103, 104939. [Google Scholar] [CrossRef]
  19. Khan, M.I.; da Silva, B. Harnessing FPGA technology for energy-efficient wearable medical devices. Electronics 2024, 13, 4094. [Google Scholar] [CrossRef]
  20. Chandrasekaran, S.; Chandran, S.; Selvam, I.J. FPGA-Based Implementation of Real-Time Cardiologist-Level Arrhythmia Detection and Classification in Electrocardiograms Using Novel Deep Learning. Int. J. Circuit Theory Appl. 2025, 53, 3662–3683. [Google Scholar] [CrossRef]
  21. Jayashree, S.; Sakthivel, S.M. FPGA implementation of optimized FIR filter for ECG denoising using peresreversible logic gate. J. Theor. Appl. Inf. Technol. 2022, 100, 4582–4594. [Google Scholar]
  22. Abubakar, S.M.; Yin, Y.; Tan, S.; Jiang, H.; Wang, Z. A 746 nW ECG processor ASIC based on ternary neural network. IEEE Trans. Biomed. Circuits Syst. 2022, 16, 703–713. [Google Scholar] [CrossRef] [PubMed]
  23. Zhang, C.; Chang, J.; Guan, Y.; Li, Q.; Wang, X.; Zhang, X. A Low-Power ECG Processor ASIC Based on an Artificial Neural Network for Arrhythmia Detection. Appl. Sci. 2023, 13, 9591. [Google Scholar] [CrossRef]
  24. Monmasson, E.; Idkhajine, L.; Cirstea, M.N.; Bahri, I.; Tisan, A.; Naouar, M.W. FPGAs in industrial control applications. IEEE Trans. Ind. Inform. 2011, 7, 224–243. [Google Scholar] [CrossRef]
  25. Monmasson, E.; Hilairet, M.; Spagnuolo, G.; Cirstea, M.N. System-on-chip FPGA devices for complex electrical energy systems control. IEEE Ind. Electron. Mag. 2021, 16, 53–64. [Google Scholar] [CrossRef]
  26. Cirstea, M.; Benkrid, K.; Dinu, A.; Ghiriti, R.; Petreus, D. Digital electronic system-on-chip design: Methodologies, tools, evolution, and trends. Micromachines 2024, 15, 247. [Google Scholar] [CrossRef]
  27. Dinu, A.; Cirstea, M.N.; Cirstea, S.E. Direct neural-network hardware-implementation algorithm. IEEE Trans. Ind. Electron. 2009, 57, 1845–1848. [Google Scholar] [CrossRef]
  28. Alhelal, D.; Aboalayon, K.A.; Daneshzand, M.; Faezipour, M. FPGA-based denoising and beat detection of the ECG signal. In Proceedings of the 2015 Long Island Systems, Applications and Technology, Farmingdale, NY, USA, 1 May 2015; IEEE: New York, NY, USA, 2015; pp. 1–5. [Google Scholar]
  29. Saha, S.; Mandal, S.B. FPGA implementation of IIR elliptic filters for de-noising ECG signal. Biomed. Signal Process. Control 2024, 96, 106544. [Google Scholar] [CrossRef]
  30. hadi Mazidi, M.; Eshghib, M.; reza Raoufyc, M. FPGA implementation of wearable ECG system for detection premature ventricular contraction. Int. J. COMADEM 2019, 22, 51–59. [Google Scholar]
  31. Chowdhury, A.; Chowdhury, M.H.; Das, D.; Ghosh, S.; Cheung, R.C.C. FPGA Implementation of PPG-Based Cardiovascular Diseases and Diabetes Classification Algorithm. Arab. J. Sci. Eng. 2024, 49, 16697–16709. [Google Scholar] [CrossRef]
  32. Shanthi, K.G.; Kinol, A.; Joy, M.; Santhi, S.; Kannan, K. Real-time FPGA Integration for ECG Monitoring: Bidirectional Recurrent Chimp Search Model. IETE J. Res. 2024, 70, 6848–6863. [Google Scholar] [CrossRef]
  33. Moody, G.B.; Mark, R.G. The impact of the MIT–BIH arrhythmia database. IEEE Eng. Med. Biol. Mag. 2001, 20, 45–50. [Google Scholar] [CrossRef]
  34. Tsai, T.H.; Tsai, F.L. Efficient lossless compression scheme for multi-channel ECG signal processing. Biomed. Signal Process. Control 2020, 59, 101879. [Google Scholar] [CrossRef]
  35. Liang, Y.; Chen, Z.; Liu, G.; Elgendi, M. A new, short-recorded photoplethysmogram dataset for blood pressure monitoring in China. Sci. Data 2018, 5, 180020. [Google Scholar] [CrossRef]
  36. Chowdhury, A.; Das, D.; Hasan, K.; Cheung, R.C.C.; Chowdhury, M.H. An FPGA implementation of multiclass disease detection from PPG. IEEE Sens. Lett. 2023, 7, 6007604. [Google Scholar] [CrossRef]
  37. Pamula, V.R.; Valero-Sarmiento, J.M.; Yan, L.; Bozkurt, A.; Van Hoof, C.; Van Helleputte, N.; Yazicioglu, R.F.; Verhelst, M. A 172 μW/Compressively Sampled Photoplethysmographic (PPG) Readout ASIC with Heart Rate Estimation Directly From Compressively Sampled Data. IEEE Trans. Biomed. Circuits Syst. 2017, 11, 487–496. [Google Scholar] [CrossRef]
  38. Matsumoto, Y.; Tanaka, T.; Sonoda, K.; Kanda, K.; Fujita, T.; Maenaka, K. Low-Power ECG Processing ASIC. Electron. Commun. Jpn. 2016, 99, 13–20. [Google Scholar] [CrossRef]
  39. Habiboullah, A.; Terosiet, M.; Histace, A.; Romain, O. Improvement of a FPGA-based Detection of QRS Complexes in ECG Signal using an Adaptive Windowing Strategy. In Proceedings of the BIOSIGNALS, Rome, Italy, 21–23 February 2016; pp. 327–332. [Google Scholar]
  40. García Limón, J.A.; Martínez-Suárez, F.; Alvarado-Serrano, C. Implementation of wavelet-transform-based algorithms in an FPGA for heart rate and rt interval automatic measurements in real time: Application in a long-term ambulatory electrocardiogram monitor. Micromachines 2023, 14, 1748. [Google Scholar] [CrossRef]
  41. Roy Chowdhury, S. High-resolution detection of sustained ventricular and supraventricular tachycardia through FPGA-based fuzzy processing of ECG signal. Med Biol. Eng. Comput. 2015, 53, 1037–1047. [Google Scholar] [CrossRef] [PubMed]
  42. Aravind Kumar, M.; Manjunatha Chari, K. Efficient FPGA-based VLSI architecture for detecting R-peaks in electrocardiogram signal by combining Shannon energy with Hilbert transform. IET Signal Process. 2018, 12, 748–755. [Google Scholar] [CrossRef]
  43. Al-Shueli, A.I. Optimized implementation of ECG signal noise cancelation using FIR and IIR filter techniques based on FPGA. Eurasian J. Eng. Technol. 2022, 9, 43–54. [Google Scholar]
  44. Bodisco, T.; D’Netto, J.; Kelson, N.; Banks, J.; Hayward, R. Computation of ECG signal features using MCMC modelling in software and FPGA reconfigurable hardware. Procedia Comput. Sci. 2014, 29, 2442–2448. [Google Scholar] [CrossRef]
  45. Abdul-Kadir, N.A.; Safri, N.M.; Othman, M.A. ASIC design of natural frequency of ECG signal for atrial fibrillation detection module using high-level synthesis approach. J. Teknol. 2015, 74. [Google Scholar] [CrossRef]
  46. Jain, S.K.; Bhaumik, B. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection. Healthc. Technol. Lett. 2016, 3, 77–84. [Google Scholar] [CrossRef] [PubMed]
  47. Da He, D.; Sodini, C.G. A 58 nW ECG ASIC with motion-tolerant heartbeat timing extraction for wearable cardiovascular monitoring. IEEE Trans. Biomed. Circuits Syst. 2014, 9, 370–376. [Google Scholar]
  48. Abburi, R.; Rani, M.A. A Wavelet architecture for Abdominal ECG preprocessing and fetal QRS detection implemented in FPGA using 90nm technology. Int. J. Recent Technol. Eng. 2019, 8, 2762–2768. [Google Scholar] [CrossRef]
  49. Nagpal, N.; Chawla, M.; Phillips, D. A Simple FPGA Based ECG R Wave Peak Detection System For Heart Rate And Heart Rate Variability Calculation. Int. J. Eng. Res. Appl. 2014, 4, 33–36. [Google Scholar]
  50. Gu, X.; Zhu, Y.; Zhou, S.; Wang, C.; Qiu, M.; Wang, G. A real-time FPGA-based accelerator for ECG analysis and diagnosis using association-rule mining. ACM Trans. Embed. Comput. Syst. (TECS) 2016, 15, 1–23. [Google Scholar] [CrossRef]
  51. Desai, M.; Caffarena, G.; Jevtic, R.; Márquez, D.G.; Otero, A. A Low-Latency, Low-Power FPGA Implementation of ECG Signal Characterization Using Hermite Polynomials. Electronics 2021, 10, 2324. [Google Scholar] [CrossRef]
  52. Ganatra, M.M.; Vithalani, C.H. A novel morphological feature extraction approach for ECG signal analysis based on generalized synchrosqueezing transform, correntropy function and adaptive heuristic framework in FPGA. J. Circuits, Syst. Comput. 2022, 31, 2250312. [Google Scholar] [CrossRef]
  53. Alouneh, S.; Al-Shayeji, M.; Abed, S.; Samrajesh, M.D.; Sultan, S. FPGA enhanced implementation of ECG QRS complex detection algorithm. Int. J. Circuits Syst. Signal Process 2015, 9, 327–336. [Google Scholar]
  54. Chatterjee, H.; Mitra, M.; Gupta, R. Real–time detection of electrocardiogram wave features using template matching and implementation in FPGA. Int. J. Biomed. Eng. Technol. 2015, 17, 290–313. [Google Scholar] [CrossRef]
  55. Noor, S.M.; John, E.; Panday, M. Design and implementation of an ultralow-energy FFT ASIC for processing ECG in cardiac pacemakers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 27, 983–987. [Google Scholar] [CrossRef]
  56. Kalamani, C.; Kamatchi, S.; Sasikala, S.; Murali, L. The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals. Autom. časopis Za Autom. Mjer. Elektron. Računarstvo I Komun. 2023, 64, 772–782. [Google Scholar]
  57. Reddy, P.V.; Tallapragada, V.V.S. FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor. Analog Integr. Circuits Signal Process. 2024, 119, 331–361. [Google Scholar] [CrossRef]
  58. Elbedwehy, A.N.; El-Mohandes, A.M.; Elnakib, A.; Abou-Elsoud, M.E. FPGA-based reservoir computing system for ECG denoising. Microprocess. Microsys. 2022, 91, 104549. [Google Scholar] [CrossRef]
  59. Egila, M.G.; El-Moursy, M.A.; El-Hennawy, A.E.; El-Simary, H.A.; Zaki, A. FPGA-based electrocardiography (ECG) signal analysis system using least-square linear phase finite impulse response (FIR) filter. J. Electr. Syst. Inf. Technol. 2016, 3, 513–526. [Google Scholar] [CrossRef]
  60. Venkatesan, C.; Karthigaikumar, P.; Varatharajan, R. FPGA implementation of modified error normalized LMS adaptive filter for ECG noise removal. Clust. Comput. 2019, 22, 12233–12241. [Google Scholar] [CrossRef]
  61. Sohal, H.; Jain, S. FPGA implementation of collateral and sequence pre-processing modules for low power ECG denoising module. Inform. Med. Unlocked 2022, 28, 100838. [Google Scholar]
  62. Janwadkar, S.; Dhavse, R. ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier. Int. J. Circuit Theory Appl. 2024, 52, 1621–1646. [Google Scholar] [CrossRef]
  63. Patel, V.; Shah, A. Denoising of Electrocardiogram Signal using Multiband Filter and its Implementation on FPGA. SJEE 2022, 19, 115–128. [Google Scholar] [CrossRef]
  64. Aboutabikh, K.; Haidar, I.; Aboukerdah, N. Design and implementation of a digital FIR notch filter for the ECG signals using FPGA. Int. J. Adv. Res. Comput. Commun. Eng. 2016, 5, 452–456. [Google Scholar] [CrossRef]
  65. Priya, V.A.; Muralidhar, M. Design and Implementation of Digital Adaptive Filter on Spartan-6 FPGA for ECG Signal Processing. Int. J. VLSI Syst. Des. Commun. Syst. 2014, 2, 494–498. [Google Scholar]
  66. Çancıoğlu, E.; Cancioglu, E.; Çakıroğlu, G.; Cakiroglu, G.; Gökçen, A.; Gokcen, A.; Altanay, Y.S.; Altanay, Y.S. Design and Implementation of Digital Filters for ECG Data Based on Field Programmable Gate Array and MATLAB. Akıllı Sist. Ve Uygulamaları Derg. 2020, 3, 17–19. [Google Scholar]
  67. Patel, V.; Shah, A. Design and implementation of low power FPGA-based optimal multiband filter with Spline function for denoising ECG signals. Comput. Methods Biomech. Biomed. Eng. 2025, 28, 226–237. [Google Scholar] [CrossRef] [PubMed]
  68. Anusuya, S.; Samiappan, D.; Buvaneswari, P.R. Design and Implementation of Motion Artifact Reduction Asic for Wearable Ecg Recording. Am.-Eurasian J. Sci. Res. 2015, 10, 154–159. [Google Scholar]
  69. Gon, A.; Mukherjee, A. Design and FPGA Implementation of an Efficient Architecture for Noise Removal in ECG Signals Using Lifting-Based Wavelet Denoising. In Proceedings of the 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), Guwahati, India, 23–24 March 2023; IEEE: New York, NY, USA, 2023; Volume 1, pp. 1–6. [Google Scholar]
  70. Sakthivel, S.M.; Reddy, O.S. Fault Tolerant FPGA Implementation on Redundancy Techniques and ECG Denoising. arXiv 2023, arXiv:2304.08165. [Google Scholar] [CrossRef]
  71. Shingne, H.B.; Dhanashri, H.G. FPGA based design and implementation of cascaded FIR filter for ECG signal processing. In Proceedings of the IDES Joint International Conferences on IPC and ARTEE, Bangalore, India, 15–17 December 2017; pp. 1673–1678. [Google Scholar]
  72. Ganatra, M.M.; Vithalani, C.H. FPGA design of a variable step-size variable tap length denlms filter with hybrid systolic-folding structure and compressor-based booth multiplier for noise reduction in ECG signal. Circuits Syst. Signal Process. 2022, 41, 3592–3622. [Google Scholar] [CrossRef]
  73. Sohal, H.; Jain, S. FPGA implementation of Power-Efficient ECG pre-processing block. In Lecture Notes in Networks and Systems; Springer: Berlin/Heidelberg, Germany, 2019; Volume 106. [Google Scholar]
  74. Padmavathi, C.; Veenadevi, S.V. An optimized FPGA based system design for the arrhythmia detection using ECG. Int. J. Innov. Technol. Explor. Eng. (IJITEE) 2019, 9, 2808–2818. [Google Scholar]
  75. Polat, Ö.; KAYHAN, S. FPGA implementation of LSD-OMP for real-time ECG signal reconstruction. Turk. J. Electr. Eng. Comput. Sci. 2021, 29, 1887–1907. [Google Scholar] [CrossRef]
  76. Alhelal, D.; Faezipour, M. Denoising and beat detection of ECG signal by Using FPGA. Int. J. High Speed Electron. Syst. 2017, 26, 1740016. [Google Scholar] [CrossRef]
  77. Sasikala, S.; Murugesan, G.; Gomathi, S. FPGA Implementation of Combination of Error Normalised Sign LMS and Zero Attractor-ENSLMS Algorithms for Denoising ECG Signals. Asian J. Res. Soc. Sci. Humanit. 2016, 6, 683–697. [Google Scholar] [CrossRef]
  78. Mohanraj, R.; Vimala, R. ECG Signal Denoising with Field-Programmable Gate Array Implementation of Fast Digital Finite Impulse Response and Infinite Impulse Response Filters. J. Med. Imaging Health Inform. 2020, 10, 81–85. [Google Scholar] [CrossRef]
  79. Faust, O.; Hagiwara, Y.; Hong, T.J.; Lih, O.S.; Acharya, U.R. Deep learning for healthcare applications based on physiological signals: A review. Comput. Methods Programs Biomed. 2018, 161, 1–13. [Google Scholar] [CrossRef]
  80. Moody, G.; Muldrow, W.; Mark, R. The MIT–BIH noise stress test database. Comput. Cardiol. 1984, 11, 381–384. [Google Scholar]
  81. Goldberger, A.L.; Amaral, L.A.; Glass, L.; Hausdorff, J.M.; Ivanov, P.C.; Mark, R.G.; Mietus, J.E.; Moody, G.B.; Peng, C.K.; Stanley, H.E. PhysioBank, PhysioToolkit, and PhysioNet: Components of a new research resource for complex physiologic signals. Circulation 2000, 101, e215–e220. [Google Scholar] [CrossRef] [PubMed]
  82. Smíšek, R.; Maršánová, L.; Němcová, A.; Vítek, M.; Kozumplík, J.; Nováková, M. CSE database: Extended annotations and new recommendations for ECG software testing. Med Biol. Eng. Comput. 2017, 55, 1473–1482. [Google Scholar] [CrossRef]
  83. Okada, M. A digital filter for the QRS complex detection. IEEE Trans. Biomed. Eng. 1979, BME-26, 700–703. [Google Scholar] [CrossRef] [PubMed]
  84. Laguna, P.; Mark, R.G.; Goldberg, A.; Moody, G.B. A database for evaluation of algorithms for measurement of QT and other waveform intervals in the ECG. In Proceedings of the Computers in Cardiology 1997, Lund, Sweden, 7–10 September 1997; IEEE: New York, NY, USA, 1997; pp. 673–676. [Google Scholar]
  85. Lugovaya, T.S. Biometric Human Identification Based on ECG. Master’s Thesis, Electrotechnical University, Saint-Petersburg, Russian, 2005. [Google Scholar]
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Article Metrics

Citations

Article Access Statistics

Journal Statistics
Article metric data becomes available approximately 24 hours after publication online.
Download PDF
Design of a Bandgap Reference with a High PSRR and Strong Load-Driving Capability
Previous
Examination of Impact of NBTIs on Commercial Power P-Channel VDMOS Transistors in Practical Applications
Next