A New Single-Stage Four-Switch Common-Ground-Type Buck–Boost Inverter

Abstract

The output voltages of photovoltaic panels typically fluctuate due to variations in environmental conditions, and therefore the use of a buck–boost inverter is essential. This article presents a novel buck–boost voltage-source inverter topology. The proposed inverter is transformerless and thus is smaller and lower-cost than isolated topologies. The topology consists of four switches but only two of them operate at a high switching frequency during each half-cycle, which significantly reduces switching losses and improves efficiency. Furthermore, a common-ground connection between the inverter input and output effectively suppresses leakage current by mitigating the common-mode voltage issue. The modulation strategy, circuit operation, and design guidelines are presented in detail. Simulation and experimental results at 500 W are also provided to verify the effectiveness of the proposed inverter topology.

1. Introduction

Power inverters are extensively utilized in renewable energy applications and can be broadly classified as voltage-source inverters (VSIs) [1] and current-source inverters (CSIs) [2]. Unlike CSIs, VSIs are more commonly employed in grid-connected photovoltaic (PV) applications due to their stable power-injection capability and relatively simple control techniques. VSIs are further classified as isolated and non-isolated inverters. Isolated inverters are effective in mitigating the leakage current. However, they require either high-frequency (HF) or low-frequency (LF) transformers [3,4,5], which increase system size and cost while reducing conversion efficiency and power density.

Unlike isolated inverters, the non-isolated VSIs do not employ transformers and are therefore typically approximately 1–2% more efficient than the isolated inverters. The full-bridge inverter, a widely adopted transformerless topology in industrial applications [6], is well-known for its effective utilization of the DC input voltage and its ability to generate high-quality AC output voltage. Despite these advantages, conventional H-bridge inverter topologies can regulate the output voltage only with in the range of input supply, effectively operating as buck-type converter, and hence are not suitable for PV applications. In addition, environmental factors like temperature variations, solar irradiance, partial shadings, and dust accumulation on PV panels cause the voltage of PV panels to fluctuate [7]. Therefore, the inverter system must posses buck–boost capability to ensure proper voltage regulation.

To achieve the buck–boost functionality, a boost converter is often cascaded to the conventional bridge-type inverter [8,9], as shown in Figure 1. In order to realize buck–boost functionality, the front stage DC–DC converter provides voltage boosting, while the VSI performs buck operation. Although the two-stage approach enables buck–boost operation, it suffers from reduced overall efficiency due to its multiple power conversion stages. Another disadvantage is the presence of the full-bridge inverter between source and load eliminating the common-ground possibility. As a result, common-mode voltage (CMV) and leakage currents can arise, even when a DC–DC converter shares a ground reference with the input source. To overcome these disadvantages of the conventional full-bridge inverter, improved designs like H6 [10] and HERIC [11,12] have been developed, with primary focus on leakage current reduction. However, these structures typically require additional switches and incur higher conduction losses, in addition to the front-stage DC–DC converter.

Figure 1. An illustration of single-stage and two-stage inverter configurations.

As a result, common-ground inverter topologies have been widely studied as an effective solution for reducing leakage current. This is accomplished by directly linking the grid’s neutral and the negative terminals of the PV panels, thereby maintaining constant common-mode voltage. Various single-stage inverters with buck–boost and common-ground functionality have been developed. A common-ground-type inverter with buck–boost functionality was introduced in [13], which offers zero leakage current and wide input voltage range but at the cost of higher complexity and increased switching losses due to multiple switches operating at high frequency in each half-cycle. Similarly, switched-capacitor-based topologies [14,15] achieves high voltage gain and common-mode voltage suppression but requires additional components and complex modulation, which increases the complexity of the design.

To overcome these limitations, a novel common-ground buck–boost inverter (CG-BBI) is proposed, as illustrated in Figure 2. The proposed CG-BBI achieves both buck and boost operation over a wide input-voltage range in a single-stage configuration, without requiring additional DC–DC converters or isolation transformers. It features a reduced component count and establishes a direct common-ground connection between the input and output, which effectively eliminates leakage current and enhances compatibility with PV applications. Furthermore, only two of the switches operate at high switching frequency during each half-cycle, which significantly reduces switching losses and improves overall conversion efficiency.

Figure 2. Proposed structure of single-stage CG-BBI.

2. Modulation Strategy and Operating Modes of CG-BBI Topology

The proposed CG-BBI modulation strategy and the corresponding gate signal generation control block diagram are presented in Figure 3 and Figure 4, respectively. For the interval where the output voltage is positive $(v_o>0)$, as shown in Figure 3, the switch $S_1$ is always ON, and $S_3$ is always OFF while the switches $S_2$ and $S_4$ are switching complementarily at high frequency. For the output voltage to be negative $(v_o<0)$, as shown in Figure 3, the switch $S_2$ remains ON, and $S_4$ stays OFF while the switches $S_1$ and $S_3$ are switching complementarily at high frequency. CG-BBI has four modes of operation throughout a switching cycle. Modes 1 and 2 correspond to the positive half $(v_o>0)$, whereas modes 3 and 4 correspond to the negative half $(v_o<0)$.

Figure 3. PWM control scheme for the proposed single-stage CG-BBI.

Figure 4. The proposed structure block diagram for gate signal generation.

To generate a control signal $S_1$, a reference signal $V_{ref}$ = $GSin\left(wt\right)$ is multiplied with a rectangular signal of line frequency, having a duty cycle of 0.5 and an amplitude of 1. The resulting half-sinusoidal signal is then added to a constant value of 1. The reciprocal of the resulting DC-biased sinusoidal signal is compared to a 50 kHz triangular carrier ($V_{tri}$). Similarly, to obtain the gating signal of $S_2$, the reference signal $V_{ref}$ = $GSin(wt-180)$ is multiplied with the inverted rectangular signal of the line frequency, having a duty cycle of 0.5 and an amplitude of 1. The resulting half-sinusoid is then added to a constant of magnitude 1. Then the reciprocal of this DC-biased half-sinusoid is compared to the triangular carrier ($V_{tri}$) with a 50 kHz switching frequency.

Mode 1: In this operating mode, switches $S_1$ and $S_4$ are turned ON, as illustrated in Figure 5a. Although $S_1$ is ON, no current flows through it due to the reverse-biased body diode of switch $S_2$. During this interval, diode $D_2$ conducts, allowing inductor $L_2$ to be energized by capacitor C, while the input source $V_{\mathrm{in}}$ simultaneously stores energy in inductor $L_1$. The voltages appearing across inductors $L_1$ and $L_2$ in this mode are given by

$$v_{L1}=V_{in}$$

(1)

$$v_{L2}=V_c$$

(2)

Figure 5. Modes of operation of CG-BBI for $v_0>0$ (a) Mode 1 (b) Mode 2.

Mode 2: In this operating mode, $S_1$ and $S_2$ are ON as shown in Figure 5b. The capacitor C is charged, and the inductor $L_2$ is de-energized through the output. The voltages appear on both the inductors $L_1$ and $L_2$ are

$$v_{L1}=V_{in}-V_c-V_o$$

(3)

$$v_{L2}=-V_o$$

(4)

The duration of mode 1 is $d_{1}T$, while the duration of mode 2 is $(1-d_1)T$. From the volt–sec balance condition of $L_1$ and $L_2$, the voltage gain $G(=V_0/V_{in})$ for $v_0>0$ is

$$G={\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{d_1}{1-d_1}}$$

(5)

where $d_1$ is the duty ratio of $S_3$ and can alternatively be represented as a function of the voltage gain as

$$d_1={\displaystyle \frac{GSin\left(wt\right)}{1+GSin\left(wt\right)}}$$

(6)

$$1-d_1={\displaystyle \frac{1}{1+GSin\left(wt\right)}}$$

(7)

Mode 3: In this operating mode, $S_2$ and $S_3$ are ON, as shown in Figure 6a. Although $S_2$ is ON, no current flows through it due to the reverse-biased body diode of switch $S_1$. During this interval, diode $D_1$ conducts, and inductor $L_2$ is energized by $v_{in}$ through switch $S_3$ and diode $D_1$. The voltages on both the inductors $L_1$ and $L_2$ are

$$v_{L1}=-V_{in}$$

(8)

$$v_{L2}=V_{in}$$

(9)

Figure 6. Modes of operation of CG-BBI for $v_0<0$: (a) mode 3, (b) mode 4.

Mode 4: In this operating mode, $S_2$ and $S_1$ are ON, as shown in Figure 6b. The inductor $L_2$ is de-energized through the output in this mode. The voltages appearing on both the inductors $L_1$ and $L_2$ are

$$v_{L1}=-V_o$$

(10)

$$v_{L2}=V_o$$

(11)

The duration of mode 3 is $d_{2}T$, while the duration of mode 4 is $(1-d_2)T$. From the volt–sec balance condition of $L_1$ and $L_2$, the voltage gain $G(=V_0/V_{in})$ for $v_0<0$ is

$$G={\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{-d_2}{1-d_2}}$$

(12)

where $d_2$ is the duty ratio of $S_4$ and can alternatively be represented in terms of the voltage gain as

$$d_2={\displaystyle \frac{GSin\left(wt\right)}{GSin\left(wt\right)-1}}$$

(13)

$$1-d_2={\displaystyle \frac{1}{1+GSin(wt-180)}}$$

(14)

The voltage gain from Equations (7) and (14) is plotted in Figure 7. As observed, the optimal voltage gain approaches infinity when the duty ratio approaches one. Also, a gain in unity is achieved for a duty ratio of 50%. As can be seen in Figure 7, the gain curve is almost linear for duty ratios less than 0.5, corresponding to operation in buck mode. For duty ratios exceeding 50%, the converter operates in boost mode, where the voltage gain exhibits nonlinear behavior with respect to the duty ratio.

Figure 7. Voltage gain verses duty ratio curves of the proposed CG-BI.

3. Common-Mode Voltage Analysis

In transformerless PV inverters connected to the grid, leakage current can flow between the PV panels and the grid ground through parasitic capacitances. These capacitances form an unintended path for high-frequency common-mode current, which is primarily driven by variations in the common-mode voltage generated during inverter switching. The resulting leakage current can degrade electromagnetic compatibility (EMC) performance, trigger ground fault protection mechanisms, pose safety risks, and reduce overall system reliability. Therefore, minimizing common-mode voltage variations and effectively mitigating leakage current are critical for meeting safety standards and ensuring stable and reliable inverter operation.

Figure 8a shows the proposed inverter grid-connected configuration, while Figure 8b presents a generalized block diagram of a grid-connected inverter. In Figure 8, P and N represent the positive and negative connections of the PV panel, while $C_{PV+}$ and $C_{PV-}$ represent the parasitic capacitors. The filter inductors are represented by $L_x$ and $L_y$. The leakage current depends on the common-mode voltages ($v_{CM}$) and differential-mode voltage ($v_{DM}$). In Figure 8 the common-mode voltage ($v_{CM}$) and differential-mode voltage ($v_{DM}$) can be found as [16]

$$\begin{array}{c}\hfill v_{CM}={\displaystyle \frac{v_{xN}+v_{yN}}{2}}\end{array}$$

(15)

$$v_{DM}=v_{xN}-v_{yN}$$

(16)

where $v_{xN}$ and $v_{yN}$ are output voltages of the inverter, referenced to the negative terminal $\left(N\right)$ of the input.

Figure 8. (a) Proposed CG-BBI topology in grid-connected mode. (b) Block diagram of a typical grid-connected inverter.

The inverters that are connected to a grid are generally categorized as either symmetrical or asymmetrical inductor-based structures. In symmetrical configuration [17,18,19], the inverter input is not directly connected to its output, and two symmetrical output inductors are required to limit the leakage current, which is dependent on $v_{CM}$ given in (15). Unlike symmetrical configurations, the asymmetrical inductor-based inverters need a single output filter inductor, and its output is directly connected to the input [20,21,22]. The leakage current depends on the total common-mode voltages ($v_{TCM}$) given as [23]

$$\begin{array}{c}\hfill v_{TCM}={\displaystyle \frac{v_{xN}+v_{yN}}{2}}+{\displaystyle \frac{v_{xN}-v_{yN}}{2}}.{\displaystyle \frac{l_y-l_x}{l_y+l_x}}\end{array}$$

(17)

In the CG-BBI topology shown in Figure 8a, because of the asymmetrical inductor-based inverter configuration, $l_y=0$, and therefore the above mentioned equation becomes

$$v_{TCM}=v_{yN}$$

(18)

Due to the common-ground nature, both ends y and N are shorted. Hence $v_{yN}$ becomes zero, ensuring the absence of any higher switching-frequency common-mode voltage in the proposed inverter.

4. Design Parameters of the Proposed Inverter

4.1. Switch Voltage Stresses

The voltage stress on each switch, relative to maximum output voltage $\left(V_o\right)$ and as a function of voltage gain $(G=V_o/V_{in})$, are obtained as follows

$${\displaystyle \frac{V_{stress(S_3,S_4)}}{V_o}}={\displaystyle \frac{2}{G}}$$

(19)

$${\displaystyle \frac{V_{stress(S_1,S_2)}}{V_o}}={\displaystyle \frac{1+G}{G}}$$

(20)

4.2. Switch Current Stresses

The current stresses on the switches, relative to maximum output current $\left(I_o\right)$ and as a function of voltage gain $(G=V_o/V_{in})$, are obtained as follows

$${\displaystyle \frac{I_{stress(S_3,S_4)}}{I_o}}=G$$

(21)

$${\displaystyle \frac{I_{stress(S_1,S_2)}}{I_o}}=1+G$$

(22)

4.3. Inductor Design

The value of inductors $L_1$ and $L_2$ can be found as a function of voltage gain as

$$L_1={\displaystyle \frac{V_o}{{\displaystyle \Delta i_{L1\left(max\right)}.f_{sw}}}}({\displaystyle \frac{1}{1+G}})$$

(23)

$$L_2={\displaystyle \frac{V_o}{{\displaystyle \Delta i_{L2\left(max\right)}.f_{sw}}}}({\displaystyle \frac{1}{1+G}})$$

(24)

In the above-mentioned equations, $\Delta i_{L1\left(max\right)}=x(\%)I_{L1}$, where $I_{L1}$ is equal to $G{I}_o$. $\Delta i_{L2\left(max\right)}=x(\%)I_{L2}$, and $I_{L2}$ is equal to $(1+G)I_o$. The value of x is usually selected from 10 to 30. Putting these values in the above equations, the value of inductors $(L_1,L_2)$ can be calculated as

$$L_1={\displaystyle \frac{\left(V_o\right).100}{x.I_o.f_{sw}}}.{\displaystyle \frac{1}{G(1+G)}}$$

(25)

$$L_2={\displaystyle \frac{\left(V_o\right).100}{x.I_o.f_{sw}}}.{\displaystyle \frac{1}{{(1+G)}^2}}$$

(26)

From the above equations, the inductance of the inductors decreases as the voltage gain increases. Therefore, the minimal voltage gain is used to determine it.

4.4. Capacitor Design

Capacitors are designed to suppress the ripples in the output voltage, resulting in smooth output waveform. The capacitance of C and $C_o$ can be derived in term of voltage gain by

$$C\ge {\displaystyle \frac{I_C}{y(\%)V_o.f_{sw}}}({\displaystyle \frac{G}{1+G}})$$

(27)

$$C_o\ge {\displaystyle \frac{I_{C_o}}{y(\%)V_o.f_{sw}}}({\displaystyle \frac{G}{1+G}})$$

(28)

where $y(\%)V_o$ is the ripple of the output voltage and is usually chosen as 5–10% of the output voltage $\left(V_o\right)$. According to the above equations, the needed capacitance changes as the voltage gain changes. In reality, changing the capacitors in response to variations in voltage gain is not possible. Therefore, a worst-case scenario is selected while designing the capacitors.

4.5. Input Capacitor

The proposed CG-BBI also requires the input DC-link capacitor $C_{in}$, like traditional buck–boost inverters. The main objective of the input filter capacitor is to reduce the ripples on the input voltage and provide a stable DC input to the inverter. This capacitor also functions as an energy buffer, ensuring maximum power point tracking (MPPT) operation of a PV system [24]. The required capacitance can be calculated as

$$C_{in}={\displaystyle \frac{P_{pv}}{2\pi f.V_{in}.{\displaystyle \Delta }{V}_{in}}}$$

(29)

where $P_{pv}$ denotes the PV panel power, f is the line frequency, and ${\displaystyle \Delta }{V}_{in}$ represents the input voltage ripple, which are typically selected as 5–10% of the input voltage $\left(V_{in}\right)$.

5. Simulation Results and Loss Analysis of the CG-BBI

A simulation model for the proposed CG-BBI was built in PSIM to validate its operating principle. The passive circuit parameters of the CG-BBI were selected as $L_1=L_2=300$ $\mathsf{\mu }$H, $C=10$ $\mathsf{\mu }$F and $C_o=5$ $\mathsf{\mu }$F. The simulation results for both boost and buck operation of CG-BBI are presented in Figure 9 and Figure 10, respectively. For the boost operating mode of the proposed inverter, the input voltage of 100 V was chosen, whereas it was 200 V for buck operation. The output voltage was kept at a constant amplitude with an RMS value of approximately 110 $V_{rms}$. The simulation was performed at an output power of 500 W, with operating conditions set to a switching frequency of 50 kHz and a line frequency of 60 Hz.

Figure 9. Boost operating mode of CG-BBI. (a) Input and output voltages along with output current, (b) inductor current, (c) voltage stress on switches.

Figure 10. Buck operating mode of CG-BBI. (a) Input and output voltages along with output current, (b) inductor current, (c) voltage stress on switches.

Figure 9a illustrates the input voltage $\left(V_{in}\right)$, output voltage $\left(V_{out}\right)$, and output current $\left(i_{out}\right)$ for the boost operation. It can be observed that, for an input voltage of 100 V, the output reaches a peak of $155.5$ V. The total harmonic distortion (THD) measured in boost mode for a load of 500 W is about $2.9\%$ and is acceptable according to the IEEE standard 519 $(THD<5\%)$. Figure 9b shows the current on both the inductors, and the ripples on both the inductors are less than $25\%$ of the peak inductor current. The switches voltage stresses are represented in Figure 9c. The switches $(S_1,S_2)$ experience voltage stresses, determined by the combined value of the input voltage and peak of the output voltage. Switches $(S_3,S_4)$ are subjected to almost double the input voltage.

Figure 10a illustrates the CG-BBI functionality in buck operating mode, that is, when the desired output voltage is lower than the input voltage. In this case the peak voltage of $155.5$ V is achieved from a 200 V input. The THD measured in buck mode for a load of 500 W is about $2.2\%$ and is in the acceptable range of less than $5\%$ according to IEEE standard 519 [25]. Figure 10b shows the current through both the inductors. The ripples on the inductors are less than $25\%$ of the peak inductor current. The CG-BBI input and output voltages determine the voltage stress experienced by each switch. The value of the voltage stress on each switch in buck operating mode is greater than that in boost operating mode, as illustrated in Figure 10c.

The main losses in inverters can be broadly categorized into active and passive component losses. Losses associated with active components primarily include the switching and conduction losses of the power switches. In contrast, passive component losses arise from the switching and conduction losses of diodes, the core and winding losses of inductors, and the equivalent series resistance (ESR) of capacitors.

The switching losses are calculated using the data sheet switching energy parameters ($E_{\mathrm{on}}$ and $E_{\mathrm{off}}$) of the UF3CO6504T3S MOSFETs employed in the prototype. These energy values are directly extracted from the data sheet curves of “switching energy’’ versus “junction temperature,” provided for $V_{\mathrm{DS}}=400\mathrm{V}$, $I_{\mathrm{D}}=40\mathrm{A}$, and a junction temperature of 100 °C. Based on these parameters, the total switching loss of the proposed converter is evaluated using

$$P_{\mathrm{sw}}={\displaystyle \frac{1}{2}}{f}_{\mathrm{sw}}(E_{\mathrm{on}}+E_{\mathrm{off}})\left({\displaystyle \frac{V_{\mathrm{ds}}}{400}}\right)\left({\displaystyle \frac{I_{\mathrm{d}}}{40}}\right)$$

(30)

The conduction loss of the capacitor is given by

$$P_c=I_{c,\mathrm{rms}}^2·\mathrm{ESR}$$

(31)

where $\mathrm{ESR}$ is the equivalent series resistance, and $I_{c,\mathrm{rms}}$ is the RMS current flowing through the capacitor, expressed as

$$I_{c,\mathrm{rms}}=\sqrt{{\displaystyle \frac{1}{T}}{\int }_0^T{i}_c^2\left(t\right)dt}$$

(32)

where T denotes the time period of the line frequency. The core and winding losses of inductors are calculated using the relationships provided in [26]. Core loss may also be approximated from the manufacturer’s core loss chart. A commonly used expression for estimating core loss is

$$P_{\mathrm{core}}=K_{\mathrm{fe}}{A}_c{l}_m{(\Delta B)}^{\beta }$$

(33)

where $K_{\mathrm{fe}}$ is a proportionality constant dependent on the operating frequency, $A_c$ is the core cross-sectional area, $l_m$ is the mean magnetic path length, $\Delta B$ is the peak AC flux density, and $\beta$ is a material-dependent constant obtained from the data sheet Winding losses arise from the DC resistance of the coil as well as skin and proximity effects. The DC winding loss is calculated using

$$P_{\mathrm{winding}}=I_{w,\mathrm{rms}}^2{R}_{\mathrm{dc}}$$

(34)

where $I_{w,\mathrm{rms}}$ is the RMS winding current, and $R_{\mathrm{dc}}$ is the DC resistance of the inductor windings.

A detailed loss breakdown of the proposed inverter in both buck and boost operating modes at an output power of 500 W and a switching frequency of 50 kHz is provided in Table 1. The same loss analysis methodology is applied to calculate the efficiency across different output power levels for both modes. As shown in Figure 11, the proposed inverter achieves a peak efficiency of 96.46% in buck mode and 96.81% in boost mode at a switching frequency of 50 kHz and an output power of 400 W.

Table 1. Loss breakdown in buck and boost modes of the proposed inverter at 500 W.

Loss Element	Buck Mode	Boost Mode	Formulas
MOSFET (Switching Losses)	7.18 W	4.61 W	$P_{\mathrm{sw}}={\displaystyle \frac{1}{2}}{f}_{\mathrm{sw}}(E_{\mathrm{on}}+E_{\mathrm{off}})\left({\displaystyle \frac{V_{\mathrm{ds}}}{400}}\right)\left({\displaystyle \frac{I_{\mathrm{d}}}{40}}\right)$
MOSFET (Conduction Losses)	2.14 W	3.36 W	$P_{\mathrm{cond}}=I_{\mathrm{rms}}^2{R}_{\mathrm{DS}\left(\mathrm{on}\right)}$
Diode (Switching Losses)	1.8 W	1.8 W	$P_{\mathrm{d},\mathrm{sw}}={\displaystyle \frac{1}{2}}{E}_{\mathrm{rr}}{f}_{\mathrm{sw}}$
Diode Conduction Losses	2.94 W	4.48 W	$P_{\mathrm{d},\mathrm{cond}}=V_f{I}_d$
Capacitor ESR Losses	0.23 W	0.37 W	$P_{\mathrm{c}}=I_{\mathrm{c},\mathrm{rms}}^2\mathrm{ESR}$
Inductor Core + Copper Losses	3.8 W	4.1 W	$\begin{array}{cc}\hfill P_{\mathrm{core}}& =K_{\mathrm{fe}}{A}_c{l}_m{(\Delta B)}^{\beta }\hfill \\ \hfill P_{\mathrm{winding}}& =I_{\mathrm{w},\mathrm{rms}}^2{R}_{\mathrm{dc}}\hfill \end{array}$
Total Losses	18.1 W	18.72 W

Figure 11. Efficiency of the proposed inverter for different output powers in both buck and boost modes.

6. Experimental Results of CG-BBI

To validate the theoretical analysis and functionality of the CG-BBI, a 500-W MOSFET-based prototype was fabricated and tested in standalone mode at a switching frequency of 50 kHz. The prototype hardware is shown in Figure 12 and was tested for both buck and boost operating modes. The output voltage was kept constant for both the operating modes, having a peak amplitude of 155.5 V. A summary of the key electrical specifications of the proposed topology are presented in Table 2. The gate driving signals, required for the operation of the inverter, were generated using a TMS320F28379D digital signal processor (DSP).

Figure 12. Prototype of the proposed CG-BBI.

Table 2. Electrical specifications of components.

Parameters	Part Number/Value
Output power	500 W
Input voltage $V_{in}$	100–200 $V_{dc}$
Output voltage	155 $V_{peak}$, 110 $V_{rms}$
Switching frequency	50 kHz
MOSFETs $(S_1,S_2,S_3,S_4)$	UF3C065040T3S
Diodes $(D_1,D_2)$	SDUR3060W
Inductors $(L_1,L_2)$	300 $\mathsf{\mu }$H
Capacitors $(C,C_o)$	5 $\mathsf{\mu }$F, 10 $\mathsf{\mu }$F

The experimental results for CG-BBI in boost operating mode at an input voltage of 100 V are shown in Figure 13. Figure 13a shows the output voltage, input voltage, and output current. Figure 13b shows the $L_1$ and $L_2$ inductor current in boost operating mode. The voltage stresses experienced by the switches are shown in Figure 13c,d. $V_{S3}$ and $V_{S4}$ in the proposed CG-BBI are the voltage stresses on the unidirectional switches, that is, voltage across the MOSFETs’ drain terminal and the cathode of their respective diode connected in series. If reverse-blocking IGBTs are selected, then $V_{S3}$ and $V_{S4}$ in the proposed CG-BBI are the voltage stresses across the reverse-blocking IGBTs.

Figure 13. Experimental evaluation of the CG-BBI operating in boost mode: (a) input and output voltages with the output current; (b) current of inductors $L_1$, $L_2$; (c) voltage stress on switches $S_1$, $S_2$; (d) voltage stress on switches $S_3$, $S_4$.

Similarly, Figure 14 shows the experimental validation in buck operating mode, having an input voltage of 200 V. Figure 14a shows the output voltage, input voltage, and output current. Figure 14b shows the current for inductors $L_1$ and $L_2$ in buck operating mode. The voltage stress across the switches in buck operating mode is shown in Figure 14c,d, where $V_{S3}$ and $V_{S4}$ represent the voltage across the unidirectional switches, i.e., MOSFET with series reverse-blocking diode in this case.

Figure 14. Experimental evaluation of the CG-BBI operating in buck mode: (a) input and output voltages with the output current; (b) current for inductors $L_1$, $L_2$; (c) voltage stress on switches $S_1$, $S_2$; (d) voltage stress on switches $S_3$, $S_4$.

7. Comparative Study

Table 3 presents a comprehensive comparison of CG-BBI with several existing power conversion topologies. CG-BBI achieves a sinusoidal output voltage with an acceptable number of active and passive components. In particular, only four active switches are required for both the buck and boost modes of operation. The comparison considers key performance criteria that include the number of components, the number of input sources, the ability to eliminate leakage current, and support for a wide input voltage range. Among the examined topologies, CG-BBI consistently demonstrates fewer active components, making it a promising candidate for compact and efficient design.

Table 3. Comparison of the proposed CG-BBI with other buck–boost inverters.

Parameters	[27]	[28]	[29]	[30]	[31]	[32]	Proposed CG-BBI
Switches	6	4	4	3	4	5	4
Diodes	4	2	0	5	3	1	2
Inductors	2	1	1	3	3	1	2
Capacitors	1	3	1	7	4	2	2
Input Sources	One	One	One	One	One	One	One
Buck–Boost Functionality	Buck	Buck	Buck	Boost	Boost	Buck–boost	Buck–boost
Common Ground	No	Yes	Yes	Yes	Yes	yes	yes
Leakage Current	Low	Negligible	Negligible	Negligible	Negligible	Negligible	Negligible
Maximum Reported Efficiency	FB-CCCV-I: 98.65% @ 2500 W, 20 kHz FB-CCCV-II: 98.9% @ 2500 W, 20 kHz	97.4% @ 500 W, 24 kHz	-	95% @ 40 kHz	95.3% @ 650 W 20 kHz	96.82% @ 400 W 50 kHz	Buck Mode 96.46% @ 400 W 50 kHz Boost Mode 96.81% @ 400 W 50 kHz

The inverter topology reported in [27] maintains a constant common-mode voltage throughout a switching cycle, thereby mitigating the leakage current. However, its input voltage must be greater than the output, and needs a front-stage boost converter. Also, it has more high-frequency-switching active components and increased switching losses, and the diodes in the current path further increase the total loss. Unlike the other structures, the inverters in [28,29] have the same switch count as CG-BBI and eliminate leakage current. But, these inverters are also limited to buck operating mode and need an external boost stage, which increases the number of components count and complexity. Also, its reliance on a front-end boost converter compromises overall system efficiency, as the total efficiency is the product of both DC–DC and DC–AC conversion efficiencies.

Similarly, the inverter in [30] uses fewer active switches and requires a high step-up front-stage converter, leading to a significant increase in passive components and structural complexity. A quasi-single-stage common-ground inverter is presented in [31], utilizing four active switches, and effectively eliminates the leakage current while enabling voltage boosting. However, all the switches operate at higher switching frequencies during the negative cycle, resulting in increased switching losses. Moreover, larger numbers of diodes and switches are present in the conduction path during each switching cycle, further contributing to conduction losses. The inverter topology presented in [32] exhibits negligible leakage current and is capable of achieving a wide voltage range and high gain; however, it suffers from higher stresses on the active components.

Overall, the comparative study demonstrates that the proposed CG-BBI topology achieves a superior balance between topology complexity, leakage current mitigation, and width of voltage range. Unlike other solutions that rely on additional front-end converters or suffer from higher switching and conduction losses, CG-BBI provides an inherently compact and efficient architecture. Its versatility and simplicity make it an excellent choice for single-phase transformerless inverters in photovoltaic applications, where maximizing efficiency and reliability while reducing complexity are critical design objectives.

8. Conclusions

A novel single-stage, four-switch common-ground buck–boost inverter (CG-BBI) topology was proposed in this work. The topology provides both buck and boost operation without requiring an additional DC–DC converter or isolation transformer, while the common-ground configuration effectively suppresses the leakage current. The employed modulation strategy allows only two devices to operate at high switching frequency during each half cycle, resulting in significantly reduced overall switching losses and improved conversion efficiency. PSIM-based simulations and experimental results obtained from a laboratory-scale prototype demonstrate stable output voltage regulation at 110 Vrms in both buck and boost operating modes. Operation near the unity power factor confirms the suitability of the proposed inverter for grid-connected photovoltaic (PV) applications. By combining single-stage buck–boost functionality, leakage current suppression, efficient power conversion, and robust operation, the proposed CG-BBI presents a practical and compact solution for single-phase transformerless inverters, highlighting its potential for efficient and reliable PV system integration.