Open Circuit Fault Mitigation in a Nine-Level Modified Packed E-Cell Inverter

Abstract

Reliability of the multilevel inverters (MLIs) is one of the most important concerns in industrial applications, mainly due to the semiconductor devices. Whenever a fault occurs in one of the switches of the inverter, it leads to abnormal conditions and can also cause serious damage to the equipment connected to the multilevel inverter. In this paper, a recently proposed nine-level Packed-E-Cell (PEC) multilevel inverter topology is investigated for its fault-tolerant capability and improved reliability. The analysis is carried out for a reduced device multilevel inverter topology that, due to a lack of redundant states, cannot tolerate switch failures. The fault-tolerant (FT) topology provides additional redundant states in the switching sequence of the existing topology. The work in this paper presents Packed-E-Cell MLI modified for fault tolerance against single-switch open-circuit faults. The modified FT topology inherently achieves self-voltage balance in the DC-link capacitors. Nearest Level Control(NLC) is used as the modulation strategy for generating the desired switching pulses. Simulation results are obtained in MATLAB/Simulink for the conditions prior to the fault, during the fault and post fault, and results are discussed. Experimental verification of the modified FT topology is also performed, in order to validate its effectiveness.

1. Introduction

Multilevel inverters have lately gained popularity, a fact attributed to their ability to provide lower voltage stress across semiconductors, good electromagnetic compatibility, low dV/dt stress, fewer switching losses, and lower total harmonic distortion (THD) [1,2,3]. MLIs find applications in various fields, including renewable energy systems [4,5] static compensator [6] and High Voltage DC (HVDC) transmission systems [7,8].

However, in addition to the benefits, MLIs face certain challenges, including an increasing number of semiconductor switches, which makes the system more complicated, costlier, and less dependable overall. As a result, with a lower device count, developing a fault-tolerant topology becomes essential to lowering the chance of a failure occurrence. According to several research studies looking at industrial applications, semiconductors account for 21% of mistakes and solders account for 13% of overall failure in the converter system, accounting for 34% of total failure [9,10]. Figure 1 shows the contribution of different units to the failure of a converter system.

Figure 1. Distribution of failures in power devices [9].

There are two types of faults in semiconductor switching devices: open-circuit and short-circuit. An open-circuit fault can be caused by a gate driver malfunction, a momentary short circuit, or damage to any inner wire. The reason behind the short-circuit fault may be due to over-voltage, over-current and wrong gate signal [11]. In the case of short-circuit faults of the semiconductor switches, the removal becomes difficult, as it incorporates additional hardware circuits for fault detection and tolerance [12].

Several authors have suggested various methods to tolerate faults, thereby increasing the reliability of the converter system of the conventional MLI topologies such as Neutral Point Clamped (NPC) [13,14], Flying Capacitor (FC) [15,16] and Cascaded H-Bridge [17,18].

In [19], to improve the reliability of the CHB multilevel inverter, one additional leg (consisting of two semiconductor switches) and four triacs are utilized, although it is not economically feasible. In [20], a modified topology of [19] is presented, without using any additional leg and with four triacs. In [21], a switch is put between the DC sources and the load, although the fault in two switches is not taken into account. The authors in [22] discuss a Fault-Tolerant Hybrid Cascaded H-Bridge Multilevel Inverter, although the failure in DC-link capacitors causes discontinuity of operation.

Recently, some topologies for reduced device-MLIs with the ability to tolerate faults have been introduced [23]. The availability of redundant states, i.e., numerous switching states that can provide the same inverter output voltage levels, is the most significant need for fault-tolerant MLIs [24]. Whenever a fault occurs, the lack of redundant states can cause the malfunction or complete shutdown of the MLIs [25]. The problem with the reduced-device MLIs is that there is lack of redundant states and hence the probability of being fully fault-tolerant is very difficult. The reliability of the reduced-device MLIs can be increased by raising the number of redundant states and this is done by adding one or more power semiconductor devices in parallel to the existing devices [26].

In [12], the authors propose an open-circuit fault detection and elimination technique of a 3-level T-Type MLI where the fault is detected by sensing the capacitor voltage. This topology is not fully fault-tolerant, although the topology in [27] is fully fault-tolerant without any loss of levels in the output voltage, but has the drawback of more switching device and capacitor requirement. However, the FT topology in [27] does not need any external circuitry for the balancing of the capacitor voltage for the fault in the switch closer to the DC link; this cannot be tolerated, as it unbalances the capacitor voltage.

The fault diagnostic method can be categorized into two types: material redundancy and analytical redundancy [28,29]. The material redundancy technique entails having extra elements to replace the faulty components, allowing the system to isolate the fault and operate in faulty conditions. This procedure involves connecting an auxiliary branch or device across the converter or part of the converter, substituting the broken branch and allowing power to flow continuously [30]. The analytical redundancy method consists in the addition of a block in the control system capable of reconfiguring the output signals using the feedback from these signals [31].

In this paper, we have followed the material redundancy fault diagnostic method, where parallel switches are connected across the switches that cause shutdown of the system. A multilevel inverter design with nine levels in output voltage during normal conditions is discussed for use with single-switch open-circuit failures in the semiconductor switching devices. The concepts and the design are verified by simulating using MATLAB/Simulink followed by experimental verification.

The remainder of this paper is structured as follows: Section 2 discusses the existing MLI topology, and fault diagnosis is performed for every switch. The proposed fault-tolerant topology, as well as its operating principle are described in Section 3. The modulation strategy is discussed in Section 4, and the simulation results are shown in MATLAB/Simulink, followed by experimental validation and power loss analyses using PLECS in Section 5. Section 5 also compares the proposed fault-tolerant topology with other fault-tolerant topologies that have recently been presented. The work is brought to a conclusion in Section 6.

2. Existing Nine-Level MLI Topology

The existing nine-level Packed-E-Cell [32,33] inverter has six active bidirectional switches and two DC capacitors which are shunted by a four -quadrant switch to form an E-cell. The DC capacitors are balanced using the redundant charging/discharging states by properly designing the corresponding PEC9 switching states. Due to the horizontal placement of the shunted capacitors, both the capacitors are charged and discharged simultaneously with the redundant states; hence, only the auxiliary DC-link voltage has to be measured and maintained at half of the DC source voltage, and this inherently balances the voltage across the DC capacitors to one-fourth of the DC source voltage. Along with a reduced component count, the E-cell also helps the proposed topology to attain multi ac terminal operation, i.e., if there is a fault in the four-quadrant switch, the PEC9 MLI topology continues to operate as five-level, thereby increasing the reliability.

The existing nine-level PEC MLI is composed of six active unidirectional switches S₁, S₂, S₃, S₄, S₅ and S₆; one four-quadrant switch S₇, a single DC source V_dc and two capacitors C₁ and C₂, as shown in Figure 2. The four-quadrant switch is connected between the midpoint of the two capacitors C₁ and C₂ and the inverter ac terminal point. A single auxiliary DC-link is created by placing the two capacitors in horizontal position, so that both the capacitors are accordingly charged and discharged. This provides a synchronism between both the capacitors during charging and discharging. Due to the presence of the four-quadrant switch, the E-cell provides multiple voltage levels, i.e., five, seven or nine at the output, without changing the structure.

Figure 2. Existing configuration of nine-level MLI [32].

There are 24 switching states for the existing nine level PEC9 MLI for both directions of current denoted by µ_i (I = 1, 2,…, 24), as shown in Table 1. During the operation, all the switches, capacitors and diodes are assumed to be ideal, and the effect of parasitic components is not included. The conducting paths for load current Io greater than zero are shown as dark lines for each mode of operation, in Figure 3.

Table 1. Switching States of the nine-level PEC9 MLI.

Modes	S1	S2	S3	S4	S5	S6	S7	Io	C1	C2	Output Voltage Magnitude	Output Level
µ1	1	0	0	0	1	1	0	>0	-	-	Vdc	+E
µ2	1	0	0	0	1	0	1	>0	↓	-	Vdc − V1	+3E/4
µ3	1	0	1	0	1	0	0	>0	↓	↓	Vdc − V1 − V2	+E/2
µ4	1	1	0	0	0	1	0	>0	↑	↑	V1 + V2	+E/2
µ5	1	1	0	0	0	0	1	>0	-	↑	V2	+E/4
µ6	0	0	0	1	1	1	0	>0	-	-	0	0
µ7	1	1	1	0	0	0	0	>0	-	-	0	0
µ8	0	0	0	1	1	0	1	>0	↓	-	−V1	−E/4
µ9	0	1	0	1	0	1	0	>0	↑	↑	−Vdc + V1 + V2	−E/2
µ10	0	0	1	1	1	0	0	>0	↓	↓	−V1 − V2	−E/2
µ11	0	1	0	1	0	0	1	>0	-	↑	−Vdc + V2	−3E/4
µ12	0	1	1	1	0	0	0	>0	-	-	Vdc	−E
µ13	1	0	0	0	1	1	0	<0	-	-	Vdc	+E
µ14	1	0	0	0	1	0	1	<0	↑	-	Vdc − V1	+3E/4
µ15	1	0	1	0	1	0	0	<0	↑	↑	Vdc − V1 − V2	+E/2
µ16	1	1	0	0	0	1	0	<0	↓	↓	V1 + V2	+E/2
µ17	1	1	0	0	0	0	1	<0	-	↓	V2	+E/4
µ18	0	0	0	1	1	1	0	<0	-	-	0	0
µ19	1	1	1	0	0	0	0	<0	-	-	0	0
µ20	0	0	0	1	1	0	1	<0	↑	-	−V1	−E/4
µ21	0	1	0	1	0	1	0	<0	↓	↓	−Vdc + V1 + V2	−E/2
µ22	0	0	1	1	1	0	0	<0	↑	↑	−V1 − V2	−E/2
µ23	0	1	0	1	0	0	1	<0	-	↓	−Vdc + V2	−3E/4
µ24	0	1	1	1	0	0	0	<0	-	-	Vdc	−E

‘↑’: Capacitors charging, ‘↓’: Capacitors discharging, ‘-’: No effect on capacitors.

Figure 3. Conduction paths of existing 9-level PEC9 topology.

The existing PEC9 MLI is investigated for open-circuit faults as shown in Table 2. If one of the switches of either S₂ or S₅ undergoes failure (open-circuit fault), existing PEC9 topology can produce three-level output voltage. If either of the switches S₃ or S₆ fails to operate, then the operation can continue with seven-level output voltage. For failure in the four-quadrant switch S₇, the existing topology can operate with five levels in the output voltage.

Table 2. Operating modes for single-switch open-circuit fault in existing PEC9 MLI.

Failed Switch	Operating Modes Available	Operation Level
S1	µ6, µ8, µ9, µ10, µ11, µ12	SHUT DOWN
S2	µ1, µ2, µ3, µ6, µ8, µ10	3 Levels
S3	µ1, µ2, µ4, µ5, µ6, µ8, µ9, µ11	7 Levels
S4	µ1, µ2, µ3, µ4, µ5, µ7	SHUT DOWN
S5	µ4, µ5, µ7, µ9, µ11, µ12	3 Levels
S6	µ2, µ3, µ5, µ7, µ8, µ10, µ11, µ12	7 Levels
S7	µ1, µ3, µ4, µ6, µ7, µ9, µ10, µ12	5 Levels

On the other hand, if switch S₁ or S₄ undergoes an OC fault, then no operating MLI modes will allow the synthesis of output voltage across the load, and the corresponding condition will be equivalent to a shutdown.

3. Modified Nine-Level PEC9 FT MLI

The modified topology (PEC9 FT) is achieved by adding two more switches S₈ and S₉ to the existing single-phase PEC9 topology. The added switches in parallel to S₁ and S₄ provide additional redundant states so that an alternative path is available when either of the switches S₁ and S₄ undergoes open-circuit fault, and the topology will not undergo complete shutdown. The modified topology is shown in Figure 4.

Figure 4. The Modified PEC9 FT MLI Topology.

With this modification, there is an increase in the number of redundant switching states. There is one output voltage level produced by each switching state in the Modified PEC9 FT MLI topology, and when all such levels are combined a nine-level periodic voltage is achieved at the output. Table 3 shows all the switching states of PEC9FT-MLI, along with the outputs. Table 3 shows that if there is an open-switch fault in any of the switches S₂, S₃, S₅, S₆ and S₇, there is still conversion of power from source to load; however, with reduced output voltage levels of seven, five or three, according to the switch location. However, if the open-switch fault occurs in switches S₁ or S₄ or any other switch pair, the post-fault output has the same magnitude and levels as it had in the pre-fault condition. This certainly improves the reliability when critical loads are supplied.

Table 3. Operating modes of FT-MLI topology for PEC9 FT MLI.

Modes	Prioritization Number	S1	S2	S3	S4	S5	S6	S7	S8	S9	Output Voltage Magnitude	Output Level
µ1	A11	1	0	0	0	1	1	0	0	0	+Vdc	+E
	A12	0	0	0	0	1	1	0	1	0	+Vdc
µ2	A21	1	0	0	0	1	0	1	0	0	+Vdc − V1	+3E/4
	A22	0	0	0	0	1	0	1	1	0	+Vdc − V1
µ3	A31	1	0	1	0	1	0	0	0	0	+Vdc − V1 − V2	+E/2
	A32	1	1	0	0	0	1	0	0	0	+V1 + V2
	A33	0	0	1	0	1	0	0	1	0	+Vdc − V1 − V2
	A34	0	1	0	0	0	1	0	1	0	+V1 + V2
µ4	A41	1	1	0	0	0	0	1	0	0	+V2	+E/4
	A42	0	1	0	0	0	0	1	1	0	+V2
µ5	A51	0	0	0	1	1	1	0	0	0	0	0
	A52	1	1	1	0	0	0	0	0	0	0
	A53	0	0	0	1	1	1	0	0	1	0
	A54	0	1	1	0	0	0	0	1	0	0
µ6	A61	0	0	0	1	1	0	1	0	0	−V1	−E/4
	A62	0	0	0	0	1	0	1	0	1	−V1
µ7	A71	0	1	0	1	0	1	0	0	0	−Vdc + V1 + V2	−E/2
	A72	0	0	1	1	1	0	0	0	0	−V1 − V2
	A73	0	1	0	0	0	1	0	0	1	−Vdc + V1 + V2
	A74	0	0	1	0	1	0	0	0	1	−V1 − V2
µ8	A81	0	1	0	1	0	0	1	0	0	−Vdc + V2	−3E/4
	A82	0	1	0	0	0	0	1	0	1	−Vdc + V2
µ9	A91	0	1	1	1	0	0	0	0	0	−Vdc	−E
	A92	0	1	1	0	0	0	0	0	1	−Vdc

4. Modulation Strategy

In this paper, optimized nearest level control (ONLC) is used for generating the control signals. ONLC is one of the subsets of the nearest level control scheme (NLC) [34], which is a fundamental frequency switching scheme. NLC is generally of three types: conventional NLC, modified NLC and optimized NLC. Amongst the three, ONLC is preferred as the value of THD is less in ONLC compared with conventional and modified NLCs for both a low number of levels and a high number of levels. In the optimized NLC method, the comparison value is taken as 0.4 instead of the half-integer value 0.5 (i.e., 1.5 is rounded off as 2 and 1.3 is rounded off as 1). The DC loss error between two levels is always maintained as 0.4 V_dc. The comparison of the sinusoidal reference signal V_ref and the carrier signals is shown in Figure 5, and the block diagram of the nearest level prediction is shown in Figure 6. The carrier constant is set to 0.4 in the optimized NLC technique, which minimizes THD while also increasing the RMS value of output voltage and current. The three important parameters considered to select the optimum constant value are as follows: the presence of odd harmonics content in output voltage, various constant carrier values, and output RMS voltage value. The RMS value is higher in the nearest value at 0.1 and decreases gradually at point 1.0, which gives a low RMS voltage value. But in the case of THD, it is variable, with different nearest values. For ‘N’ level output voltage, the total number of carrier signals (B₁ to B_n) required are as follows:

B1	B2	B3	B4	……	Bn−1	Bn
0.4	1 + 0.4	2 + 0.4	3 + 0.4	……	(n − 2) + 0.4	(n − 1) + 0.4

where n = (N − 1)/2

Figure 5. Level generation method of optimized nearest level control.

Figure 6. Block diagram of optimized NLC.

The switching angle for the optimized NLC can be found using the equation below:

$${\varnothing }_{\mathrm{p}}{=\sin }^{-1}\left[\right(\mathrm{p} - 0.6)/\mathrm{n}]$$

where p = 1, 2, 3, …, (N − 1)/2.

5. Results and Discussion

5.1. Simulation Results

The open loop simulation of the modified proposed FT MLI is performed using the optimized nearest level control (ONLC) technique with MATLAB/Simulink software. Simulation was carried out to obtain the waveforms of single-phase output voltage, current through the load, and THD in the output voltage for R-L Load. The component parameters used in the simulation of existing PEC9 MLI are listed in Table 4.

Table 4. Simulation parameters for the proposed FT MLI.

Parameters	Attributes
DC Voltage Source 1	100 Volts
DC Voltage Source 2	50 Volts
Switches (S1 to S9)	IGBT/Diode
Switching frequency	50 Hz
Fundamental frequency	50 Hz
Load (R, L)	100 Ω, 250 mH
Capacitors (C1 and C2)	2500 µf each
Modulation Index	1

Figure 7a–g shows the waveform for the voltage at the output, current through the load and the voltage across capacitors under pre-fault condition (t < 0.04 s), during-fault condition (0.04 < t < 0.08 s) and post-fault condition (t > 0.08 s). When an open-circuit fault occurs in switches S₁, S₄, S₈, and S₉ at t = 0.04 s, the post-fault output voltage levels remain the same as that of a healthy condition at nine with a peak value of 100 V, and the load current post fault remains at the same peak magnitude as in normal conditions. The proposed design reduces the post-fault output voltage levels from nine to seven for an open-circuit fault in the switches S₃ and S₆, as well as reducing the peak magnitude of the load current. When the four-quadrant switch S₇ experiences an open-circuit fault, the output voltage levels drop from nine to five, along with the reduction in amplitude of the load current. In the case of an open-circuit fault in switches S₂ and S₅, the post-fault voltage has three levels, with a peak value of 50 V along with a balanced current with reduced peak value. The simulation results show that the proposed fault-tolerant topology has the benefit of allowing power conversion to continue even if one of the switches has an open-circuit failure.

Figure 7. Waveforms obtained from the simulation for the voltage at the output, current through the load and voltage across the capacitor for pre-fault, faulty and post-fault conditions in: (a) S₁ or S₈, (b) S₂, (c) S₃, (d) S₄ or S₉ (e) S₅ (f) S₆ and (g) S₇.

The voltage across the capacitors C₁ and C₂ as shown in Figure 7 remains constant, with a value of Vdc/4, i.e., 25 volts for the given supply of 100 Volts.

Figure 8 presents the simulation results of the voltage THD after the fault has been cleared. Figure 8a shows the output voltage THD profile after the faults in switches S₁, S₄, S₈ or S₉ have been cleared. Similarly, Figure 8b–d shows the THD profile for the output voltage for faults in switches S₃ or S₆, S₇, and S₂ or S₅, respectively.

Figure 8. Simulation results of Voltage THD profiles after clearing of faults in (a) S₁, S₄, S₈ or S₉ (b) S₃ or S₆ (c) S₇, and (d) S₂ or S₅.

5.2. Experimental Results

The above-mentioned simulation results for the suggested fault-tolerant multilevel inverter design were verified using an experimental prototype, as shown in Figure 9. Table 5 shows the parameters used for obtaining the experimental results.

Figure 9. Experimental setup for the proposed fault-tolerant topology.

Table 5. Parameters of experimental validation.

Parameters	Attributes
DC source 1	120 V
DC source 2	60 V
Capacitors (C1 and C2)	2500 µF each
Switches	IGBT FGA25N120
Load (purely resistive)	200 Ω
DSP Kit	C2000, Texas instruments
Optocoupler	TLP 250 (TOSHIBA)

The pre-fault, during-fault, and post-fault waveforms for output voltage, load current, and capacitor voltages are shown in Figure 10. For open-circuit faults in switches S₁, S₄, S₈ or S₉ the post-fault output voltage contains nine levels, and the peak is maintained at 120 V, as shown in Figure 10a,d. For open-circuit faults in S₂ or S₅, the output voltage levels reduce to three, and peak output voltage reduces to 60 Volts, as shown in Figure 10b,e. For open-circuit faults in switches S₃ and S₆, the post-fault output voltage reduces to seven levels and a peak value of 90 V, as shown in Figure 10c,f. For an open-switch fault in S₇ the post-fault output voltages are reduced to five, with a peak value of 120 V, as shown in Figure 10g. Figure 10h shows the voltage across each capacitor maintained at 30 V for the pre-fault, during-fault and post-fault conditions for any of the switches.

Figure 10. Experimental results: voltage across the output and current through the load waveform showing pre-fault, during-fault and post-fault conditions for switches; (a) S₁ or S₈ (b) S₂, (c) S₃, (d) S₄ or S₈, (e) S₅ and (f) S₆; (g) S₇ Open, (h) voltage across capacitors for fault across each switch.

Figure 11 represents the experimental validation of the output voltage THD after the fault has been cleared. Figure 11a shows the output voltage THD profile after the faults in switches S₁, S₄, S₈ or S₉ have been cleared. Similarly Figure 11b–d shows the THD profile for the output voltage for faults in switches S₃ or S₆, S₇, and S₂ or S₅, respectively.

Figure 11. Experimental verification of Voltage THD profiles for clearing of faults in: (a) S₁, S₄, S₈ or S₉, (b) S₃ or S₆, (c) S₇ and (d) S₂ or S₅.

5.3. Power Loss Analysis

PLECS (Piecewise Linear Electrical Circuit Simulation) software was used to assess power and efficiency losses in the overall sense of the recommended topology. Thermal modeling in the software was used to calculate precise conduction and switching losses for all switches, as well as losses across the capacitors. Infineon’s IGBT switch IGA30N60H3 was used for this work. Figure 12 depicts the IGBT’s turn ON, turn OFF, and conduction loss models. Switching losses (P_S) and conduction losses (P_C) of all semiconductor devices, as well as ripple loss (P_R) of capacitors, were considered in this study.

Figure 12. Loss model for (a) turn ON, (b) turn OFF, and (c) conduction loss for IGBT IGA30N60H3.

5.3.1. Switching Losses

Switching losses occurred at the instant the switches were turned on or off. Taking into account the approximation in a linear sense between the current and the voltage of switches throughout the switching period, the following equations may be written for the kth switch:

Loss of power during switching ON:

$${\mathrm{P}}_{\mathrm{S}, \mathrm{on}, \mathrm{k}}=\mathrm{f}\underset{0}{\overset{{\mathrm{t}}_{\mathrm{on}}}{{\displaystyle \int }}}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)\mathrm{dt}$$

(1)

$$=\mathrm{f}\underset{0}{\overset{{\mathrm{t}}_{\mathrm{on}}}{{\displaystyle \int }}}\left(\frac{{\mathrm{V}}_{\mathrm{S},\mathrm{k}}}{{\mathrm{t}}_{\mathrm{on}}}\mathrm{t}\right)\left(-\frac{{\mathrm{I}}_{\mathrm{k}}}{{\mathrm{t}}_{\mathrm{on}}}\left(\mathrm{t}-{\mathrm{t}}_{\mathrm{on}}\right)\right)\mathrm{dt}=\frac{1}{6}{ \mathrm{f} \mathrm{V}}_{\mathrm{S},\mathrm{k}}{\mathrm{I}}_{\mathrm{k}}{\mathrm{t}}_{\mathrm{on}}$$

(2)

Loss of power during switching OFF:

$${\mathrm{P}}_{\mathrm{S},\mathrm{off},\mathrm{k}}=\mathrm{f}\underset{0}{\overset{{\mathrm{t}}_{\mathrm{off}}}{{\displaystyle \int }}}\mathrm{v}\left(\mathrm{t}\right)\mathrm{i}\left(\mathrm{t}\right)\mathrm{dt}$$

(3)

$$=\mathrm{f}\underset{0}{\overset{{\mathrm{t}}_{\mathrm{off}}}{{\displaystyle \int }}}\left(\frac{{\mathrm{V}}_{\mathrm{S},\mathrm{k}}}{{\mathrm{t}}_{\mathrm{off}}}\mathrm{t}\right)\left(-\frac{{\mathrm{I}}_{\mathrm{k}}{}^{\prime }}{{\mathrm{t}}_{\mathrm{off}}}\left(\mathrm{t}-{\mathrm{t}}_{\mathrm{off}}\right)\right)\mathrm{dt}=\frac{1}{6}{ \mathrm{f} \mathrm{V}}_{\mathrm{S},\mathrm{k}}{\mathrm{I}}_{\mathrm{k}}{}^{\prime }{\mathrm{t}}_{\mathrm{off}}$$

(4)

where ${\mathrm{I}}_{\mathrm{k}}$ and ${\mathrm{I}}_{\mathrm{k}}{}^{\prime }$ denote currents across the kth switch when it has been turned ON, and prior to turning it OFF, respectively, f is the frequency of switching, and ${\mathrm{V}}_{\mathrm{S},\mathrm{k}}$ denotes the voltage for the OFF-state of the kth switch. For calculating the loss in switching in total, the ON (${\mathrm{N}}_{\mathrm{on}}$) and the OFF number of switching states (${\mathrm{N}}_{\mathrm{off}}$) for each cycle are multiplied with (1) and (2) following (3):

$$P_S={\displaystyle \sum }_{k=1}^{12}({\displaystyle \sum }_{m=1}^{N_{on}}{\mathrm{P}}_{\mathrm{S},\mathrm{on},\mathrm{km}}+{\displaystyle \sum }_{\mathrm{m}=1}^{{\mathrm{N}}_{\mathrm{off}}}{\mathrm{P}}_{\mathrm{S},\mathrm{off},\mathrm{km}})$$

(5)

5.3.2. Conduction Losses (P_C)

To quantify losses in conduction in the steady-state condition, the internal resistance of each component, such as the semiconductor devices and capacitors, had to be addressed. The capacitors were expected to be identical. Because the condition of resistive loading is believed to be the worst-case scenario in the study of loss of power for the SCMLIs, the results were collected using the PLECS software for a resistive load.

5.3.3. Capacitor Ripple Losses (P_R)

Ripple losses occur because of the difference between the input voltage (V_in) and the voltage across the capacitors (V_cj (j = 1, 2, 3, 4)), when the capacitors are connected in parallel. It is assumed that the capacitor is fully charged to V_in during the charging state.

The capacitor ripple voltage is taken as:

$${\mathsf{\Delta }\mathrm{V}}_{\mathrm{Cj}}=\frac{1}{{\mathrm{C}}_{\mathrm{j}}}{{\displaystyle \int }}_{{\mathrm{t}}^{\prime }}^{\mathrm{t}}{\mathrm{i}}_{{\mathrm{C}}_{\mathrm{j}}}\left(\mathrm{t}\right)\mathrm{dt} \mathrm{for} \mathrm{j}=1, 2, 3, 4$$

(6)

Here, ${\mathrm{i}}_{{\mathrm{C}}_{\mathrm{j}}}$ denotes passing current of the jth capacitor. The discharging period is $[{\mathrm{t}}^{\prime }-\mathrm{t}]$. Thus, the total ripple loss in the duration of the output waveform cycle is given by (7).

$${\mathrm{P}}_{\mathrm{R}}=\frac{\mathrm{f}}{2}{\displaystyle \sum }_{\mathrm{j}=1}^4{\mathrm{C}}_{\mathrm{j}}{ \mathsf{\Delta }\mathrm{V}}_{\mathrm{Cj}}{}^2$$

(7)

It is clear from (6) and (7) that ripple loss is in inverse proportion to capacitance. As a result, more capacitance resulted in reduced ripple loss and, as a result, increased efficiency. The efficiency of the overall proposed inverter is given by (8).

$$\mathsf{\eta }=\frac{{\mathrm{P}}_{\mathrm{o}}}{{\mathrm{P}}_{\mathrm{o}}+{\mathrm{P}}_{\mathrm{S}}+{\mathrm{P}}_{\mathrm{C}}+{\mathrm{P}}_{\mathrm{R}}}$$

(8)

Figure 13 shows the efficiency vs load power factor curve for the proposed fault-tolerant MLI for various modulation indices. For both setups in which capacitor ripple loss was ignored, maximum efficiency was around 98.7%, and a 100-watt output power was attained. In its place, capacitor ESR loss (conduction loss owing to internal resistance of the capacitors (here 0.1 ohm)) was used.

Figure 13. Efficiency versus load power factor curve of the proposed fault-tolerant MLI.

5.4. Comparison with Recent Topologies

This section compares the proposed fault-tolerant multilevel inverter with recently developed fault-tolerant topologies that produce nine levels as output during the pre-fault/normal conditions. The suggested fault-tolerant topology is compared, based on the number of DC sources, capacitors, switches, and bidirectional switches. The comparison is made in tabular form as shown in Table 6. In terms of the number of IGBT switches and DC sources, the suggested fault-tolerant topology is more cost-effective than other compared topologies.

Table 6. Comparison of various parameters of the proposed FT MLI topology with other recently developed topologies.

	Proposed Topology	[35]	[36]	[37]	[38]
DC sources	2	2	4	2	4
Capacitor	2	2	0	2	0
Switches	9	13	10	16	12
4-quadrant switches	1	0	2	0	0
Output voltage levels	9	9	9	9	9
Fault-tolerant	✓	✓	✓	✓	✓

‘✓’:parameter is met.

6. Conclusions

This paper presents a multilevel inverter topology that is fault-tolerant; its comparison with other recently proposed fault-tolerant multilevel inverters proves its capability. The proposed topology includes redundant circuit paths that help give output even if the power switches are open-circuited, making it entirely fault-tolerant. The capacitors’ self-voltage balancing is maintained inherently under pre-fault, fault, and post-fault conditions. The optimized nearest level control technique is used for simulation and the results obtained from the experiments validate its adaptability against open-circuit faults. Simulation and experimental verification are used to verify the practicality of the proposed topology.