A Two-Stage DC/DC Isolated High-Voltage Converter with Zero-Voltage Switching and Zero-Current Switching Applied in Electronic Power Conditioners

Abstract

This paper presents a two-stage DC/DC converter with high efficiency utilized in an electronic power conditioner (EPC), which is widely applicable in satellite communications, etc. The galvanically isolated converter contains two cascaded converters: a buck converter, which is a pre-regulator operating under a closed-loop condition, and a push–pull converter, which is intended to boost the input voltage, operating under an open-loop condition. In the push–pull converter, the power switches, including the main switches and the rectifier diodes, operate under zero-voltage switching (ZVS) and zero-current switching (ZCS) at both switch off and switch on, which minimizes the switching loss. Furthermore, all of the parasitic parameters, such as the parasitic capacitance, leakage inductance, and magnetizing inductance of the main transformer, are fully utilized. Therefore, the presented topology benefits from fewer semiconductors but higher efficiency. The proposed topology produces less EMI noise because of ZVS and ZCS processes whose fundamental switching frequency interference is relatively low. The presented converter achieves a wide bus voltage regulation range in a satellite because of the pre-regulation of the buck cell. The theoretical analysis is validated by a prototype and its experimental results. The maximum efficiency of the converter can be up to 94.5%, and the high-voltage output is 7000 V.

1. Introduction

Microwave signals are amplified using space traveling wave tube amplifiers [1] (STWTA) as an important component of satellite systems. Typically, a TWTA comprises a traveling wave tube [2] (TWT) and an electronic power conditioner [3] (EPC). An interaction between a beam wave and an electromagnetic wave contributes to the amplification of microwave power when a TWT is utilized. Additionally, the EPC converts the satellite bus voltage [4] (typically ranging from 30 to 100 V DC) to the required electrode voltage (ranging from a few kV to a few hundred kV DC) through high-frequency power converters. Since the primary power conversion is the most significant aspect of the EPC, it must be considered when designing the circuit [5].

Presently, the main power conversion is categorized into two major types: single-stage power conversion and two-stage power conversion. The greatest advantage of single-stage conversion is its simplicity, and it is used in applications such as phase-shifted full-bridges [6,7,8], asymmetric half-bridges [9,10,11], three-transistor push–pulls [12], and so on. However, all of these single-stage topologies suffer from the same issue: stringent input voltage and load quality requirements. The application of a single-stage power conversion cannot satisfy the requirements of satellites. Consequently, two-stage power converters are increasingly utilized in the EPC. There are two types of topologies that have become dominant applications: boost and full-bridge [13], and buck and phase-shifted full-bridge [14]. In boost and full-bridge topologies, the control loop response time is very slow, and the surge current is high [15]. Furthermore, the complexity of the control systems of buck and phase-shifted full-bridge converters negatively impacts their reliability, and this topology cannot work in ZVS or ZCS when the load is not heavy [16]. Two other two-stage cascade transformations, flyback and asymmetrical half-bridge, and forward and push–pull, are rarely used due to their poor efficiency. In these two-stage topologies, forward and push–pull have the highest efficiency, which is 91.47% [17].

The statistics indicate that STWTAs consume 70% to 90% of DC consumption. Additionally, they contribute to 35% of the total weight in radar systems [18]. Therefore, power conversion topology must be continuously enhanced to meet the requirements of higher efficiency [19] and the miniaturization of on-board equipment.

Buck and push–pull, and boost and push–pull are two different topologies, as shown in Figure 1. Based on the system requirement, if EPC has some malfunctions or failures, it cannot affect other modules in the satellite. If in the fault mode, the power switch (the red one) in Figure 1a can be turned off and thus can prevent affecting the bus voltage in the satellite. However, in Figure 1b, the power switch (the red one), when turned off, cannot prevent affecting the bus voltage, and it must include an additional protective circuit. Moreover, if ZVS and ZCS need to be realized in a boost and push–pull topology, extra inductance and capacitance (the blue ones) need to be added to the circuit, which increases the complexity of the circuit.

Figure 1. The two different topologies of a two-stage converter: (a) The buck and push–pull topology, and (b) the boost and push–pull topology.

Motivated by the above analysis and practical application, this paper presents a two-stage converter topology with a high efficiency: buck and push–pull, where the push–pull converter is implemented in ZVS and ZCS. The buck regulator is used to pre-regulate the voltage in hard switching.

In addition, the high-voltage output is achieved through a soft-switching push–pull converter. The block diagram of this two-stage converter is shown in Figure 2. Closed-loop feedback is applied in the buck regulator to provide stable voltage for the push–pull circuit, and the push–pull circuit works in an open-loop state with a high output voltage after a doubler rectifier circuit.

Figure 2. The block diagram of the two-stage converter.

This two-stage DC/DC converter topology enjoys the following advantages:

(1) It makes full use of the parasitic capacitance and inductance that participate in the resonant switching, without adding additional components, in order to achieve soft switching and thereby increase efficiency.

(2) The power switches of the push–pull converter and the diodes of the second side of the rectifier can be operated to provide zero current and zero voltage both at the time of switching off and switching on, resulting in increased efficiency and reduced voltage and current limitations.

(3) Dual interleaved drivers are used in the buck circuit, so the magnetic reset process does not need to be considered for duty cycles that exceed 50%, and the design of the drive transformer is more compact than that of a single-drive method, resulting in a significantly broader range of applications.

(4) This topology produces less EMI noise due to the shapes of the current and voltage waveforms, which contain very low magnitudes of fundamental switching frequency interference.

(5) The cost is lower as a result of the low-current/voltage limitation (also a result of point 1), and it is simple to implement overload limitation without causing component damage.

(6) The control scheme can be simpler than full-bridge or other topologies if the switches in both the buck and push–pull operate on the same frequency.

This paper begins with Section 2, which examines operational modes. Section 3 introduces the key parameter utilized in the topology design. Section 4 presents the experimental results from the laboratory prototype. Section 5 compares buck and push–pull converters with other topologies and discusses potential future research enhancements. Section 6 concludes the paper.

2. The Proposed Converter

2.1. Description of the Topology

This paper proposes a two-stage DC/DC converter consisting of a buck regulator and a push–pull converter. The schematic circuit is depicted in Figure 3.

Figure 3. The DC/DC converter circuit diagram.

$Q_3$, $Q_4$, $D_1$, $L_b$, and $C_b$ constitute the interleaved dual-driver buck regulator. They are power switches, the fly-wheel diode, inductance, and capacitance, respectively. Equivalent primary leakage inductance, $L_p$, helps achieve the soft-switching with $C_b$, as will be discussed later. The resonant frequency is $f=\frac{1}{2\pi \sqrt{L_p{C}_b}}$. $Q_1$ and $Q_2$ are power switches used in push–pull converter. The transformer, T, provides galvanic isolation between the input and output sides and is employed to generate high voltage together with voltage-doubler circuits, which include voltage-doubler rectifier diodes and capacitance: $D_{O1}$, $D_{O2}$, $C_{O1}$, and $C_{O2}$. Winding capacitance, $C_{p1}$ and $C_{p2}$, cannot be ignored because the converter is applied in a high-voltage situation. $C_{Q1}$ and $C_{Q2}$ denote the sums of the parasitic output capacitance of the semiconductor and external parallel capacitance. $D_{Q1}$ and $D_{Q2}$ are body diodes.

The following considerations are made to make the analysis simpler:

(1) Assume that all components are ideal;

(2) Transformer turns ratio, $N$:

$$N_1=N_2=\frac{N_3}{N}$$

(1)

$$L_{m1}=L_{m2}=L_m=\frac{L_{m3}}{N^2}$$

(2)

where $L_m$ is much larger than $L_p$;

(3) The sum of semiconductor parasitic output capacitance and external parallel capacitance:

$$C_{Q1}=C_{Q2}=C_Q$$

(3)

(4) Voltage-doubler rectifier capacitance

$$C_{O1}=C_{O2}$$

(4)

and the voltage of both $C_{O1}$ and $C_{O2}$ are $\frac{U_O}{2}$.

2.2. Modes of Operation

Throughout the process of a completed switching cycle, from $t_0$~$t_8$, the converter operates in eight modes, as in the following exposition. The key waveforms are exhibited in Figure 4.

Figure 4. The key waveforms in a complete switching cycle.

Mode I [$t_0$, $t_1$]: The equivalent circuit of mode I is depicted in Figure 5. The switch $Q_2$ turns off at the instant of $t_0$, the capacitance $C_{Q2}$ starts to charge, and the voltage increases. On the other hand, $C_{Q1}$ is discharging simultaneously. Furthermore, the charging capacity of $C_{Q2}$ is equal to the discharging capacity of $C_{Q1}$ due to the coupling effect and the balance of the transformer. There is no energy exchange in the transformer. The leakage inductance $L_p$ resonates with $C_{Q1}$ and $C_{Q2}$. The winding capacitance of transformer $C_{p1}$ starts charging and $C_{p2}$ discharges. In addition, $I_{Cp1}=I_{Cp2}$. When the voltage of $C_{p1}$ reaches $-V_b$, $V_{Cp2}$ reaches $V_b$ and this mode comes to the end.

Figure 5. The equivalent circuit of mode I.

Since there is no energy exchange between the primary side and the secondary side in mode I, the voltage across $C_b$ can be considered constant, and the equivalent circuit of mode I can be depicted in Figure 6.

Figure 6. Approximated equivalent circuit for no energy exchanging between the primary side and secondary side.

Therefore:

$$\{\begin{array}{c}V-L_{m1}\frac{d{i}_1}{dt}+M\frac{d{i}_2}{dt}-\frac{1}{C_{Q1}}{{\displaystyle \int }}^{}{i}_{1}dt=0\\ V-L_{m2}\frac{d{i}_2}{dt}-M\frac{d{i}_1}{dt}-\frac{1}{C_{Q2}}{{\displaystyle \int }}^{}{i}_{2}dt=0\end{array}$$

(5)

As $L_{m1}=L_{m2}=L_m$, $C_{Q1}=C_{Q2}=C_Q$, neglecting the effect of the leakage inductance, it is $M=L_m$, so that yields:

$$i_1=-i_2$$

(6)

Combining (5) and (6):

$$V-2L_m\frac{d{i}_1}{dt}-\frac{1}{C_Q}{{\displaystyle \int }}^{}{i}_{1}dt=0$$

(7)

The solution of (7) is:

$$\begin{gathered} i_1(t)=\frac{I_m}{\sqrt{2}cos\psi }cos\left(\omega t+\psi \right) \\ \omega =\frac{1}{\sqrt{2L_m{C}_Q}} \\ {I}_m=\frac{1}{2}\frac{V}{L_m}{T}_{ON} \end{gathered}$$

(8)

Mode II [$t_1$,$t_2$]: The equivalent circuit of mode II is depicted in Figure 7. In this mode, the voltage of winding capacitance $C_{p1}$ remains $-V_b$, and $V_{Cp2}$ remains $V_b$. $C_{Q2}$ keeps charging, and the voltage increases. Since $C_{Q1}$ is discharging, the voltage decreases as well. A small level of high-frequency oscillated current flows through the second-side rectifier diode $D_{O2}$. When the voltage of $V_{Q1}$ drops to 0 and $V_{Q2}$ rises to $2V_b$, $C_{Q1}$ and $C_{Q2}$ complete discharging and charging and mode II finishes.

Figure 7. Equivalent circuit of mode II.

Mode III [$t_2$,$t_3$]: The equivalent circuit of mode III is depicted in Figure 8.When the resonance on the primary side of the transformer finishes, the current through $C_{Q1}$, $C_{Q2}$, $C_{p1}$, and $C_{p2}$ returns to 0, but the voltage is still the same, respectively. $I_{Q1}$ and $I_{Lp}$ go to 0 gradually so that the MOSFET $Q_1$ operates in ZCS when it turns on. From the moment of $t_2$, the current through $D_{O2}$ returns to 0, and $D_{O2}$ operates in ZCS in the stage of energy exchange between the primary and secondary sides.

Figure 8. Equivalent circuit of mode III.

Mode IV [$t_3$,$t_4$]: As $V_{Q1}$ had already been 0 at $t_3$, the MOSFET $Q_1$ turns on in ZVS. Mode IV is the major process that transfers energy from the primary side to the secondary side. No more current flows in $C_{Q1}$, $C_{Q2}$, $C_{p1}$, or $C_{p2}$, but the voltage on them is invariable. Energy transmits from the push–pull side to the high-voltage side through a high-frequency transformer on the coupling of magnetizing inductance $L_{m1}$. The current in $Q_1$ increases gradually in sinusoidal form from 0 to the maximum (about 10 A), then decreases to 0 later again, the current in $D_{O2}$ charges the voltage-doubling capacitance in the same form and synchronously offers energy for the load. In the current circumstance $t_4$, the MOSFET $Q_1$ operates in ZCS when it turns off, and mode IV comes to an end.

The equivalent circuit of Figure 9 can be depicted in Figure 10 during the time that switch $Q_1$ is on. Normally, the equivalent output capacitance, $C_O^{\prime }$, is much smaller than the buck capacitance, $C_b$, so the main resonance can be located in the loop consisting of $C_b$ and leakage inductance, $L_p$. According to KCL,

$$I_{Lb}=I_{Cb}+I_{Lp}$$

(9)

Hence,

$$\frac{I_{Lb}}{C_b}=\frac{I_{Lp}}{C_b}+L_P\frac{d_{I_{Lp}}^2}{d{t}^2}$$

(10)

whose solution is:

$$\begin{gathered} I_{Lp}(t)=I_{Lb}-I_{Lb0}cos(\omega t+\phi ) \\ \omega =\frac{1}{\sqrt{L_p{C}_b}} \end{gathered}$$

(11)

According to KVL,

$$V_{Cb}-V_{Lp}=V_{Lm1}$$

(12)

that is,

$$V_{Cb}(t)-V_{Lm1}=L_p\frac{di}{dt}$$

(13)

Applying (11) into (13):

$$\begin{gathered} I_{Lb}-I_{Lb0}cos\phi =0 \\ \frac{V_{Cb}(t)-V_{Lm1}}{L_p{I}_{Lb0}}=\omega sin\phi \end{gathered}$$

(14)

whose solution is:

$$\begin{gathered} tg\phi =\frac{V_{Cb}(t3)-V_{Lm1}}{L_p{I}_{Lb}\omega } \\ {I}_{Lb0}=\frac{I_{Lb}}{cos\phi } \end{gathered}$$

(15)

Until the moment $t_4$, the first half of the switching cycle comes to an end, and the circuit turns into the second half of the cycle. Based on symmetry, modes V~VIII are in one-to-one correspondence with modes I~IV.

Figure 9. Equivalent circuit of mode IV.

Figure 10. When the switch $Q_1$ turns on, this circuit is equivalent to the circuit in Figure 9.

3. Key Parameter Design

Taking input voltage $V_{in}=30\mathrm{V}\mathrm{DC}$, output voltage $V_O=7000\mathrm{V}\mathrm{DC}$, load power $P_O=130\mathrm{W}$, and switch frequency $f=100\mathrm{kHz}$ as an example, the key parameter design of the circuit is as follows.

3.1. Buck Inductance, $L_b$

Buck inductance can be calculated as:

$$L_b=\frac{V_b\left(1-D\right)}{K_{ind}{I}_{b}f}$$

(16)

where $V_b$ is the voltage of buck output (V), in this case, $V_b=22\mathrm{V}$; $D$ is the duty cycle (%) in the interleaved dual-driver, $D=\frac{1}{2}\frac{V_b}{V_{in}}=36.67\%$; $K_{ind}$ is the ripple current rate, $K_{ind}=0.3$, generally; $I_b$ is the current of the buck output (A), and $I_b=\frac{P_o}{V_b}=5.91\mathrm{A}$. Hence, $L_b=78.6\mathrm{uH}$.

3.2. Buck Capacitance, $C_b$

Buck capacitance can be calculated as:

$$C_b=\frac{1}{f^2}\frac{1}{4{\pi }^2{L}_p}=4.2 \mathrm{uF}$$

(17)

where $L_p=0.6\mathrm{uH}$ is the leakage inductance of the transformer and $f=100\mathrm{kHz}$ is the switching frequency.

3.3. Power Transformer Parameter

The number of turns on the primary side of the transformer is:

$$N_p=\frac{V_{in}}{K_{f}f{B}_W{A}_e}$$

(18)

where $K_f=4.0$ is the waveform factor of the square wave; $f=100\mathrm{kHz}$ is the switching frequency; the type of magnetic core is TPW33-UYF36 series; $B_w=150\mathrm{mT}$ is the magnetic flux density; and $A_e=130.98{\mathrm{mm}}^2$ is the effective cross areas of the core. Therefore, $N_p=4.16$. Taking an integer value, that is $N_1=N_2=5$.

The number of turns on the secondary side of the transformer can be calculated by

$$N_s=\frac{N_p{V}_o}{2V_{in}}=583.4$$

(19)

In this case, $N_3=584$.

The general design rule of the power transformer parameter is that the equivalent primary leakage inductance, $L_p$, and the winding capacitance of the transformer, $C_p$, should be suitable. The practical measurements of these parasitic parameters: $L_p=0.6 \mathrm{uH}$ and $C_p=9 \mathrm{nF}$. If $L_p$ is different from the design value, a switch frequency of $f=100\mathrm{kHz}$ can be achieved by adjusting the value of the buck capacitance, $C_b$, according to $f=\frac{1}{2\pi \sqrt{L_p{C}_b}}$. If the sum value of $C_p$, $C_Q$, and the external parallel capacitance is about 10 nF, ZVS and ZCS are realized in the two-stage converter.

3.4. Power Loss of Transformer

Allowable loss can be calculated as:

$$\begin{array}{ll}{P}_{fe}=P_{\Sigma }-P_{cu}=& \left(\frac{P_o}{\eta }-P_o\right)-\left(P_{pcu}+P_{scu}\right)=\left(\frac{P_o}{\eta }-P_o\right)-\left(I_p^2{R}_p+I_o^2{R}_s\right)\\ & =\left(\frac{P_o}{\eta }-P_o\right)-\left[{\left(\frac{P_o}{V_{in}\eta }\right)}^2\left(MLT\right)\left(N_p\right)\frac{\mathsf{\mu }\Omega }{\mathrm{cm}}{10}^{-6}+{\left(\frac{P_o}{U_o}\right)}^2\left(MLT\right)\left(N_s\right)\frac{\mathsf{\mu }\Omega }{\mathrm{cm}}{10}^{-6}\right]=3.02\mathrm{W}\end{array}$$

(20)

where $P_{\Sigma }$ is the total loss (W), $P_{cu}$ is the total copper loss (W), $P_{pcu}$ is the copper loss of the primary side (W), $P_{scu}$ is the copper loss of the secondary side (W), and $MLT$ is the average length of a single turn (cm).

The actual loss can be calculated as:

$$\acute{P_{fe}}=\frac{W}{kg}\times W_{tfe}=2.63\mathrm{W}$$

(21)

where $W_{tfe}$ is the weight of allowable iron loss (kg).

Obviously,

$$\acute{P_{fe}}<P_{fe}$$

(22)

The loss in the unit area can be calculated as:

$$\mathsf{\Phi }=\frac{\acute{P_{fe}}+P_{cu}}{A_s}=0.025\mathrm{W}/{\mathrm{cm}}^2$$

(23)

The temperature increase in the transformer is less than 20 °C in this case. The coiling method of the transformer additionally obtains a smaller distributed capacitance in layer coiling mode than in slot coiling mode, which has just a couple of nF.

3.5. Interleaved Dual-Driver Isolated Transformer

Buck circuits use interleaved dual drivers that require the support of an isolated driver transformer. The leakage inductance and power loss are reduced as a result of the use of the RM5 series of ferrite magnet cores and the “hamburger” coiling method, in which the primary side coil is wrapped by two secondary side coils. The calculation of drive transformer turns is identical to that of power transformer turns.

$$N_p=N_{s1}=N_{s2}=54$$

(24)

4. Experimental Validation

As shown in Figure 11, a laboratory prototype of the EPC was fabricated to verify the ZVS and ZCS in the two-stage DC/DC converter, along with other characteristics. In the converter, there are four power switches: two switches are used in the buck regulator and another two switches are used in the push–pull circuit. The driver transformer is used to isolate the drive signals because the source electrodes of power switches in the buck circuit connect to the non-zero level. The inductances include one buck inductance and two filter inductances in input voltage. CPLD is used to generate control signals and control the sequence relationships.

Figure 11. Experimental EPC in the laboratory.

Dual interleaved drivers are used in the buck circuit, and the driving frequency of the buck regulator is consistent with that of the push–pull circuit. The single-channel drive frequency is 45.2 kHz, and the equivalent switching frequency of the dual interleaved drivers is 90.4 kHz. The drive signals are applied to the power switches of the buck circuit through the drive chip and the isolated drive transformer. Table 1 outlines the parameters.

Table 1. Parameters of the converter.

Parameter	Value
Input voltage, $V_{in}$	30 V DC
Output voltage,	7000 V DC
Rated power, $P_O$	130 W
Buck voltage, $V_b$	22 V
Buck inductance, $L_b$	75 uH
Buck capacitance, $C_b$	4.4 uF
Output capacitance, $C_O$	47 uF
Voltage-doubling rectifier capacitances, $C_{o1}$ and $C_{o2}$	2.2 uF
Power MOSFETs, $Q_1$ to $Q_4$	IRFB4127
Power diode, $D_1$	DSA30C150

Figure 12 shows that ZVS and ZCS can be realized in both the on and off states. The waveforms of both $V_{DS\left(Q1\right)}$ and $V_{DS\left(Q2\right)}$ are approximately trapezoidal, and $I_{Q1}$ and $I_{Q2}$ are sinusoidal. There is no voltage spike or overshooting current. The peak voltage of the switches:

$$V_{p-p}=2V_b=46\mathrm{V}$$

(25)

Figure 12. Steady-state waveforms of the converter.

The voltage stress is independent of the load. The peak current of the switches:

$$I_{p-p}=\frac{P_o}{V_b}\left(1+\frac{1}{cos\left\{{\tan }^{-1}\left[2\pi f^2{\left(\frac{T_{off}-T_{on}}{2}\right)}^2\right]\right\}}\right)=12.64 \mathrm{A}$$

(26)

where $f$ is the operating frequency of dual interleaved drivers, which is 90.4 kHz, $T_{off}$ is the off time of the switches, which is 14.9 us, while $T_{on}$ is the on time of the switches, which is 7.38 us.

In the same load condition (130 W), the parasitic capacitance and leakage inductance are used to form the resonant tank. Moreover, another two-stage converter, boost and push–pull, can realize ZVS but cannot realize ZCS. The drain-source voltage also increases and reaches 70 V, as shown in Figure 13.

Figure 13. The waveform of another two-stage converter, boost and push–pull. The load is 130 W.

According to Figure 14, the buck voltage is about 22 V in the two-stage converter.

Figure 14. The waveform of buck voltage, $V_b$.

The bus voltage in satellites always varies, but the target of high efficiency never changes. Figure 15 illustrates the variation in efficiency in different input voltages, where Figure 15a illustrates the efficiency when the output power is 130 W, while Figure 15b shows the efficiency when the output power is 75 W. The lower input voltage or the heavier load leads to a higher duty cycle for the buck converter. As a result, the efficiency of the DC/DC converter increases as well. The highest efficiency can be up to 95%.

Figure 15. The efficiencies of the converter in different input voltages for different loads: (a) The efficiencies for 130 W; (b) The efficiencies for 75 W.

Figure 16 shows the test result of the conducted emission of this two-stage converter in different switching conditions, where Figure 16a presents the test result when the converter worked in hard switching, while Figure 16b shows the result when the converter worked in soft switching. According to the test results of conducted emission, when the converter worked in ZVS and ZCS, the interference of conduction emission was smaller than that in hard switching.

Figure 16. The test result of conducted emission in different switching conditions: (a) The two-stage converter in hard switching; (b) The two-stage converter in soft switching.

5. Discussion

According to the experiment results, the buck and push–pull converter works in ZVS and ZCS in both the off and on states. Another two-stage converter, boost and push–pull, can realize ZVS but not ZCS under the same load condition (130 W), and the drain-source voltage also increases.

Compared with a unipolar topology, this two-stage topology can operate steadily in ZVS and ZCS over a wider input voltage range from 25 V to 40 V. When the input voltage ranges from 24 V to 30 V, unipolar topologies, such as three-transistor push–pull, can realize ZVS and ZCS [12].

Another common two-stage converter is forward and push–pull. The forward and push–pull converter can realize ZCS or zero-current transition (ZCT) using resonant components on the secondary side of the transformer. ZCS causes high current stress, and its efficiency is low. ZCT operates in quasi-resonance mode, which may result in low current stress; the efficiency is relatively higher; and the maximum efficiency is 91.47% when operating at full load [17]. Compared with forward and push–pull, the buck and push–pull converter can achieve up to 94.5% efficiency.

However, the two-stage converter has many aspects that need to be improved. In subsequent work, the planar transformer will be considered for a further reduction in volume, and the lower ripple of the output voltage needs to be researched continuously.

6. Conclusions

In this paper, a two-stage DC/DC converter, buck and push–pull, was proposed. The proposed power converter was studied based on circuit analysis. In addition, a prototype was built, and the theoretical analysis was validated by the experimental results. The proposed two-stage converter enjoys the following advantages:

(1) All parasitic parameters, including the leakage inductance, magnetizing inductance, and parasitic capacitance, are fully utilized in the proposed two-stage power converter. Only an external resonant capacitance is required for the resonant tank. Therefore, fewer components are needed.

(2) In addition, all power switches, including the main switches and the rectifier diodes, operate under ZVS and ZCS. As a result, the switching loss is minimized, which contributes to the increase in the switching frequency and efficiency. Experimental results show that the efficiency can reach 94.5%.

(3) Furthermore, the EMI issue is improved due to the soft switching advantages, which was validated by the experimental results.

In conclusion, a two-stage power converter was proposed, where the first stage is a buck converter and the second stage is a resonant push–pull converter. The working principles and the calculations of the main parameters were researched. The theoretical analysis was validated by a prototype. The experimental results show that the proposed topology is suitable for high-voltage, high-efficiency applications.