# A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility

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## Abstract

**:**

## 1. Introduction

## 2. Topology and Operation of Proposed Hybrid DC–DC Converter

_{1}) and the power switch T, the rest of the circuit is connected precisely in parallel with each other. Hence, the output side two capacitors (C

_{1}and C

_{3}) are placed across the load. This hybrid structure increases the voltage gain by complementing the benefits of boost and Cuk converters. The converter provides continuous current mode operation with the help of a single power switch, which provides less voltage stress on the controlled switch and diodes.

#### Operation of Hybrid DC–DC Converter

_{1}, C

_{2}and C

_{3}) and inductors (L

_{1}and L

_{2}) charging and discharging analysis derivations were considered as follows. The two assumptions were taken for this analysis: (1) all the components are ideal; (2) the converter works under continuous conduction. Figure 3a illustrates the continuous conduction operating mode waveforms of the proposed converter. This advanced hybrid DC–DC converter mode operation has three modes of operation.

- Mode-I [t
_{a}–t_{b}], presented in Figure 2a. During mode-1, when t = t_{a}, the power switch T is turned ON and inductors (L_{1}and L_{2}) are charging until t_{b}. In the same interval, the capacitor C_{2}is discharging through T, and inductor L_{2}as the diodes (D_{1}and D_{2}) are blocking concerning V_{C1}and V_{C2}. - Mode-II [t
_{b}–t_{c}], illustrated in Figure 2b. During mode-1, when t = t_{b}, the power switch T is in the OFF state. Now the capacitor C_{1}voltage (V_{C1}) is higher than V_{C2}. Hence, after t_{b}interval, the C_{2}is charging and inductors L_{1}and L_{2}are discharging. It is happening throughout t_{b}to t_{c.}In the course of this period, diode D_{2}is continuously conducting since diode D_{1}is still in reverse bias. - Mode-III [t
_{c}–t_{d}], presented in Figure 2c. During this mode, the power switch T remains OFF as well as the V_{C1}is equal or lesser than V_{C2}. Here, both the inductors L_{1}and L_{2}are discharging, and C_{1}and C_{2}are charging via L_{1}. Hence the diode D_{1}and D_{2}are conducting and delivering the current to load.

**Figure 2.**Modes of operation of the proposed hybrid DC-to-DC converter: (

**a**) Mode-I [t

_{a}–t

_{b}]; (

**b**) Mode-II [t

_{b}–t

_{c}]; (

**c**) Mode-III [t

_{c}–t

_{d}].

**Figure 3.**(

**a**) Mode diagram of the proposed circuit; (

**b**) voltage gain versus duty ratio for boost, Cuk and proposed hybrid converter.

_{1}value was chosen with minimal current ripple ∆

_{iL}. The inductor current, i

_{L}for the proposed converter is supplied from either a PV or DC source (V

_{PV}or V

_{in}). When the converter receives a supply voltage from the input source, the converter power switch T is turned ON, and inductor current i

_{L1}is derived as follows. Applying Kirchhoff’s voltage law in mode-I [t

_{a}–t

_{b}], the capacitors current i

_{C1}and i

_{C2}are derived as

_{b}–t

_{c}], when the power switch T is in OFF, the coil transfers energy to the capacitors C

_{1}and C

_{3}. As a result, from loop 1 and loop 2, it can verify that

_{C1}and i

_{C2}are derived as follows,

_{C(T)}= V

_{C(0)}. Hence, the average value of the current capacitors is null. Also, the inductor coils average voltage is zero, since ${v}_{L}\left(t\right)=L\frac{d{i}_{L}\left(t\right)}{dt}$. The currents in the inductors and voltage in the capacitors tend to be approximately constant. The power switch is in the ON state for a percentage of the period (δT) and OFF during the next state (δT-T). Here, T is the total switching time. Therefore, the average value inductor voltage V

_{L1}and capacitor’s current i

_{C1}are illustrated in Figure 4 and Figure 7.

_{C1}

_{2}voltage is illustrated in Figure 5, and inductor average voltage value is

_{3}can be written as

_{3}charge and discharge current is shown in Figure 6. Here the capacitor current average value observed is zero, and the average current in the inductor is similar to the average output current, as the inductor tends to retain that average value.

_{0}= i

_{l2}

_{1}current (i

_{C1}) is displayed in Figure 7. From the capacitor current interval zero to δT and δ to T time, the i

_{C1}is calculated as

_{1}current is calculated as

_{2}current is calculated as

## 3. Scaling Converter Components Design

_{1}and L

_{2}) and capacitors (C

_{1,}C

_{2}and C

_{3}), are calculated for maximum values as the power switch T should support both the converter voltage and current.

#### 3.1. Design of Inductors

_{1}and L

_{2}) values calculation and current limitation analysis are observed by precise variation concerning the average value shown in Figure 8. The differential equation of inductor voltage V

_{L}is shown as

_{L}nearly constant, the current equation inductor is calculated as follows

#### 3.2. Design of Capacitors

_{1}, C

_{2}and C

_{3}are given below. The changing and discharging variation around the average value is shown in Figure 9.

_{1}, the current is given by:

_{c}= δT, C

_{1}is

_{2}is given by

_{c}= δT

_{3}, the current does not show instantaneous values and is nearly constant during the switching state. The behavior of capacitor C

_{3}is opposite capacitors C

_{1}and C

_{2}. When controlling the power semiconductor switch for the driving load variation, capacitor charge ∆Q is related to the inductor current ∆i

_{L2}/2 and time is taken T/2.

_{1}and C

_{3}values are deliberate in this section. The calculation is computed by including the sudden change in drive load resistance. Output voltage in the dynamic operating region is determined using the equivalent circuit (Figure 10 and Figure 11), assuming that the current passes zero to its steady-state value, ∆t

_{1}, the settling time of the current in the inductor L

_{1}.

_{1}is calculated using Equation (37)

_{1}value needs to calculate, in detail, from the response of i

_{LI}(s), which displays the input current of the response when rapid changes occur in output current i

_{o}(s). At time ∆

_{t2}, the current flow through the capacitor C

_{3}is calculated as

_{1}) and the power switch T, the rest of the proposed converter circuit elements are connected precisely in parallel with each other and on the output side, two capacitors (C

_{1}and C

_{3}) are placed across the load. Therefore, the proposed converter increases the voltage gain by combining the benefits of boost and Cuk converters.

#### 3.3. Small Signal Analysis of Hybrid DC–DC Converter

_{C1}and V

_{C2}, the voltage gain converter is calculated as

_{L1}/R

_{0}= r

_{L2}/R

_{0}.

_{L1/}R

_{0}= 0), where losses need to be introduced in the circuit (the gain for unit value goes to zero, as expected) and other operating conditions r

_{L1}/R

_{0}= r

_{L2}/R

_{0}= 0.0001 to 0.76, where near 0.76 duty cycle, the converter gain approaches six times boosting (V

_{0}= 6V

_{in}).

#### 3.4. Analysis of Losses

_{1}and L

_{2}are denoted from internal resistors r

_{L1}and r

_{L2}, respectively. Thus, the losses in r

_{L1}

#### 3.5. Conduction Losses in the Diodes

_{2,}resulting in the same results for this diode

## 4. Design Procedure

- The input power P
_{in}= 150 W, for V_{in}= 24 V, I_{in}= 6.2 A; - Power of the converter, P
_{i}= 150 W; - Input voltage converter V
_{in}= 24 V; - Duty cycle is fixed as δ = 0.8;
- The converter output voltage, V
_{o}= 104 V; - The output current and inductor current were expected to be I
_{0}= 1.11 A and I_{L1}= 4.25 A, respectively; - The capacitor C
_{1}and C_{3}voltages were calculated as V_{C1}= 110 V and V_{C3}= 104 V; - The general typical value sizing of capacitor C
_{1}, C_{3}and L_{1}, L_{2}was calculated as ∆i_{L1}= 10% I_{L1}, hence for L_{1}= 1 mH, the change in this was ∆i_{L1}= 0.425 A. The same changes can be seen for ∆i_{L2}= 10% I_{L2}, L_{2}= 1 mH and ∆i_{L2}= 0.14 A; - When the change in the capacitor ∆V
_{C1}was 1% V_{C1}, the capacitor C_{1}value was 100 μF and ∆V_{C1}= 1.10 V. Similarly, for ∆V_{C2}= 1% V_{C2}, C_{2}= 100 μF, ∆V_{C2}= 1.04V and ∆V_{C3}= 1% V_{C3}, C_{3}= 2 μF,∆V_{C3}= 0.08 V; - For the power semiconductor switch, the maximum open-circuit voltage was Vs
_{max}= 100 V, Vs_{max}= 95 V; - Diodes D
_{1}and D_{2}, Vs_{max}= 100 V, Vs_{max}= 95 V.

_{1}and D

_{2}can ensure a voltage of 100V, which ensures the safety factor of the converter. The converter can support a maximum current of six amps. When using six amps, the current safety factor is reduced to 60%–65%. Hence, the semiconductor must be selected to withstand the converter to provide maximum currents and voltages with a safety factor around 50%. The n-type reinforcing MOSFET is better chosen for providing the safety factor, and the proposed converter design uses the same [35]. The diodes (D

_{1}and D

_{2}), and MOSFET switching losses and conduction losses were calculated and given in Equations (61)–(73).

_{1}and D

_{2}:

_{1}and D

_{2}:

_{i}= input power and ∑P

_{T}= Total losses (P

_{Diode2 Con.Losses}+ P

_{Diode2 Con.Losses}+ P

_{MOSFET switching loss}+ P

_{MOSFET Conduction Loss}).

## 5. Simulation Results

_{in}) = 24 V, maximum duty cycle δ = 0.8 and switching frequency f

_{s}= 10 kHz. The converter input and output inductors were L

_{1}= 1 mH and L

_{2}= 1 mH receptivity. The capacitors were C

_{1}= 100 μF, C

_{2}= 100 μF and C

_{3}= 2 μF. Figure 14, Figure 15, Figure 16 and Figure 17 show the proposed converter simulation results for 10 kHz switching frequency and 80% duty cycle, and the results confirm the theoretical values. The converter duty cycle was fixed to be equal to or less than 0.8 to minimize the conduction losses. From Figure 14, when the converter duty cycle was fixed at 0.8 with 24V input voltage, the converter delivered an output voltage of 124 V (5.166 times higher than the input voltage). During the continuous conduction mode, the inductance L1 current was limited within the saturation limit in the range of 3 to 4.5 A and maintained the converter input current. Figure 15 displays the input current, as well as voltage across the power switches, and Figure 17 shows D

_{1}and D

_{2}voltages, V

_{D1}and V

_{D2,}respectively, during the switching period. From the results, it could be seen that during the time of switching, the switches (MOSFET and diode) were maintained with their maximum allowable voltage as 100 V. It was verified that the voltage across the switches was less than that of the converter. From the i

_{L2}and V

_{D2}simulation results, it can be seen that the proposed converter maintains a continuous current capability. Figure 16 shows the simulation waveforms for the inductor current i

_{L1}and inductor current i

_{L2}. From this waveform, it is seen that the inductors were charging uniformly and delivering the current in the continuous conduction. Figure 17 illustrates the voltage across the power diode, V

_{D1}and V

_{D2}. When the duty cycle was reduced to 0.6, the converter performance, switching reliability and continuous current capability were linear. Hence, the proposed converter has a wide range of controllability with a controlled degree of freedom to avail wider voltage outputs. The simulation was also performed in transient conditions (changing load and sudden change in the duty cycle). During this transient period, the output voltage and current through i

_{L1}changed with a small transient period and after reaching the continuous conduction and maintaining the constant output voltage.

## 6. Experimental Results

_{1}current saturation limit range of 3 to 4.5 A, as depicted in Figure 22. Hence, the power switch was secured against the high rising current by maintaining the converter input current inductance L

_{1}current saturation limit, which ensures the converter reliability against the input source. Similarly, from Figure 23 and Figure 24, during the time of switching, the MOSFET and diode were maintained with their maximum allowable voltage as 100 V, which was smaller than the converter output voltage (102 V). Here, during the switching period, the voltage across the main power switch was 100 V, and diode D

_{1}and D

_{2}were equal to V

_{D1}= 100 V and V

_{D2}= 95 V, respectively. During the entire mode of operation, the inductor current i

_{L1}and i

_{L2}maintained the identical current profile, which maintains the voltage balance between C

_{1}and C

_{2}. Figure 25 shows the experimental waveform of the input inductor current, i

_{L1}and voltage across i

_{D2}the power switch for input voltage 24 V and 0.8 duty cycle.

_{L1}and preserved in the converter in continuous conduction.

_{1}, D

_{2}and MOSFET) switching losses were calculated as 0.4 W, 0.5 W and 1.2 W using equations (61)–(74). Hence, the total switching losses for the converter was 2.1 W. Similarly, the conduction of the power switches and other circuit parameters losses were observed. In the overall power distribution losses, the MOSFET switching loss and conduction loss alone are about 52%. As presented in Figure 26b, the I

^{2}R losses in the MOSFET, diode and the snubber circuitry losses were accounted for as significant losses. Nevertheless, the proposed converter voltage stress reduction helps to choose the lower voltage-rating switch, and hence conduction losses are expected to reduce.

#### Key Performance Comparison

## 7. Conclusions

## Author Contributions

## Conflicts of Interest

## References

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**Figure 14.**Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (

**a**) input voltage waveform (voltage scale: 1 V/div and t: 20 μs/div) and (

**b**) input voltage waveform (voltage scale 50 V/div and t: 20 μs/div).

**Figure 15.**Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (

**a**) input current waveform (current scale: 0.5 A/div and t: 20 μs/div) and (

**b**) voltage across the power switch waveform (voltage scale 50 V/div and t: 20 μs/div).

**Figure 16.**Simulation waveforms for input voltage 24 V DC and 0.8 duty cycle; (

**a**) inductor current i

_{L1}waveform (current scale: 0.5 A/div and t: 20 μs/div) and (

**b**) inductor current i

_{L2}waveform (current scale: 0.5 A V/div and t: 20 μs/div).

**Figure 17.**Simulation waveforms for input voltage 24V DC and 0.8 duty cycle; (

**a**) voltage across the power diode, V

_{D1}waveform (voltage scale: 50 V/div and t: 20 μs/div) and (

**b**) voltage across the power diode, V

_{D2}waveform (voltage scale: 50 V/div and t: 20 μs/div).

**Figure 21.**The experimental waveform of input voltage and output voltage for input voltage 24 V and 0.8 duty cycle.

**Figure 22.**The experimental waveform of input current and output voltage for input voltage 24 V and 0.8 duty cycle.

**Figure 23.**The experimental waveform of input current and voltage across the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 24.**The experimental waveform of the input inductor current, i

_{L1}and voltage across i

_{D1}the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 25.**The experimental waveform of the input inductor current, i

_{L1}and voltage across i

_{D2}the power switch for input voltage 24 V and 0.8 duty cycle.

**Figure 26.**(

**a**) Theoretical and experimental results comparison. (

**b**) Experimental power loss distribution operating at rated condition (duty ratio from 0.8).

Components | Parameter |
---|---|

Input power P_{input} | 150 W |

Input voltage V_{in} | 24 V |

Output power P_{0} | 112 W |

Switching frequency f_{s} | 10 KHz |

Power MOSFET | SiHB30N60E |

Diode D_{1} and D_{2} | VS-15EWX06FN-M3 |

Inductance L_{1} and L_{2} | 1 mH |

Capacitor C_{1},C_{2} and C_{3} | 100 μF, 100 μF and 2 μF |

The output of Diode V_{D1} and V_{D2} | 100 V and 95 V |

Output Capacitor V_{C1},V_{C2} and V_{C3} | 104 V, 110 V and 8 V |

Similar Converter Topology | Converter [39] | Converter [9] | Converter [30] | Converter [40] | Converter [36] | Proposed Converter |
---|---|---|---|---|---|---|

Switches used | 1 | 2 | 1 | 1 | 1 | 1 |

Diodes used | 5 | 2 | 2 | 3 | 1 | 2 |

No. of Inductors used | 3 | 2 | 2 | 3 | 2 | 2 |

No. of capacitors used | 3 | 2 | 3 | 3 | 3 | 3 |

Continuous input current | Yes | No | Yes | Yes | No | Yes |

Voltage gain, V_{O} | $\frac{{\left(\delta \right)}^{2}}{{\left(1-\delta \right)}^{2}}\text{}\mathrm{Vin}$ | $\frac{2\left(1+\delta \right)}{\left(1-\delta \right)}\text{}\mathrm{Vin}$ | $\frac{1}{1-\delta}\text{}\mathrm{Vin}$ | $\frac{\delta}{{\left(1-\delta \right)}^{2}}\text{}\mathrm{Vin}$ | $\frac{2\delta}{\left(1-\delta \right)}\text{}\mathrm{Vin}$ | ${V}_{O}=\frac{1+\delta}{1-\delta}{V}_{PV}$ |

Efficiency | 91% | 90% | 91% | 90% | 92% | 92.2% |

The voltage stress on the active switch | Moderate | Less | High | Less | High | Moderate |

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Karthikeyan, M.; Elavarasu, R.; Ramesh, P.; Bharatiraja, C.; Sanjeevikumar, P.; Mihet-Popa, L.; Mitolo, M.
A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility. *Energies* **2020**, *13*, 2312.
https://doi.org/10.3390/en13092312

**AMA Style**

Karthikeyan M, Elavarasu R, Ramesh P, Bharatiraja C, Sanjeevikumar P, Mihet-Popa L, Mitolo M.
A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility. *Energies*. 2020; 13(9):2312.
https://doi.org/10.3390/en13092312

**Chicago/Turabian Style**

Karthikeyan, M., R. Elavarasu, P. Ramesh, C. Bharatiraja, P. Sanjeevikumar, Lucian Mihet-Popa, and Massimo Mitolo.
2020. "A Hybridization of Cuk and Boost Converter Using Single Switch with Higher Voltage Gain Compatibility" *Energies* 13, no. 9: 2312.
https://doi.org/10.3390/en13092312