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Energies 2017, 10(5), 715;

A SVPWM to Eliminate Common-Mode Voltage for Multilevel Inverters

School of automation, Guangdong University of Technology, 510006 Guangzhou, China
School of Electrical and Information Engineering, Changsha University of Science and Technology, 410004 Changsha, China
Author to whom correspondence should be addressed.
Academic Editor: Gabriele Grandi
Received: 5 April 2017 / Revised: 25 April 2017 / Accepted: 2 May 2017 / Published: 18 May 2017
(This article belongs to the Section Energy Fundamentals and Conversion)
Full-Text   |   PDF [3133 KB, uploaded 18 May 2017]   |  


This paper presents a new space vector pulse width modulation (SVPWM) to eliminate common-mode voltage (CMV) for multilevel inverters. The proposed SVPWM is performed in a new coordinate system, in which the converter voltage vectors have only integer entries and the absolute coordinate increment between adjacent vectors is equal to 1. The location of the reference vector, detection of the nearest three CMV vectors, and duty cycles of the nearest three CMV vectors are all obtained by simple calculations, no lookup table is needed and the SVPWM is computationally fast. Compared with earlier pulse width modulations (PWMs), the realization of the CMV vectors is very simple, and the CMV of multilevel inverters are limited to zero with any modulation index. Because the SVPWM is independent of the level number of the inverter, the proposed SVPWM is suitable for any level of inverter. This paper also thoroughly compares the proposed SVPWM with prior PWMs. Experimental results are also given in the paper. View Full-Text
Keywords: SVPWM; common-mode voltages; multilevel inverters SVPWM; common-mode voltages; multilevel inverters

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Tang, X.; Lai, C.; Liu, Z.; Zhang, M. A SVPWM to Eliminate Common-Mode Voltage for Multilevel Inverters. Energies 2017, 10, 715.

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