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Open AccessArticle

A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems

1
College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea
2
Samsung Electronics, Hwaseong 18448, Korea
*
Authors to whom correspondence should be addressed.
Sensors 2018, 18(8), 2709; https://doi.org/10.3390/s18082709
Received: 25 July 2018 / Revised: 9 August 2018 / Accepted: 14 August 2018 / Published: 17 August 2018
(This article belongs to the Section Physical Sensors)
We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply. View Full-Text
Keywords: dual-channel; transceiver; charge-recycling; shared CDR; CMOS Image Sensor (CIS) System; stacked driver dual-channel; transceiver; charge-recycling; shared CDR; CMOS Image Sensor (CIS) System; stacked driver
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Kim, S.-H.; Shin, H.; Jeong, Y.; Lee, J.-H.; Choi, J.; Chun, J.-H. A 12-Gb/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems. Sensors 2018, 18, 2709.

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