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Open AccessArticle

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea
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Sensors 2018, 18(10), 3486; https://doi.org/10.3390/s18103486
Received: 30 August 2018 / Revised: 2 October 2018 / Accepted: 13 October 2018 / Published: 16 October 2018
(This article belongs to the Section Internet of Things)
Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step. View Full-Text
Keywords: analog-to-digital converter; successive approximation register; comparator offset; capacitor mismatch calibration analog-to-digital converter; successive approximation register; comparator offset; capacitor mismatch calibration
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Lee, J.-H.; Park, D.; Cho, W.; Phan, H.N.; Nguyen, C.L.; Lee, J.-W. A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques. Sensors 2018, 18, 3486.

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