# Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation

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## Abstract

**:**

## 1. Introduction

## 2. LCC Decoding Algorithm

## 3. Time-Varying Channel Adaptive LCC Algorithm

Algorithm 1: Time-Varying Channel Adaptive LCC Algorithm |

## 4. The Proposed Time-Varying Channel Adaptive LCC Decoder

#### 4.1. Multiplicity Assignment with Channel Detection

#### 4.2. The Architecture of the Proposed Pcf Block

## 5. Implementation Results

## 6. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 2.**Frame error rate (FER) versus Eb/No of the proposed decoder compared with other algorithms for RS(255,239) codes.

**Figure 3.**Frame error rate (FER) versus Eb/No of the proposed decoder compared with other algorithms for RS(127,119) codes.

**Table 1.**The corresponding relationship between the counter value of received RS(255,239) code and the decoding parameters.

Counter | 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 | 24 | 36 | >36 |
---|---|---|---|---|---|---|---|---|---|---|---|

Error num. | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | >10 |

${t}_{a}$ | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 8 | 8 | 8 |

TV num. $\zeta $ | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 4 | 8 | 16 |

**Table 2.**The corresponding relationship between the counter value of received RS(127,119) code and the decoding parameters.

Counter | 2 | 4 | 6 | 8 | 14 | >14 |
---|---|---|---|---|---|---|

Error num. | 1 | 2 | 3 | 4 | 5 | >5 |

${t}_{a}$ | 1 | 2 | 3 | 4 | 4 | 4 |

TV num. $\zeta $ | 1 | 1 | 1 | 1 | 4 | 8 |

Testing Order | TV1 | TV2 | TV3 | TV4 |
---|---|---|---|---|

Flipping pattern | 00000000 | 11111000 | 10000110 | 11100100 |

Testing order | TV5 | TV6 | TV7 | TV8 |

Flipping pattern | 01011011 | 10100011 | 01110000 | 00111010 |

Testing order | TV9 | TV10 | TV11 | TV12 |

Flipping pattern | 11001001 | 00010101 | 10000000 | 01001110 |

Testing order | TV13 | TV14 | TV15 | TV16 |

Flipping pattern | 00101001 | 11010010 | 01000101 | 10011100 |

Testing Order | TV1 | TV2 | TV3 | TV4 |
---|---|---|---|---|

Flipping pattern | 00000000 | 11100000 | 10011000 | 01000110 |

Testing order | TV5 | TV6 | TV7 | TV8 |

Flipping pattern | 00110000 | 00101001 | 11000101 | 10000010 |

Testing order | TV${}_{e}$1 | TV${}_{e}$2 | TV${}_{e}$3 | TV${}_{e}$4 |

Even Flipping pattern | 00000000 | 11100000 | 10011000 | 01010100 |

Testing order | TV${}_{e}$5 | TV${}_{e}$6 | TV${}_{e}$7 | TV${}_{e}$8 |

Even Flipping pattern | 00100011 | 10101100 | 01001000 | 10000011 |

Testing order | TV${}_{o}$1 | TV${}_{o}$2 | TV${}_{o}$3 | TV${}_{o}$4 |

Odd Flipping pattern | 00000000 | 11100000 | 10011000 | 00000100 |

Testing order | TV${}_{o}$5 | TV${}_{o}$6 | TV${}_{o}$7 | TV${}_{o}$8 |

Odd Flipping pattern | 01110010 | 11000101 | 10101010 | 00110001 |

Algorithm | Num. of TVs | Avg. Num. of TVs | FER |
---|---|---|---|

Conv. LCC in [9], TV = 8 | 6400 k | 8 | 3.17 × 10${}^{-4}$ |

Conv. LCC in [9], TV = 16 | 12,800 k | 16 | 1.66 × 10${}^{-4}$ |

Modified LCC in [9], TV = 8 | 6400 k | 8 | 1.95 × 10${}^{-4}$ |

Modified LCC in [9], TV = 16 | 12,800 k | 16 | 7.96 × 10${}^{-5}$ |

Modified LCC in [11], TV = 8 | 6400 k | 8 | 1.34 × 10${}^{-4}$ |

Proposed LCC TV ≤ 8 | 4899 k | 6 | 1.74 × 10${}^{-4}$ |

Proposed LCC TV ≤ 16 | 6347 k | 8 | 7.63 × 10${}^{-5}$ |

Algorithm | Conv. LCC, TV = 8 | Proposed LCC, TV ≤ 8 | Proposed LCC (Even/Odd), TV ≤ 8 |
---|---|---|---|

Num. of TVs | 6400 k | 3049 k | 3049 k |

Avg. num. of TVs | 8 | 3.8 | 3.8 |

FER | 7.88 × 10${}^{-4}$ | 6.71 × 10${}^{-4}$ | 6.76 × 10${}^{-4}$ |

**Table 7.**The implementation results of the proposed MA module in 0.13 $\mathsf{\mu}\mathrm{m}$ CMOS process at 200 MHz.

Module | Area (${\mathbf{mm}}^{2}$) | Gate Count (XORs) | ${\mathit{f}}_{\mathit{max}}$ (MHz) | Throughput (Gb/s) | Power (mW) |
---|---|---|---|---|---|

MA [7] | 0.0661 | 5561 | 220 | 1.76 | 6.0 |

Proposed | 0.0625 | 5261 | 385 | 3.08 | 5.6 |

Architecture | [7] | [9] | [11] | Proposed | Proposed |
---|---|---|---|---|---|

Tech. | 0.13 µ$\mathrm{m}$ | 65 nm | 65 nm | 0.13 µ$\mathrm{m}$ | 65 nm |

${f}_{max}$ (MHz) | 220 | 550 | 550 | 385 | 550 |

Power (mW@MHz) | - | 23.0@550 | 21.5@550 | 259.2@385 | 31.5@550 |

Throughput (Gbps) | 1.6a | 4.4a | 8.8a | 15.7b | 22.4b |

Gate count (kXORs) with buffer | 27.9 | 31.1 | 34.9 | 55.4 | 56.8 |

Coding gain (dBs@FER) | 0.37@10${}^{-6}$ | 0.56@10${}^{-6}$ | 0.50@10${}^{-6}$ | 0.56@10${}^{-6}$ | 0.56@10${}^{-6}$ |

Latency (clock cycles) | 400a | 528a | 272a | 50b | 50b |

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**MDPI and ACS Style**

Wang, H.; Zhang, W.; Chang, Y.; Gao, J.; Liu, Y.
Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation. *Entropy* **2022**, *24*, 424.
https://doi.org/10.3390/e24030424

**AMA Style**

Wang H, Zhang W, Chang Y, Gao J, Liu Y.
Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation. *Entropy*. 2022; 24(3):424.
https://doi.org/10.3390/e24030424

**Chicago/Turabian Style**

Wang, Hao, Wei Zhang, Yanyan Chang, Jiajing Gao, and Yanyan Liu.
2022. "Low-Complexity Chase Decoding of Reed–Solomon Codes Using Channel Evaluation" *Entropy* 24, no. 3: 424.
https://doi.org/10.3390/e24030424