Search Results (474)

Intelligence, surveillance, and reconnaissance (ISR) platforms and electric vertical take-off and landing (eVTOL) aircraft demand onboard power conversion systems that simultaneously achieve high gravimetric power density, robustness, and fault-tolerance. In this context, modular battery architectures based on per-string power electronic interfaces emerge as a key enabler for voltage regulation, fault isolation, and in-flight reconfiguration. However, the stringent mass and volume constraints of electric aviation place magnetic components among the primary limiting factors of converter scalability. This paper presents a design methodology for interleaved converters with coupled inductors that explicitly decompose common-mode, differential-mode, and uncoupled inductance components. The proposed approach enables independent adjustment of current ripple and dynamic response, allowing zero-voltage switching (ZVS) operation while ensuring stable and controllable behavior under close-loop current regulation. The methodology is experimentally validated on a 4 kW two-phase interleaved GaN-based boost converter operating at 500 kHz. Experimental results demonstrate a peak efficiency of 97%, with less than 1% variation across the operating range, and stable dynamic behavior under load transients. These results confirm the effectiveness of the proposed design methodology as a scalable solution for high-power-density, high-reliability power converters in electric aviation battery systems. Full article

To address the issue that current ripple in traditional switching power amplifiers (SPA) for active magnetic bearing (AMB) systems is constrained by the switching frequency, this paper proposes a novel LCL filter-based switching power amplifier (LCL-SPA) along with its parameter design and high-performance control strategy. Without altering the original full-bridge topology or the switching frequency, the proposed scheme achieves superior ripple suppression. To tackle the inherent resonance problem of the LCL filter, a sensorless capacitor current feedback active damping (CCFAD) strategy is proposed. This approach effectively suppresses resonance without additional hardware sensors and ensures system stability under digital control delays. Furthermore, to overcome the limitations of traditional PI controllers in terms of the dynamic performance and parameter tuning of the LCL-SPA, a high-performance LESO-based control algorithm within the Linear Active Disturbance Rejection Control (LADRC) framework is designed. By utilizing a Linear Extended State Observer (LESO) to estimate and compensate for total lumped disturbances in real-time, the algorithm simplifies the parameter tuning process and achieves rapid current tracking with nearly zero overshoot. Experimental results demonstrate that the proposed LCL-SPA achieves extremely low current ripple across various reference currents, with the ripple minimized to 20 mA at a 3 A load. Frequency response tests confirm that the system possesses a closed-loop bandwidth of up to 2 kHz, satisfying the high dynamic requirements of magnetic bearings. Full article

Switched-inductor converters are ubiquitous in modern electronics. Their switching behavior makes them inherently nonlinear and unsuitable for classical linear frequency-response models, requiring linearization for stability analysis. Common approaches—such as state-space averaging, circuit averaging, and signal-flow graphs—can be algebraically intensive and may offer limited circuit-level interpretability. This paper proposes a direct small-signal AC response model for switched inductors in both CCM and DCM that preserves circuit intuition while maintaining the accuracy of conventional methods. The proposed framework enables the systematic derivation of the duty-cycle-to-output-voltage, duty-cycle-to-output-current, and duty-cycle-to-inductor-current transfer functions within a unified circuit representation. Bode plots of the duty-cycle-to-voltage and duty-cycle-to-current gains confirm that the model accurately captures the LC double pole and associated zeros, including the shift of the load-related zero in the reconstructed inductor-current gain. The resulting model remains straightforward to use, analyze, and simulate and may facilitate control-loop design as well as integration into automated synthesis or optimization tools. In DCM, the model further provides an analytical expression for the duty-cycle-to-inductor-current gain, contributing to a clearer understanding of this relationship in the literature. Results validated in SIMPLIS show excellent agreement with state-space averaging predictions. Full article

Common-mode voltage (CMV) is a critical concern in motor drive applications employing multilevel inverters, as it can lead to significant issues such as high-frequency noise, electromagnetic interference, and motor bearing degradation. These effects can compromise the reliability, reduce the operational lifespan of electric machines, and introduce safety hazards. In this study, an enhanced Direct Torque Control (DTC) strategy incorporating Space Vector Modulation (SVM) is proposed to specifically address CMV-related challenges in induction motors (IM) driven by a three-level Neutral-Point-Clamped (NPC) inverter. The proposed DTC scheme utilizes a specialized modulation technique that effectively mitigates CMV while also minimizing current harmonic content, and torque and flux ripples with a constant switching frequency. The developed SVM algorithm simplifies the three-level space vector representation into six equivalent two-level diagrams, enabling more efficient control. The zero-voltage vector is synthesized virtually by combining two active vectors within a two-level hexagonal structure. The effectiveness of the proposed DTC approach is validated through both simulation and Hardware-In-the-Loop (HIL) testing. Compared to the conventional DTC method, the proposed solution demonstrates superior performance in CMV minimization and leakage current reduction. Notably, it limits the CMV amplitude to V_dc/6, a significant improvement over the V_dc/2 typically observed with the standard DTC approach. Full article

To address the issues of limited soft-switching range and high inductor current peak in traditional single phase shift (SPS) modulation for AC–DC converters under a wide range of voltage conversion ratio conditions, this paper proposes an optimized modulation strategy based on SPS modulation. First, the steady-state operating characteristics under SPS modulation are analyzed, and the current-transfer equation is derived. A conversion coefficient is then introduced to transform the conventional phase-shift ratio into a new variable. Based on this, the time-domain characteristics of the inductor current peak and the constraints for zero voltage switching (ZVS) are analyzed. An analytical expression of the conversion coefficient is obtained, which ensures ZVS operation for all switches in the dual-active-bridge (DAB) converter and minimizes the inductor current peak. Finally, experiments verify the effectiveness and feasibility of the proposed modulation strategy. Full article

The three-phase four-leg (3P4L) parallel-inverter system has been increasingly applied in the field of new energy power generation due to its capability of feeding single-phase loads. However, zero-sequence circulating current (ZSCC) can jeopardize the stable operation of the parallel-inverter system. To address this issue, this paper proposes a ZSCC suppression strategy based on the coordination of Model Predictive Control (MPC) and an improved 3D-SVPWM technique. Firstly, an overall methodology is established by introducing a regulation factor into each switching cycle of the inverter modulation. This introduction enables flexible adjustment of the zero-sequence duty cycle difference between the two inverters, laying the foundation for ZSCC suppression. Secondly, the MPC algorithm is applied to construct a transfer function model of the parallel system incorporating the regulation factor. Closed-loop feedback of ZSCC is introduced, using the deviation between the actual ZSCC and zero as the cost function, and the zero-vector duty cycle adjustment margin as the constraint. The optimal regulation factor is calculated and injected into the improved 3D-SVPWM. Through receding horizon optimization within MPC, disturbances are actively predicted and compensated, achieving precise ZSCC suppression. Finally, simulation results based on Matlab and hardware-in-the-loop (HIL) verify the effectiveness of the proposed strategy. Full article

Quasi-resonant (QR) DC–DC converters with PWM control achieve soft switching by shaping the commutation transient through a local resonant process. This paper proposes a symmetry-based unified perspective on classical QR converters by interpreting zero-voltage switching (ZVS) and zero-current switching (ZCS) as dual commutation symmetries: ZVS restores voltage symmetry at turn-on, whereas ZCS restores current symmetry at turn-off. Building on this viewpoint, we organize QR Buck, Boost, and Buck–Boost converters through two complementary forms of symmetry: (i) commutation symmetry (ZVS vs. ZCS) and (ii) topological duality (Buck ↔ Boost and the self-dual nature of Buck–Boost). The framework is anchored in normalized parameter spaces commonly used in QR analyses and is illustrated using representative ZVS and ZCS Buck cases, including waveform-stage symmetry and loss/stress implications. Furthermore, we discuss the “cost of symmetry” via stress and conduction-loss metrics, highlighting how soft-switching conditions trade voltage and current stresses in dual fashions. The proposed organization offers a compact conceptual map that links operating regimes, design degrees of freedom, and expected stress/loss trends across the main classical QR-PWM converter families. Full article

The Four-Leg Three-Phase Voltage Source Inverter (4LVSI) is a versatile solution for integrating renewable energy sources (RESs) into distribution networks, as it compensates unbalanced voltages and currents while providing a path for zero-sequence components. Accurate current control is essential to ensure power quality and reliable operation under these conditions. Conventional controllers such as proportional–integral, resonant, or feedback-linearization methods achieve acceptable tracking under static dc-link conditions, but their performance degrades when dc-link voltage dynamics arise due to renewable-source fluctuations. This paper proposes a data-driven model reference neural control (MRNC) strategy for a four-leg inverter connected to RESs, explicitly accounting for dc-link voltage variations. The proposed controller reformulates the classical Model Reference Adaptive Control (MRAC) as a lightweight single-layer neural network whose adaptive weights are updated online using the Recursive Least Squares (RLS) algorithm. In this framework, the dc-link variations are not modeled explicitly but are implicitly learned through the data-driven adaptation process, as their influence is captured in the neural network regressors formed from real-time input–output measurements. This allows the controller to continuously identify the inverter dynamics and compensate the effect of dc-link fluctuations without requiring additional observers or prior modeling. The proposed approach is validated through detailed time-domain simulations and real-time Hardware-in-the-Loop (HIL) experiments implemented at a 10 kHz switching frequency. The results indicated that the RLS-based MRNC controller achieved the lowest steady-state current error, reducing it by approximately 1.85% and 1% compared to the Proportional-Resonant (PR) and One-Step-Ahead (OSAC) controllers, respectively. Moreover, under dc-link voltage variations, the proposed controller significantly reduced the current overshoot, achieving decreases of 5.9 A and 6.36 A relative to the PR controller. Full article

The transition to clean photovoltaic sustainable generation sources has motivated several developments in required power electronics interface systems. The conventional solution is based on two cascaded conversion stages, leading to reduced efficiency, inevitable leakage currents, and/or a high number of required components. Another solution is the use of integrated two-stage solutions suffering from asymmetrical switch structures, discontinuous input side currents, and/or complex modulation and control requirements. This paper presents a modified configuration with symmetrical six switches based on the common ground boost inverter solution. Furthermore, the proposed solution presents a continuous input side current and a simple modulation strategy. Moreover, the proposed CG topology offers a reduction of the current stress on the power switch by diverting the load current away from the power switch during the inductor charging. The operation, modulation, and control of the developed solution are presented in the paper, including comprehensive performance comparisons with boost inverter solutions in the literature. Simulation and experimental prototype-based results confirm the advantages and superiority of the proposed topology over existing topologies. Full article

The DC converter constitutes a pivotal component within medium-voltage direct current (MVDC) collection systems, performing functions such as voltage boosting, isolation, and power transmission. To accommodate the demand for high-capacity DC converters in MVDC collection systems for new energy sources, a full-bridge medium-frequency converter featuring low voltage and current stress on auxiliary switching devices is proposed. Based on the principles of dual-transformer configuration and component sharing, this converter employs a half-bridge circuit and a full-bridge circuit sharing two switching devices. Utilizing mixed-frequency modulation, the full-bridge main circuit operates at medium frequency to transmit the majority of power, while the half-bridge auxiliary circuit regulates overall power and voltage through high-frequency chopping control. This achieves zero-current switching for the medium-frequency switching devices across the entire load range, significantly reducing switching losses in the converter. This paper details the converter’s operating principles and analyzes key parameter design methodologies. Finally, a 240–6000 V/7200 W prototype was constructed to validate the proposed converter’s performance. Full article

This paper proposes a zero-voltage-switching (ZVS) synchronous buck converter employing a digital hybrid control scheme with variable slope compensation. By using an auxiliary-switch network and a digital controller to sense voltage and current, the system can automatically adjust the slope-compensation parameters according to the input and output conditions, thereby enhancing stability over a wide operating range. The proposed method effectively suppresses the reverse-recovery current spike of the synchronous rectifier during continuous conduction mode (CCM) operation and enables the main switch to achieve ZVS, reducing switching loss and improving efficiency. A laboratory prototype with an input voltage range of 30–160 V and output voltage levels of 24 V, 48 V, and 96 V at 5 A is developed to verify the feasibility of the proposed architecture. Full article

Three-leg AC-DC Vienna rectifiers are susceptible to single open-switch faults, which make DC-link voltage ripple and make three-leg input AC currents distorted and unbalanced. Thus, this paper presents a quick identification method for single open-switch faults based on three-leg fault currents and output capacitors voltage difference. Fault-leg identification depended on zero-plateaus in the three-leg fault currents, whereas fault-side identification was dependent on reconstruction variables obtained through Clark transformation and phase shifting. In order to improve the reliability of the diagnosis system, the harmonic component of capacitor voltage difference is used to realize the missed diagnosis detection and adjust the time threshold automatically. This method requires no additional hardware and is easy to implement. Experimental results verify the effectiveness of this strategy. It is shown that the fault diagnosis method proposed in this paper has the advantages of fast diagnosis speed, high accuracy and good robustness. Full article

This paper proposes a fixed frequency pulse width modulation (PWM) for a dual active half-bridge resonant converter. The wide voltage range can be achieved without adding any additional components, and the voltage gain characteristic is independent of the load. Meanwhile, all switches can achieve full range zero voltage switching (ZVS). The driving logic is unified between the primary and secondary sides, allowing for the implementation of both boost and buck modes. Hence, the control logic is simple. In addition, the multiple-order harmonic analysis of the resonant tank is proposed without complex time-domain calculations. Hence, the expression of voltage gain, current characteristics, and soft switching conditions can be conveniently analyzed. Finally, a 500 W experimental prototype was built. The experimental results prove the effectiveness and superiority of the proposed solution. Full article

With the increasing demand for high efficiency and high power density in photovoltaic power generation, triangular current mode (TCM) control has garnered significant attention due to its capability to achieve zero voltage switching (ZVS) for switches. However, TCM is inherently a variable-frequency control method. Traditional modeling approaches based on fixed-frequency assumptions neglect the non-linear characteristics and sideband effects introduced by frequency variations, failing to accurately describe the dynamic behavior of the system. This paper proposes a multi-frequency small-signal modeling method tailored for TCM inverters. Small-signal models characterizing the impact of duty cycle perturbations and frequency modulation perturbations on the output voltage are derived, and the joint effect of both the duty cycle and switching frequency is analyzed. On this basis, a loop gain expression incorporating sideband frequency components is derived using Mason’s gain formula. Finally, the proposed model is verified through simulation. The results demonstrate that, compared with the multi-frequency model, which only considers the effect of duty cycle control, the proposed multi-frequency model can more accurately predict the dynamic response of TCM inverters across a wide frequency range, providing a precise theoretical basis for the control system design of variable-frequency inverters. Full article

Modern deep neural network (DNN) accelerators must sustain high throughput while avoiding performance degradation from supply voltage (VDD) droop, which occurs when large arrays of multiply–accumulate (MAC) units switch concurrently and induce high peak current ($IC{C}_{max}$) transients on the power delivery network (PDN). In this work, we focus on ASIC-class DNN accelerators with tightly synchronized MAC arrays rather than FPGA-based implementations, where such cycle-aligned switching is most pronounced. Conventional guardbanding and reactive countermeasures (e.g., throttling, clock stretching, or emergency DVFS) either waste energy or incur non-trivial throughput penalties. We propose SparseDroop, a unified hardware-conscious framework that proactively shapes instantaneous current demand to mitigate droop without reducing sustained computing rate. SparseDroop comprises two complementary techniques. (1) SparseStagger, a lightweight hardware-friendly droop scheduler that exploits the inherent unstructured sparsity already present in the weights and activations—it does not introduce any additional sparsification. SparseStagger dynamically inspects the zero patterns mapped to each processing element (PE) column and staggers MAC start times within a column so that high-activity bursts are temporally interleaved. This fine-grain reordering smooths $ICC$ trajectories, lowers the probability and depth of transient VDD dips, and preserves cycle-level alignment at tile/row boundaries—thereby maintaining no throughput loss and negligible control overhead. (2) SparseBlock, an architecture-aware, block-wise-structured sparsity induction method that intentionally introduces additional sparsity aligned with the accelerator’s dataflow. By co-designing block layout with the dataflow, SparseBlock reduces the likelihood that all PEs in a column become simultaneously active, directly constraining $IC{C}_{max}$ and peak dynamic power on the PDN. Together, SparseStagger’s opportunistic staggering (from existing unstructured weight zeros) and SparseBlock’s structured, layout-aware sparsity induction (added to prevent peak-power excursions) deliver a scalable, low-overhead solution that improves voltage stability, energy efficiency, and robustness, integrates cleanly with the accelerator dataflow, and preserves model accuracy with modest retraining or fine-tuning. Full article