A Novel Two-Transformer Full-Bridge Converter with Integrated Boost Converter for Hold-Up Time Compensation

Abstract

This article presents a new full-bridge converter with two series-connected transformers (TTFB), designed to meet the hold-up time requirements in power systems. The conventional TTFB topology offers low root mean square (RMS) output current, clamped voltage stress across the primary switches, and zero-voltage switching (ZVS) capability. However, under a wide input voltage range, it suffers from a significant circulating current during the freewheeling period, leading to efficiency degradation. To mitigate this issue, a new converter is proposed by integrating the TTFB with a boost circuit, which operates during the hold-up state when the input voltage drops below the nominal level. Thus, the proposed converter can increase the duty ratio under nominal input voltage conditions, thereby reducing the primary-side RMS current and improving efficiency. To validate the effectiveness of the proposed method, a prototype with a 12 V/400 W output was implemented. The proposed converter achieved a peak efficiency of 92.1% at 50% load, and maintained a higher efficiency across the entire load range compared to the conventional design. Thus, the proposed converter offers a solution for applications demanding extended hold-up time with improved efficiency.

1. Introduction

Hold-up time refers to the duration during which a power converter must continue supplying a regulated output voltage after an alternating current (AC) input power interruption, as illustrated in Figure 1. This short-term backup capability is especially critical in modern power systems to ensure uninterrupted power delivery during brief outages. Applications such as telecom, data servers, industrial controllers, medical devices, and aerospace systems demand reliable operation, even during momentary input voltage sags or dropouts. In these systems, hold-up time serves as a key design parameter to avoid unintentional resets, data loss, or system malfunction.

To meet these application-specific hold-up time requirements, power converters must not only ensure reliable energy delivery during interruptions but also address size and cost constraints. During the hold-up time, i.e., when the AC line is momentarily lost, the energy required by the load is supplied by the DC/DC converter, which draws power from the bulky link capacitor. Therefore, the converter must be carefully sized to satisfy the requirements typically ranging from 10 ms to over 50 ms, depending on the relevant standards [1,2,3].

In practice, minimizing the size of the link capacitors is essential to reduce cost and improve the power density. One effective strategy is to employ converter topologies that maintain output voltage regulation over a wide input voltage range [4]. Among various converter topologies, the asymmetric half-bridge (AHB), phase-shifted full-bridge (PSFB), and LLC resonant converters are widely adopted due to their galvanic isolation and ZVS capability. However, these converters have several limitations when operating over a wide input voltage range. The asymmetric operation of the AHB converter induces a DC offset current in the transformer, which leads to uneven voltage stress on the rectifier diodes [5]. As a result, components with unbalanced voltage ratings are required, and the transformer size may need to be increased to avoid magnetic saturation [6]. The PSFB converter suffers from large circulating currents, which increase conduction losses. The LLC resonant converter requires a wide switching frequency range, leading to bulky magnetic components and an increased circulating current.

To solve these problems, researchers have proposed various hold-up time compensation techniques, as illustrated in Figure 2. The first approach involves improving AC/DC control strategies [7,8,9,10]. A method to compensate for the link capacitor voltage using an extension circuit was studied in [7,8]. However, the additional power diode in the main current path decreases the converter’s efficiency. A variable DC-link voltage control scheme is discussed in [9], and the use of a boost converter as a half-bridge converter is studied in [10]. However, placing a capacitor between the bridge diode and the AC/DC stage may lead to undesirable harmonic distortion.

The second approach focuses on optimization of the DC/DC stage. Various techniques have been studied to improve the inherent issues of each topology under wide input voltage conditions. In AHB converters, several techniques have been investigated to suppress the DC offset current [11,12,13,14,15]. Methods such as secondary side switch control, the use of a coupled inductor rectifier, and a secondary capacitor [11,12,13] have been shown to effectively reduce the DC offset current. These techniques allow for a symmetric duty ratio of the main and auxiliary switches. However, unbalanced voltage stress on the rectifier diodes may cause uneven switching losses, affecting system reliability. Other methods involve adjusting the transformer turns ratio to increase voltage gain [14,17]. Although these methods can be applied to other topologies, they require increased transformer winding turns and additional switching components. In PSFB converters, various techniques have been proposed to reduce circulating currents [16,17,18,19]. A frequency modulation scheme was employed to increase the voltage gain [16]. During the hold-up state, the operating frequency shifted to the lower side to increase voltage gain. However, the main transformer became bulky and lossy due to the design considerations for low-frequency operation. Additionally, the resonant inductance variation scheme [15,18] mitigates inherent defects of the topologies and provides voltage clamping for the rectifier diodes. However, the use of an additional inductor and two switches increases costs. Similarly, various approaches to limiting the switching frequency range in the LLC resonant converter have been proposed [20,21,22,23,24]. For example, an asymmetric pulse width modulation (PWM) control scheme [20] can achieve high voltage gain during the hold-up time, but the transformer remains bulky due to the transformer DC offset current. Resonant tank modifications [21,22,23] allow for voltage regulation within a narrow frequency range by varying the resonant capacitance or inductance. However, these methods typically require additional components, leading to higher costs.

Another candidate topology in DC/DC converter that does not require an output inductor is the full-bridge converter with two series-connected transformers (TTFB) [25], as shown in Figure 3a. These two transformers act not only as the main transformer but also as the output inductor [26,27]. The TTFB eliminates the need for an output inductor, simplifying the structure and manufacturing process [28,29]. In addition, the TTFB enables ZVS for all switches and extends the ZVS range for the lagging leg switches due to its increased leakage inductance. Furthermore, the control method is relatively simple, as it operates at a fixed switching frequency. The stress on the switching components is also balanced due to the symmetric operation of the primary switch legs. However, circulating current during the freewheeling interval remains a drawback [30]. Methods such as using a diode on the secondary side or adding a blocking capacitor on the primary side have been proposed to mitigate this issue [31,32]. Despite reducing circulating current, this issue remains and results in increased voltage stress on the rectifier diodes due to the voltage across the primary capacitor. An existing method [18], as shown in Figure 3b, can be applied to the TTFB for hold-up time compensation. This method clamps the voltage across the rectifier diodes while reducing circulating current. However, it requires high-voltage-rated switches and an auxiliary inductor.

This article proposes a new hold-up time compensation circuit for TTFB, as shown in Figure 4. By integrating a single MOSFET and auxiliary diodes on the secondary side, the proposed converter enables maximum duty ratio operation under nominal input voltage. This effectively eliminates circulating current and enables the use of low-voltage-rated rectifier diodes. Moreover, the additional components do not conduct during the nominal state. Therefore, the proposed method can prevent unnecessary losses from these components. Unlike similar techniques [19,24], the proposed converter supports a center-tap rectifier with fewer conducting components, enabling a simpler and more economical design.

To validate the advantages of the proposed converter, a prototype with an input range of 250–400 V and an output of 12 V/400 W is implemented, and both theoretical analysis and experimental results are presented.

The rest of this article is organized as follows. Section 2 presents the derivation and operational principle of the proposed converter. Section 3 provides the characteristics of the proposed converter. A 250–400 V input and 12 V/400 W output prototype was built and tested to verify the effectiveness and feasibility of the proposed converter in Section 4. Finally, Section 5 concludes this article.

2. Features of the Proposed Converter

2.1. Derivation of the Proposed Converter

Figure 5 shows the derivation process of the proposed method for compensating the hold-up time. As shown in Figure 5a, the center-tap rectifier comprises two rectifier diodes (D₁ and D₂), an output capacitor (C_O), and the magnetizing inductances (L_m1 and L_m2) of the transformers. In the conventional TTFB topology, when switches Q₁ and Q₄ are turned on, L_m2 operates as an output inductor. Figure 5b illustrates that, when the auxiliary switch Q_a is added and turned on, diode D₁ is turned off. Consequently, the voltage across L_m1 and L_m2 becomes zero and V_S/n, respectively, where V_S/n represents the input voltage reflected by the transformer turns ratio. As a result, the current through magnetizing inductance i_Lm1 remains constant, while the i_Lm2 increases, leading to the build-up mode. When Q_a is turned off, as shown in Figure 5c, D₁ turns on, and the current difference between i_Lm2 and i_Lm1 flows toward the output. This operation is referred to as the powering mode. Figure 5d shows the circuit for one full switching cycle operation, where auxiliary switches Q_a1 and Q_a2 can be merged into a single switch for simplification.

To realize this integration, auxiliary diodes D_a1 and D_a2 are required, as shown in Figure 5e, to prevent a short-circuit path through the transformers. Compared to the boost integration approach proposed in [33], the auxiliary components do not increase conduction losses during nominal operation, since the auxiliary diodes only conduct during the hold-up state. This feature significantly reduces conduction losses on the secondary side. Additionally, Figure 5f illustrates another type of rectifier configuration. The type II rectifier may be preferable, as it requires only one floating gate driver for Q_a when synchronous rectifiers are used, compared to the type I rectifier.

2.2. Operational Principles

To explain the operational principles of the proposed converter, key waveforms and the equivalent circuits are presented in Figure 6, Figure 7 and Figure 8. The proposed converter operates in two main modes depending on the AC line status. The nominal state refers to the condition in which the auxiliary switch Q_a remains off and the converter operates as a traditional TTFB, as shown in Figure 7. The hold-up state occurs when Q_a is modulated using PWM to boost the output voltage, as shown in Figure 8. These two modes alternate according to input voltage conditions. The waveforms for the nominal state are shown in Figure 6a, while those for the hold-up state are presented in Figure 6b.

One switching cycle is divided into two half cycles. Since the two half cycles are symmetric except for the reversed current direction, only the first half cycle is explained. As shown in the key waveforms, D_a denotes the duty ratio during which the switch Q_a is turned on. For simplicity in the mode analysis, several assumptions are defined as follows:

(1)

The two transformers are identical, with the same turns ratio (N_p1/N_s1 = N_p2/N_s2 = n), magnetizing inductance (L_m1 = L_m2 = L_m), and leakage inductance (L_lkg1 = L_lkg2 = L_lkg).

(2)

Magnetizing inductance L_m is sufficiently larger than leakage inductance L_lkg (L_m >> L_lkg).

(3)

The magnetizing inductances reflected to the primary side are denoted as L_m1.p and L_m2.p, and their values are equal to L_m.p.

(4)

Switches Q₁–Q₄ operate ideally, except for output capacitance and body diode.

(5)

The additional switch Q_a operates ideally, except for body diode.

(6)

The duty loss is neglected, and the output voltage is constant.

2.2.1. Mode Analysis: Nominal State Operation

In the nominal state, the proposed converter has the same circuit configuration as the conventional TTFB, as shown in Figure 3a, since the auxiliary switch Q_a remains off. Its operating principle is identical to that of a conventional TTFB, which employs phase-shift modulation to control the primary switches. Since the proposed converter is designed to operate at the maximum duty ratio, the analyzed operating point is assumed to be D = 0.5.

Mode 1 [t₀ − t₁]: After Q₁ and Q₄ are turned on and the commutation of the secondary rectifier diodes D₁ and D₂ are completed, mode 1 starts. The transformer T1 acts as a forward type of transformer in this mode. Since i_D1 and i_D2 are commutated completely, D₂ is turned off and D₁ is still conducting. Therefore, V_o is applied across L_m1, and V_s/n − V_o is impressed on L_m2. That is, L_m2 plays a role as an inductor and determines the slope of the primary current in this mode. The energy stored in L_m2 during this mode should be discharged through D₂ in all modes except for mode 1. The primary current i_pri(t), magnetizing current i_Lm1.p(t), and current through D₁ are determined as follows:

$$i_{pri}(t)=i_{pri}(t_0)+{\displaystyle \frac{V_S-n{V}_O}{L_{m.\mathrm{p}}}}(t-t_0)$$

(1)

$$i_{Lm1,\mathrm{p}}(t)=i_{Lm1,\mathrm{p}}(t_0)+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}(t-t_0)$$

(2)

$$i_{D1}(t)=i_{D1}(t_0)+{\displaystyle \frac{n(V_S-2n{V}_O)}{L_{m.\mathrm{p}}}}(t-t_0).$$

(3)

Mode 2 [t₁ − t₂]: After Q₁ and Q₄ are turned off, the primary current flows back to the source through the output capacitor of Q₂ and Q₃. During this mode, the output capacitance of Q₂ and Q₃ start to be discharged, while those of Q₁ and Q₄ begin to be charged. Due to the energy stored in the leakage inductance, the current continues to flow through the body diodes of Q₂ and Q₃. Once the voltage across Q₂ and Q₃ drops to zero, ZVS turn-on is achieved. Meanwhile, when V_Lm2 reaches −V_o, the output current commutates from D₁ to D₂. This mode is essential for achieving soft switching. The i_pri(t), i_Lm1.p(t), and i_D1(t) are expressed as follows:

$$i_{pri}(t)=i_{pri}(t_1)-{\displaystyle \frac{V_S}{2L_{lkg}}}(t-t_1)$$

(4)

$$i_{Lm1,\mathrm{p}}(t)=i_{Lm1,\mathrm{p}}(t_1)+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}(t-t_1)$$

(5)

$$i_{D1}(t)=i_{D1}(t_1)-n\left({\displaystyle \frac{V_S}{2L_{lkg}}}+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}\right)(t-t_1).$$

(6)

2.2.2. Mode Analysis: Hold-Up State Operation

Mode 1 [t₀ − t₁]: Mode 1 begins when switches Q₁ and Q₄ are turned on, and the auxiliary switch Q_a is also turned on. Since the two transformers alternately act as a transformer and an output inductor during each half-cycle, transformer T₁ (which includes L_m1) operates as the main transformer, while transformer T₂ (which include L_m2) serves as the output inductor in this mode. Because Q_a is turned on, zero voltage is applied to L_m1. Consequently, the input voltage V_s is applied to L_m2.p, which acts as the output inductor. As a result, the primary current increases with a slope of V_s/L_m.p. The i_pri(t), i_Lm1.p(t), and i_D1(t) are expressed as follows:

$$i_{pri}(t)=i_{pri}(t_0)+{\displaystyle \frac{V_S}{L_{m.\mathrm{p}}}}(t-t_0)$$

(7)

$$i_{Lm1,\mathrm{p}}(t)=i_{Lm1.\mathrm{p}}(t_0)$$

(8)

$$i_{Da1}(t)=i_{D1}(t_0)+{\displaystyle \frac{n{V}_S}{L_{m.\mathrm{p}}}}(t-t_0).$$

(9)

Mode 2 [t₁ − t₂]: Mode 2 starts when Q_a is turned off. Since the output capacitance of Q_a, i.e., C_oss, is charged to the output voltage V_o, D_a1 is turned off, and the rectifier diode D₁ is turned on. As a result, the reflected voltage nV_o is applied to L_m1,p, while the voltage across L_m2,p decreases to V_s − nV_o. Therefore, i_pri continues to increases, but with a lower slope of (V_s − nV_o)/L_m.p. Meanwhile, the current difference i_Lm2 − i_Lm1 flows through diode D₁ to the output. The i_pri(t), i_Lm1.p(t), and i_D1(t) are expressed as follows:

$$i_{pri}(t)=i_{pri}(t_1)+{\displaystyle \frac{V_S-n{V}_O}{L_{m.\mathrm{p}}}}(t-t_1)$$

(10)

$$i_{Lm1,\mathrm{p}}(t)=i_{Lm1,\mathrm{p}}(t_1)+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}(t-t_1)$$

(11)

$$i_{D1}(t)=i_{Da1}(t_1)+{\displaystyle \frac{n(V_S-2n{V}_O)}{L_{m.\mathrm{p}}}}(t-t_1).$$

(12)

Mode 3 [t₂ − t₃]: Mode 3 begins when Q₁ and Q₄ are turned off. The output capacitance of Q₂ and Q₃ start to be discharged, while those of Q₁ and Q₄ begin to be charged. When V_Lm2 reaches −V_o, D₂ conducts and the commutation between D₁ and D₂ is started. Since V_Lm1 is still maintained at V_o, the voltage across the leakage inductor V_2Llkg is −V_s. As a result, i_pri decreases with a slope of −V_s/2L_lkg. The i_pri(t), i_Lm1.p(t), i_D1(t), and i_D2(t) are expressed as follows:

$$i_{pri}(t)=i_{pri}(t_2)-{\displaystyle \frac{V_S}{2L_{lkg}}}(t-t_2)$$

(13)

$$i_{Lm1,\mathrm{p}}(t)=i_{Lm1,\mathrm{p}}(t_2)+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}(t-t_2)$$

(14)

$$i_{D1}(t)=i_{D1}(t_2)-n\left({\displaystyle \frac{V_S}{2L_{lkg}}}+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}\right)(t-t_2)$$

(15)

$$i_{D2}(t)=n\left({\displaystyle \frac{V_S}{2L_{lkg}}}+{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}\right)(t-t_2).$$

(16)

3. Analysis of the Proposed Converter

3.1. Transformer Turns Ratio Design

The transformer turns ratio for a conventional converter is typically determined based on the minimum input voltage, with V_S,min = 250 V selected to ensure proper output voltage regulation. In contrast, the proposed converter achieves increased voltage gain through secondary-side PWM control. Therefore, its transformer turns ratio can be designed based on the nominal input voltage, V_S,nom.

In the prototype design, the mode transition is set to occur when the input voltage drops 5% below the nominal value (V_S,nom = 400 V), i.e., at approximately V_S,nom(min) ≈ 380 V. Considering a maximum effective duty ratio of D_eff,max = 0.44, which includes both the dead time and commutation time within each switching cycle, the required conventional turns ratio n_conv and proposed turns ratio n_prop are calculated as follows:

$$n_{conv}={\displaystyle \frac{V_{S,\min }{D}_{eff,\max }}{V_O}}$$

(17)

$$n_{prop}={\displaystyle \frac{V_{S,nom(\min )}{D}_{eff,\max }}{V_O}}$$

(18)

where V_o is the regulated output voltage. The resulting values of n_conv and n_prop are 9 and 14, respectively.

3.2. Voltage Gain Comparison

The normalized voltage gain of the proposed converter can be obtained by applying the volt-second balance to the magnetizing inductor. As shown in Figure 6a, the voltage applied to L_m2 in the nominal state is identical to that in the conventional TTFB converter. Consequently, the normalized voltage gain in the nominal state M_nom can be expressed as follows:

$$M_{nom}={\displaystyle \frac{n_{prop}{V}_O}{V_S}}=D.$$

(19)

The voltage applied to L_m2 in the hold-up state is shown in Figure 6b. During the first half-cycle, the applied voltage is V_S/n for D_a·T_S and (V_S/n − V_o) for (0.5 − D_a)T_S. During the second half-cycle, the applied voltage is 0 for D_a·T_S and −V_o for (0.5 − D_a)Ts. Therefore, the normalized voltage gain in the hold-up state M_hold can be expressed as follows:

$$M_{hold}={\displaystyle \frac{n_{prop}{V}_O}{V_S}}={\displaystyle \frac{0.5}{1-2D_a}}.$$

(20)

Figure 9 shows the graphs of the normalized voltage gain for the conventional and proposed converter as a function of duty ratio. Up to the maximum duty ratio, D_max = 0.5, the normalized voltage gain is the same as that of the conventional converter. With the primary side duty ratio fixed at 0.5, an additional duty ratio is applied to Q_a to further increase the voltage gain, as presented in Equation (20). Therefore, the proposed converter offers a higher voltage gain than the conventional design.

3.3. Circulating Current Comparison

Figure 10 shows the circulating current of the conventional and proposed converters. The circulating current of the proposed converter is lower than that of the conventional one. This results from the higher duty ratio of the primary-side switches. As a result, the freewheeling period is shortened, thereby further reducing the circulating current. The magnitude of the circulating current directly influences the primary-side RMS current. As the primary-side RMS current decreases, the corresponding power loss is also reduced.

3.4. ZVS Condition

The ZVS condition for the lagging leg switches is determined by the magnitude of the current at the switching instant and is expressed as follows:

$$E_{Lag\_leg}={\displaystyle \frac{1}{2}}\cdot 2L_{lkg}\cdot i_{pri}^2(t_1)\ge {\displaystyle \frac{1}{2}}\cdot 2C_{oss}\cdot V_S^2$$

(21)

$$i_{pri}(t_1)={\displaystyle \frac{I_O}{2n}}+{\displaystyle \frac{V_S-n{V}_O}{2L_{m.\mathrm{p}}}}\cdot D{T}_S-{\displaystyle \frac{n{V}_O}{L_{m.\mathrm{p}}}}(0.5-D)T_S.$$

(22)

From (15) and (16), it is evident that the ZVS condition of the proposed converter is primarily determined by the leakage inductance and the load condition. Figure 11 illustrates the relationship between load and leakage inductance, assuming a constant duty ratio across the full load range. At 20% load, the leakage inductance required to achieve ZVS in the conventional converter is approximately 3.2 times that of the proposed converter. This indicates that the proposed converter requires less energy to achieve ZVS.

3.5. Voltage Stress on Rectifier Diodes

Figure 12 illustrates the voltage stress on the rectifier diodes of both the conventional and proposed converters. In the conventional converter, the voltage applied across rectifier diodes D₁ and D₂ is always V_S/n_conv in both the nominal and hold-up states, respectively.

The worst-case condition for the conventional converter occurs when the input voltage reaches its maximum during the nominal state. In the proposed converter, the voltage across D₁ and D₂ is V_S/n_prop, which is different only because of the transformer turns ratio. During the hold-up state, V_o + V_S/n_prop is applied to D₁ and D₂. Therefore, the maximum voltage stress occurs at the transition point between the nominal and hold-up states. Consequently, a voltage stress difference of 6.4 V is observed between the conventional and proposed converters. Considering a 150% design margin, diodes with a lower voltage rating were selected.

3.6. Conduction Losses in Power Devices

Power losses in semiconductor devices increase the junction temperature, which in turn degrades device performance. Minimizing these losses enhances thermal stability and improves system reliability.

• Conduction losses in power MOSFETs:

The conduction losses for each MOSFET are given by the following:

$$P_{cond}=I_{Drms}^2\times R_{DS(on)}$$

(23)

where I_Drms is the RMS value of the drain current, and R_DS(on) is the drain source on-state resistance. All converters use identical MOSFETs; thus, R_DS(on) is the same. Since the circulating current decreases in the order of conventional 1, conventional 2, and proposed, the proposed converter has the lowest I_Drms, resulting in reduced conduction losses.

2.

Conduction losses in rectifier diodes:

In terms of reducing the number of conducting device, a center-tap rectifier employs two diodes, whereas a full-bridge rectifier requires four. Although the center-tap rectifier reduces the number of diodes by half, each experiences doubled voltage stress. This results in a higher forward voltage drop and increases conduction loss [34]. The loss for each diode is given by the following equation:

$$P_{diode}=V_F\times I_{D.avg}$$

(24)

where V_F is the forward voltage of the diode, and I_D,avg is the average current through the diode. The proposed converter allows the use of low-voltage-rated diodes in the rectifier circuit. Therefore, the proposed rectifier reduces the number of components and allows the use of diodes with low forward voltage drop, thereby lowering conduction losses.

3.7. Comparison with Previous Works

Table 1. Comparison with previous works.

Previous Work	[13]	[14]	[17]	[18]	[22]	[24]	Proposed
Topology	AHB	AHB	PSFB	PSFB	LLC	LLC	TTFB
Key Idea	Secondary Capacitor	Turns Ratio Change	Turns Ratio Change	Resonant Inductance Variation	Resonant Tank Modification	Integrated Boost Converter	Integrated Boost Converter
1. Balanced Rectifier Stress	Unbalanced	Unbalanced	Balanced	Balanced	Balanced	Balanced	Balanced
2. Output Inductor Reduction	No	No	No	No	Yes	Yes	Yes
3. Output Current Ripple	Low	Low	Low	Low	High	High	Low
4. Additional Components	3	3	8	3	5	2	3
5. Conducting Components *	2	1	1	1	1	2	1
6. Control Complexity	Simple	Moderate	Simple	Moderate	Complex	Complex	Moderate
7. Extended Voltage Gain Range	No	Yes	Yes	No	Yes	Yes	Yes

* Conducting components: number of conducting semiconductor devices on the secondary side (nominal state).

presents a comparison between the proposed converter and previous works, highlighting the topological advantages and key contributions of this article. This subsection evaluates and compares various hold-up time compensation methods, based on the approaches discussed in Section 1, with a focus on the following key criteria:

• Balanced rectifier stress: Unbalanced voltage stress on rectifier diodes requires components with different voltage ratings. The rectifier diodes in the proposed converter are balanced, enabling optimized component selection.
• Output inductor reduction: An inductor is one of the most expensive and bulky components in a system. Eliminating it reduces system cost, improves power density, and simplifies circuit design. The proposed converter eliminates the output inductor, reducing the complexity while maintaining high performance.
• Output current ripple: A larger peak-to-peak output current increases the current stress on the power semiconductor devices and imposes more stringent design requirements on the output capacitors. Since one transformer also functions as the output inductor, the proposed converter mitigates the output current ripple without requiring an additional inductor.
• Additional components: To reduce the cost, the number of additional components should be minimized. The proposed converter introduces only three additional semiconductor devices.
• Conducting components: To achieve high efficiency, the number of conducting devices should be minimized. As the proposed converter uses a center-tap rectifier, only one diode conducts during the nominal state.
• Control complexity: A simplified control algorithm lowers hardware cost and reduces the time and effort required for design and verification. The proposed controller operates at a fixed switching frequency and applies PWM only to an auxiliary switch during the hold-up state, thereby maintaining a relatively low complexity.
• Extended voltage gain range: Extending the voltage gain range preserves output regulation over a wide input range and allows optimal selection of design parameters—such as the transformer turns ratio and device ratings—to achieve high efficiency.

3.8. Link Capacitor Design

$$T_H={\displaystyle \frac{\eta C_{Link}(V_{S,nom}^2-V_{S,\min }^2)}{2P_O}}$$

(25)

$$C_{Link}={\displaystyle \frac{2P_O{T}_H}{\eta (V_{S,nom}^2-V_{S,\min }^2)}}.$$

(26)

The proposed converter is designed to maintain the output voltage for at least 20 ms during input loss. Based on Equation (26), the required capacitance is 205 μF under 400 V nominal input, 250 V minimum input, 400 W output power, and 80% efficiency. Accordingly, a 270 μF input capacitor is selected, exceeding the calculated value.

3.9. Comparision with Other Topologies

• Power Loss Comparison

Figure 13 shows the power loss distribution of the LLC, TTFB, and proposed converters under nominal input voltage and full-load conditions. The LLC shows the highest loss of 47.79 W, mainly due to high diode losses. The TTFB reduces losses to 38.58 W with lower transformer and diodes losses. The proposed converter achieves the lowest total loss of 32.06 W by minimizing switch and diodes losses, demonstrating superior efficiency.

2.

Power Density Comparison

The power density was calculated based on the total volume of all components, including heat sinks. As shown in

Table 2. Comparison of power density across topologies.

Topology	LLC	TTFB	Prop.
Power Density [W/cm3]	3.64	3.02	4.62

, the proposed converter achieves the highest power density, followed by the LLC and TTFB converters. This indicates that the proposed converter offers superior space efficiency.

3.

Cost Comparison

Table 3. Cost comparison across topologies.

Topology	LLC	TTFB	Prop.
Total Cost	USD 17.4	USD 16.57	USD 19.53

Price for a 1000-set order.

presents the total cost for each converter. The TTFB converter has the lowest cost, while the proposed converter is the most expensive due to additional components. However, the improved performance and power density justify the higher cost.

4. Experimental Results

The effectiveness and feasibility of the proposed converter were verified under the following specifications: V_S = 250–400 V, V_S.nom = 400 V, V_o = 12 V, P_O.max = 400 W, f_sw = 70 kHz, and hold-up time T_H = 20 ms. An experimental comparison was conducted among the conventional converter 1 [25], conventional converter 2 [18], and the proposed converter.

Table 4. Components list of prototypes.

Components		Conventional 1 [25]	Conventional 2 [18]	Proposed
Switch	Q1–Q4	IPP60R160P7 (VDS = 650 V, RDS(on) = 160 mΩ)		IPP60R160P7 (VDS = 650 V, RDS(on) = 160 mΩ)
	Q5–Q6	–	IPP60R160P7 (VDS = 650 V, RDS(on) = 160 mΩ)	–
	Qa	–	–	IRFB7530PBF (VDS = 60 V, RDS(on) = 1.65 mΩ)
Diode	D1, D2	STPS40M80CT (VR = 80 V, VF = 0.475 V)		STPS40M60CT (VR = 60 V, VF = 0.385 V)
	Da1, Da2	–	–
Transformer	T1, T2	Lm.p = 300 μH, Llkg.p = 13 μH (Core:PQ3220)		Lm.p = 300 μH, Llkg.p = 14 μH (Core:PQ3220)
		Turns ratio (NP:NS) = 27:3		Turns ratio (NP:NS) = 42:3
		$N_P: 0.2$$\mathrm{mm}\times 9$ strands $N_S: 0.2$$\mathrm{mm}\times 150$ strands		$N_P: 0.2$$\mathrm{mm}\times 9$ strands $N_S: 0.2$$\mathrm{mm}\times 150$ strands
Inductor	La	–	100 μH (Core:PQ2020)	–
			$\mathrm{Wire}:0.2$$\mathrm{mm}\times 25$ turns

summarizes the components used in experiments. All transformer parameters were measured on the primary side.

Figure 14 and Figure 15 show the key waveforms of the prototype converters under nominal and hold-up states at full load conditions, respectively. As shown in Figure 14a, conventional converter 1 operates with a small duty ratio at a nominal input voltage of 400 V, resulting in a high RMS current. In conventional converter 2, the circulating current is reduced by utilizing inductor L_a, as shown in Figure 14b. However, voltage ringing is observed at the rectifier diodes due to the resonance between inductor L_a and the parasitic capacitors of switches Q₅ and Q₆. In contrast, the proposed converter minimizes primary-side RMS current by operating at the maximum duty ratio, as shown in Figure 14c. Additionally, rectifier diodes D₁ and D₂ experience reduced voltage stress, allowing the use of low-voltage-rated diodes. During the nominal state, the secondary-side switch Q_a remains off, and current flows only through D₁ and D₂.

Figure 15a shows the waveform of conventional converter 1 at the minimum input voltage. The duty ratio of the primary-side switches reaches its maximum value of 0.5, and the voltage across the rectifier diodes decreases accordingly. In conventional 2, during the hold-up state, switches Q₁ and Q₂ are kept off, while switches Q₃ to Q₆ operate, effectively performing the same function as conventional converter 1 during the hold-up state, as shown in Figure 15b. In the proposed converter, as shown in Figure 15c, the auxiliary switch Q_a operates during the hold-up state, resulting in increased voltage gain. During the operation when Q₁ and Q₄ are on, auxiliary diode D_a1 conducts together with Q_a when Q_a is turned on. When Q_a is turned off, D_a1 also turns off, and power is delivered to the output through D₁. Similarly, during the opposite half-cycle when Q₂ and Q₃ are on, D_a2 conducts with Q_a when Q_a is turned on, and turns off when Q_a is turned off, allowing power transfer through D₂.

Figure 16 presents the waveforms of the transient operation during the hold-up time. When AC loss occurs, the input voltage V_S begins to drop gradually. As the input continues to fall, the duty D increases and eventually reaches 0.5. After this point, the auxiliary switch Q_a is turned on to maintain a stable output voltage. Consequently, the output voltage is tightly regulated during the hold-up time.

Figure 17 presents the thermal image of the proposed converter under a full load condition with the minimum input voltage. As shown in Figure 17a, the secondary side exhibits a higher temperature than the primary side due to significant output current. In particular, as illustrated in Figure 17b, the auxiliary switch shows the highest temperature among the secondary-side components. This measurement was taken over a period longer than the actual hold-up time. Approximately 40 °C of heat is measured at the rectifier diodes, auxiliary diodes, and the transformers.

To ensure a fair and consistent evaluation, the performances of both the conventional and proposed converters were measured using the same experimental setup. The KEYSIGHT N8950A (Keysight Technologies, Santa Rosa, CA, USA) was employed as the input DC power supply, and the CHROMA 63204A (Chroma ATE Inc., Taoyuan, Taiwan) was used as the programmable output load. A YOKOGAWA WT1800 (Yokogawa Electric Corporation, Tokyo, Japan) power analyzer was used for power measurement, and waveform observation was conducted using a YOKOGAWA DLM2024 (Yokogawa Electric Corporation, Tokyo, Japan) oscilloscope with a 701929 current probe and 701978 differential probes. Digital control was implemented using a TMS320F28069M (Texas Instruments, Dallas, TX, USA) microcontroller, and AGILENT E3648A (Agilent Technologies, Santa Clara, CA, USA) provided the auxiliary low-voltage power supply.

Figure 18 presents a detailed comparison of the power losses in the main components of the three converter configurations under nominal input voltage and full load condition. To ensure a fair comparison, the converter in [18] was reconfigured with two series-connected transformers to match the structure of the proposed topology. Compared to the conventional converters, the proposed converter exhibits the lowest conduction loss in the primary-side switches due to a reduced circulating current. This is because, as the circulating current decreases, the drain-source RMS current flowing through the switches also reduces, effectively lowering the conduction loss in the proposed converter. In addition, the proposed transformer has a greater number of primary turns, which lowers flux density variation and thus reduces core loss. Furthermore, secondary-side conduction loss is also minimized by adopting low-voltage-rated diodes. As a result, the total power loss in the proposed converter is reduced by 6.5 W and 5.1 W compared to conventional converter 1 and 2, respectively.

Figure 19 shows the measured efficiency curves under nominal input condition. Although the proposed converter includes an additional MOSFET and two auxiliary diodes, these components do not conduct during the nominal state and, therefore, do not contribute to additional losses. Consequently, the proposed converter achieves higher efficiency than both conventional converters across the entire load range.

5. Conclusions

In this article, a new TTFB converter with a center-tap rectifier structure is proposed. Although conventional converters can be designed to operate at lower input voltages to ensure sufficient hold-up time compensation, this approach results in significant primary-side circulating current in the nominal state. The proposed converter integrates a boost stage with a single MOSFET and two auxiliary diodes, enabling operation at maximum duty ratio in the nominal state. As a result, the circulating current is effectively eliminated. Furthermore, by adopting a higher transformer turns ratio, the proposed converter enables the use of low-voltage-rated diodes. As a result, both primary- and secondary-side losses are significantly reduced. Moreover, as no additional losses are incurred in the nominal state, high efficiency is achieved. Furthermore, the proposed converter eliminates the need for an output inductor and maintains ZVS with a significantly lower leakage inductance. Experimental results confirmed peak efficiencies of 92.1% at 50% load under nominal conditions. It consistently outperforms traditional TTFB converters across the entire load range. Consequently, the proposed converter is a promising candidate for hold-up time applications requiring high efficiency.