Non-Isolated Ultra-High Step-Up DC-DC Converter Topology Using Coupled-Inductor-Based Inverting Buck-Boost and Voltage Multipliers

Abstract

This paper introduces a non-isolated ultra-high voltage gain topology using the combination of the coupled-inductor-based inverting buck-boost converter (IBB) and voltage multiplier (VM) structure. In the proposed converter, an ultra-high step-up voltage gain can be achieved with a small duty cycle thanks to a coupled inductor and VMs. The voltage stress and the losses of the switches in the proposed converter are even less than other conventional topologies. Unlike other coupled-inductor topologies, a large voltage spike caused by the leakage inductance of the coupled inductor is smoothed by the capacitor in the voltage multiplier. In addition, zero-voltage switching (ZVS) turn-on for the switches and zero-current switching (ZCS) turn-off for the diodes can be achieved with the energy stored in the leakage inductance. A 360 W (40 V/380 V) prototype converter is implemented to prove the advantages of the proposed converter, with a maximum efficiency of 98.4%.

1. Introduction

The urgent global shift toward renewable energy systems has brought about a critical need for efficient and robust high-step-up DC-DC converters. As photovoltaic (PV) modules and fuel cells (FCs) become increasingly central to distributed energy systems, their inherently low output voltage, typically ranging from 24 V to 48 V, presents a significant technical challenge. These voltages must be stepped up efficiently and safely to much higher levels, such as 380 V for single-phase or 700 V for three-phase grid-tie inverters, to interface with modern power grids and hybrid energy storage systems [1]. The performance and reliability of these converters directly impact the overall efficiency, cost, and lifetime of renewable energy installations, making their design and optimization a priority for researchers and industry alike.

Historically, isolated topologies such as flyback, forward, and push–pull converters have been employed to achieve high voltage gains by adjusting the transformer turns ratio. While these converters are capable of providing electrical isolation between input and output, which is sometimes essential for safety and noise immunity, they are plagued by several drawbacks. The high core losses associated with transformer-based designs, along with the bulkiness and weight of magnetic components, significantly limit their application in space-constrained, non-isolated scenarios. Furthermore, the need for multiple windings and a complex transformer construction increases manufacturing costs and reduces system reliability. These factors make isolated converters less attractive for applications where galvanic isolation is not strictly necessary [2].

In contrast, conventional non-isolated boost converters are widely used due to their simplicity, robustness, and ease of control. However, when high voltage gains are required, such as those needed to interface low-voltage renewable sources with high-voltage DC buses, these topologies face severe limitations. Specifically, achieving high gains necessitates operating at extreme duty cycles, often exceeding 80%. This leads to several undesirable effects: increased switching losses, elevated voltage stress across semiconductor devices, and significant efficiency degradation due to parasitic resistances in both active and passive components. The resulting voltage spikes and thermal stresses not only reduce the converter lifespan but also require the use of high-voltage-rated components, which are more expensive and less efficient. These limitations have motivated extensive research into alternative converter topologies that can deliver high step-up ratios with improved efficiency, reliability, and cost-effectiveness [3].

To address these challenges, recent research has focused on non-isolated high-step-up DC-DC converters, which can be broadly categorized into two main groups: single-inductor topologies and coupled-inductor topologies. Single-inductor topologies include interleaved boost and buck-boost converters, which utilize parallel converter stages to reduce current stress and improve the power handling capability [4,5,6]. While these designs offer improved performance over conventional boost converters, they require complex control strategies and additional components, increasing system complexity and cost. Switched-inductor and voltage-lift techniques represent other approaches, leveraging inductive and capacitive stacking to achieve moderate voltage gains [7,8,9,10,11,12]. However, these methods often result in an unbalanced voltage distribution across components, limiting their effectiveness in high-gain applications.

Voltage multiplier (VM) hybrids have emerged as a promising solution, combining diode–capacitor networks with conventional boost stages to achieve higher voltage gains [13,14,15]. These topologies can deliver gains beyond those achievable with single-stage designs, but cascading multiple stages to reach ultra-high ratios (e.g., 10× to 15×) inevitably increases the number of components, leading to higher conduction losses, a reduced power density, and an elevated system cost [13,14,15]. Despite these drawbacks, VM-based converters remain popular for their modularity and scalability.

Coupled-inductor topologies have gained significant attention for their ability to achieve high step-up ratios with fewer stages by exploiting magnetic coupling between inductors [16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37]. These converters can be designed with various winding configurations, allowing for a flexible voltage gain adjustment through the turns ratio. However, several persistent challenges limit their widespread adoption. First, high turns ratios are often required to achieve the desired voltage gain, which increases the winding resistance and leakage inductance. This not only reduces efficiency—often to below 92% at full load—but also necessitates larger magnetic cores, increasing the converter size and weight [16,17,18,19,20,21,22,23,24,25,26,27]. Second, leakage inductance induces significant voltage spikes during switching transitions, which can damage semiconductor devices and reduce system reliability. To mitigate these spikes, passive snubbers [16,17,18,19,20,21,22,23,24,25,26,27], active clamping circuits [28,29,30,31], and various clamp topologies have been proposed. While effective, these solutions add complexity and cost to the converter, and in the case of active snubbers, require additional control circuitry [28,29,30,31]. Recent advances in passive absorption techniques, such as resonant snubbers, have shown promise in simplifying spike mitigation and improving efficiency [38,39].

A third major challenge in coupled-inductor converters is the issue of hard-switching losses, which limit the maximum practical switching frequency and force the use of bulky passive components to maintain acceptable efficiency [21,23,24,26,28,29]. Switching techniques, such as zero-voltage switching (ZVS) and zero-current switching (ZCS), have been developed to address this problem by recovering leakage inductance energy and reducing switching losses. However, these methods often require additional auxiliary circuits, increasing system complexity and cost.

In addition to these technical challenges, many existing coupled-inductor topologies suffer from an asymmetrical voltage stress distribution, particularly in the output stage [16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,36,37]. For example, diodes in some designs must withstand voltage stresses approaching the full output voltage (~700 V), necessitating the use of expensive, high-voltage silicon carbide (SiC) devices. Similarly, output capacitors in certain topologies are subjected to stresses up to 1.5 times the output voltage, increasing their size and cost. These issues collectively limit the power density, efficiency, and cost-effectiveness of state-of-the-art high-step-up converters.

To overcome these limitations, this paper presents a novel voltage-double coupled-inductor boost converter that combines the benefits of coupled-inductor and voltage multiplier topologies while addressing their key drawbacks. The proposed converter achieves an ultra-high voltage gain (up to 10×) with a low turns ratio (n = 2), significantly reducing the winding resistance and leakage inductance compared to conventional designs (n = 5–6). Inherent leakage energy recovery is realized through resonant transitions, eliminating the need for external snubbers and simplifying the control strategy [38,39]. The symmetrical configuration of the converter ensures an even voltage stress distribution across all switches and diodes, with the maximum stress limited to less than half the output voltage. This allows the use of low-cost silicon (Si) components, further reducing the system cost and improving reliability. The converter also offers dual-mode flexibility, with the voltage gain adjustable through either the turns ratio or the number of cascaded voltage multiplier stages, supporting output voltages from 380 V to 800 V at moderate duty cycles (D < 0.5). Finally, the integration of the ZVS and ZCS operation reduces switching losses by up to 60% compared to conventional hard-switched designs, enabling efficiencies exceeding 95% at switching frequencies up to 150 kHz [40,41].

The remainder of this paper is organized as follows: Section 2 describes the operating principles and theoretical analysis of the proposed converter. Section 3 provides detailed design guidelines and component selection criteria. Section 4 presents the experimental results from a 500 W prototype, validating the performance and feasibility of the proposed topology. Section 5 compares the proposed converter with state-of-the-art designs, highlighting its advantages in terms of efficiency, power density, and cost. Section 6 concludes this paper and discusses potential directions for future research.

2. Proposed Converter Structure

2.1. Operating Principle

As shown in Figure 1, the proposed topology consists of two voltage multipliers (VM): a positive VM (which includes diodes $D_1$ and $D_2$ and capacitors $C_1$ and $C_s$) and a negative VM (which includes diodes $D_3$ and $D_4$ and capacitors $C_3$ and $C_D$) connected to the synchronous inverting buck-boost (IBB) converter. Moreover, the main inductor of the IBB is replaced by a coupled inductor. The secondary side of the coupled inductor is positioned along the common path between the blocking capacitors $C_s$ (positive VM) and $C_D$ (negative VM). This configuration not only enables ZVS turn-on for switches and ZCS turn-off for diodes but also enhances the overall voltage gain of the converter. In the proposed topology, the leakage inductance referred to the secondary side is used for the ZVS condition, and its energy is absorbed by blocking capacitors $C_s$ and $C_D$, eliminating the need for external snubbers. Furthermore, the symmetrical configuration ensures that the voltage stress and current stress are evenly shared among all output components. Consequently, low-cost, compact components with low voltage ratings can be used.

In this section, the working principle of the proposed converter is described in continuous conduction mode (CCM). From the key waveform shown in Figure 2, one switching cycle is divided into six modes, corresponding to the operational states of the main switches. The equivalent circuit for each mode is shown in Figure 3. In the proposed two-stage converter, the main switches and the synchronous rectifier switches are synchronized in operation. To describe the operating principle of the proposed converter, the following assumptions are made:

• Steady-state operation with a continuous magnetizing inductor current;
• Ideal components (parasitics neglected);
• Large capacitors maintain constant voltages during switching periods;
• Symmetrical capacitance values $C_1$ = $C_2$ = $C_3$ and $C_S$ = $C_D$;
• The switching period is $T_s$, where $S_1$ is closed for ${DT}_S$ and open for (1 − D) $T_s$.

The turns ratio N of the coupled inductor and the relationship between winding voltages are defined as follows:

$$N={\displaystyle \frac{N_2}{N_1}}, V_{L_2}={\displaystyle \frac{N_2}{N_1}}{V}_{L_1}$$

(1)

where $N_1$ and $N_2$ are the primary and secondary winding turns and $V_{L_1}$ and $V_{L_2}$ are the primary and secondary winding of the coupled inductor, respectively.

Based on the key waveforms shown in Figure 2, one switching cycle is divided into six modes, corresponding to the operational states of the main switches. The equivalent circuits for each mode are illustrated in Figure 3. The following paragraphs describe the operation in each mode.

Mode 1 ($t_1$-$t_2$)

Prior to $t_1$, $S_1$ is off, $D_1$ and $D_4$ are reverse-biased, and $S_2$, $D_2$, and $D_3$ conduct. At $t_1$, $S_2$ turns off, initiating the discharge of $S_1$ parasitic capacitor $C_{oss1}$. The coupled inductor begins charging. During this process, the charging of $S_2$ parasitic capacitor $C_{oss2}$ and the discharging of the leakage inductor $L_{LK2}$ elevate the voltage across $S_2$, forward-biasing the $S_1$ body diode to establish ZVS turn-on for $S_1$.

Mode 2 ($t_2$-$t_3$)

At $t_2$, $S_2$ is fully off: $C_{oss2}$ is charged and $C_{oss1}$ is discharged. $S_1$ turns on under the ZVS condition established in Mode 1. With S₁ fully conducting, its body diode reverse-biases, directing current through $S_1$ rather than its body diode. By $t_3$, $L_{LK2}$ fully discharges, reducing currents through $D_2$ and $D_3$ to zero and achieving ZCS turn-off for these diodes.

Mode 3 ($t_3$-$t_4$)

At $t_3$, $S_1$ remains on, and $S_2$ is off. The coupled inductor charges, forward-biasing $D_1$ and $D_4$ via the secondary winding voltage, while reverse-biasing $D_2$ and $D_3$. Capacitors $C_D$ and $C_1$ discharge, while $C_s$ charges. The leakage inductor $L_{LK2}$ stores energy during this interval.

Applying Kirchhoff’s Voltage Law (KVL), we obtain the following:

$$V_{L_1}=V_S,V_{L_2}=N{V}_{L_1}=N{V}_S$$

(2)

$$V_{C_S}+V_{L_2}=V_{C_1}+V_{L_{LK2}}$$

(3)

$$V_{L_1}+V_{L_2}+V_{C_2}=V_{C_D}+V_{L_{LK2}}$$

(4)

$$V_O=V_{C_1}+V_{C_2}+V_{C_3}+V_S$$

(5)

Using Kirchhoff’s Current Law (KCL), the leakage inductor current $I_{LLK2}$ is

$$I_{L_{LK2}}={\displaystyle \frac{C_1\Delta V_{C1}}{\left(t_4-t_3\right)}}+{\displaystyle \frac{V_{L_1}\left(t_4-t_3\right)}{N{L}_1}}+{\displaystyle \frac{C_2\Delta V_{C2}}{\left(t_4-t_3\right)}}$$

(6)

Since the output current ripple is very small and can be neglected, the voltage of capacitor $C_3$ can be considered constant. Then, the total ripple of the output voltage is only contributed by the voltage ripple of capacitors $C_1$ and $C_2$. Moreover, from the earlier assumption, capacitors $C_1$, $C_2$, and $C_3$ have the same value. Then, the leakage inductor current can be rewritten as follows:

$$I_{L_{LK2}\left(t_4-t_3\right)}={\displaystyle \frac{2C_1\Delta V_O}{\left(t_4-t_3\right)}}+{\displaystyle \frac{V_{L_1}\left(t_4-t_3\right)}{N{L}_1}}$$

(7)

The leakage inductor voltage during this mode is

$$V_{L_{LK2}\left(t_4-t_3\right)}={\displaystyle \frac{L_{LK2}d{i}_{L_{LK2}}}{dt}}={\displaystyle \frac{L_{LK2}\left(2C_O\Delta V_{O}N{L}_1+V_{L_1}(t_3-t_2{)}^2\right)}{(t_3-t_2{)}^{2}N{L}_1}}$$

(8)

Mode 4 ($t_4$-$t_5$)

At $t_4$, $S_1$ turns off, and $S_2$ turns on. $D_1$ and $D_4$ remain forward-biased, while $D_2$ and $D_3$ reverse-bias. S₂’s body diode conducts, discharging $C_{oss2}$ and charging $C_{oss1}$. The coupled inductor and $L_{LK2}$ discharge, reducing currents through $D_1$ and $D_4$ to enable ZCS turn-off. By $t_5$, $L_{LK2}$ fully discharges.

Mode 5 ($t_5$-$t_6$)

During this mode, energy from the coupled inductor core discharges into output capacitor $C_2$, while the blocking capacitor $C_D$ (negative VM) discharges into $C_3$. The leakage inductor $L_{LK2}$ charges after full discharge in Mode 3. Blocking capacitor C_S (positive VM) charges for the next cycle, with its voltage combining the input voltage, coupled inductor winding voltages, and the voltage drop across $L_{LK2}$. This configuration enhances the overall voltage gain without increasing component stress.

Using KVL, we obtain

$$V_L=V_{C_2},V_{L_2}=N{V}_{L_1}=N{V}_{C_2}$$

(9)

$$V_{L_1}+V_{L_2}+V_S=V_{C_S}+V_{L_{LK2}}$$

(10)

$$V_{C_D}+V_{L_2}=V_{C_3}+V_{L_{LK2}}$$

(11)

$$V_O=V_{C_1}+V_{C_2}+V_{C_3}+V_S$$

(12)

Mode 6 ($t_6$-$t_7$).

At $t_6$, the $C_2$ voltage exceeds the coupled inductor’s primary winding voltage, reverse-biasing S₂’s body diode. Current flows through S₂ instead. By $t_7$, the switching cycle completes, resetting the system for the next cycle.

The leakage inductor $L_{LK2}$ is charged in the whole time of Mode 5 and Mode 6. Similar to Mode 3, the current $I_{LLK2}$ flow through the leakage inductor $L_{LK2}$ can be calculated with Equation (13) using KCL.

The leakage inductor the current $I_{LLK2}$ during $t_7-t_5$ is

$$I_{{L_{LK2}}_{\left(t_{7 }-t_5\right)}}={\displaystyle \frac{2C_1\Delta V_o}{\left(t_7-t_5\right)}}+{\displaystyle \frac{V_{L_1}\left(t_7-t_5\right)}{N{L}_1}}$$

(13)

And the leakage inductor $L_{LK2}$ voltage is

$$V_{L_{LK2}\left(t_7-t_5\right)}={\displaystyle \frac{L_{LK2}d{i}_{L_{LK2}}}{dt}}={\displaystyle \frac{L_{LK2}\left(2C_O\Delta V_{O}N{L}_1+V_{L_1}(t_7-t_5{)}^2\right)}{(t_7-t_5{)}^{2}N{L}_1}}$$

(14)

2.2. Steady-State Analysis of the Proposed Converter

2.2.1. Voltage Gain and Voltage Stress on Components

Mode 1, Mode 2, and Mode 4 occur transiently and are negligible in a steady-state analysis. Thus, the effective intervals are the ($t_2-t_4$) active period (${DT}_S$) and ($t_7-t_5$) inactive period $\left(1-D\right)T_S$.

Applying the volt-second balance to the primary winding of coupled inductor results in

$${\overline{V}}_{L_1}=D{V}_S-\left(1-D\right)V_{C_2}=0$$

(15)

$${\overline{V}}_{L_1}=D{V}_S-\left(1-D\right)\left(V_{C_S}+V_{L_{LK2}\left(t_7-t_5\right) }-N{V}_{C_2}-V_S\right)=0$$

(16)

$${\overline{V}}_{L_1}=D\left(V_{C_D}+V_{L_{LK2\left(t_4-t_3\right)}}-N{V}_S-V_{C_2}\right)-\left(1-D\right)V_{C_2}=0$$

(17)

$$V_O=V_{C_1}+V_{C_2}+V_{C_3}+V_S$$

(18)

Solving these equations yields the following capacitor voltages:

$$V_{C_2}={\displaystyle \frac{D{V}_S}{1-D}}$$

(19)

$$V_{C_D}=\left(N+{\displaystyle \frac{1}{1-D}}\right)V_S-{\displaystyle \frac{L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}(D{T}_s{)}^2\right)}{N{L}_1(D{T}_s{)}^2}}$$

(20)

$$V_{C_S}=\left({\displaystyle \frac{1+ND}{1-D}}\right)V_S-{\displaystyle \frac{L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}\left(\right(1-D)T_s{)}^2\right)}{N{L}_1\left(\right(1-D)T_s{)}^2}}$$

(21)

$$\begin{gathered} V_{C_1}=V_{C_3}=\left({\displaystyle \frac{1+N}{1-D}}\right)V_S-{\displaystyle \frac{L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}\left(\right(1-D)T_s{)}^2\right)}{N{L}_1\left(\right(1-D)T_s{)}^2}} \\ -{\displaystyle \frac{L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}(D{T}_s{)}^2\right)}{N{L}_1(D{T}_s{)}^2}} \end{gathered}$$

(22)

The output voltage equation is

$$\begin{gathered} V_o=\left({\displaystyle \frac{3+2N}{1-D}}\right)V_S-{\displaystyle \frac{2L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}\left(\right(1-D)T_s{)}^2\right)}{N{L}_1\left(\right(1-D)T_s{)}^2}} \\ -{\displaystyle \frac{2L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}(D{T}_s{)}^2\right)}{N{L}_1(D{T}_s{)}^2}} \end{gathered}$$

(23)

Voltage gain (M) is

$$\begin{gathered} M={\displaystyle \frac{V_o}{V_S}}=\left({\displaystyle \frac{3+2N}{1-D}}\right)-{\displaystyle \frac{2L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}\left(\right(1-D)T_s{)}^2\right)}{N{L}_1\left(\right(1-D)T_s{)}^2}} \\ -{\displaystyle \frac{2L_{LK2}\left(2C_1\Delta V_{o}N{L}_1+V_{L_1}(D{T}_s{)}^2\right)}{N{L}_1(D{T}_s{)}^2}} \end{gathered}$$

(24)

And voltage stress on semiconductors is

$$V_{S_1}=V_{S_2}={\displaystyle \frac{V_S}{1-D}}$$

(25)

$$V_{D_1}=V_{D_2}=V_{D_3}=V_{D_4}=V_{C_1}=V_{C_3}$$

(26)

Equation (25) demonstrates that the voltage gain is determined by both the voltage multiplier (VM) stages and the coupled inductor’s turns ratio (N). This enables the flexible achievement of an ultra-high voltage gain through either cascading additional VM stages, increasing the turns ratio, or a combination of both strategies. Equation (25) further reveals a symmetrical voltage stress distribution across components, ensuring that output diodes and capacitors operate at low stress levels ($<0.5\times V_O$), a direct benefit of the converter’s symmetrical configuration.

2.2.2. ZVS Condition

To achieve ZVS turn-on for $S_1$, the voltage across leakage inductor $L_{LK2}$ during discharge must satisfy the following:

$$V_{L_{LK2}}-V_{C_S}-V_{L_2} \ge 0$$

(27)

$$V_{L_2}=N{V}_{L_1}=N{V}_S$$

(28)

where Equation (28) is the secondary winding voltage.

The voltage across $I_{LK2}$ is determined by its current change rate. During Mode 1, $I_{LK2}$ fully discharges, yielding

$$\Delta I_{LK2}=I_{LK2\left(t_1\right)}-0$$

(29)

Here, $I_{LK2\left(t_1\right)}$ corresponds to the leakage inductor current at $t_7$ from the previous switching cycle:

$$I_{LK{2}_{\left(t_1\right)}}=I_{LK{2}_{\left(t_7-t_5\right)}}$$

(30)

Then, the ZVS condition equation can be expressed as follows:

$${\displaystyle \frac{L_{LK2}\Delta I_{{L_{LK2}}_{\left(t_7-t_5\right)}}}{T_r}} \ge V_{C_S}+N{V}_S$$

(31)

From Equations (14) and (31), the minimum leakage inductance is

$$L_{LK2} \ge {\displaystyle \frac{\left(V_{C_S}+N{V}_S\right)T_r}{\Delta I_{{L_{LK2}}_{\left(t_7-t_5\right)}}}}={\displaystyle \frac{\left(t_7-t_5\right)N{L}_1\left(V_{C_S}+N{V}_S\right)T_r}{2C_1\Delta V_{o}N{L}_1+V_{L_1}(t_7-t_5{)}^2}}$$

(32)

Recognizing ($t_7$ − $t_5$) = $\left(1-D\right)T_S$, this simplifies to

$$L_{LK2} \ge {\displaystyle \frac{\left(1-D\right)T_{s}N{L}_1\left(V_{C_S}+N{V}_S\right)T_r}{2C_1\Delta V_{o}N{L}_1+V_{L_1}\left(\right(1-D)T_s{)}^2}}$$

(33)

where $T_r$ is the resonant discharge time of the secondary side leakage inductor $L_{LK2}$.

In practical implementations, parasitic parameters such as the output capacitance of MOSFETs, the junction capacitance of diodes, and the equivalent series resistance (ESR) of capacitors and inductors significantly influence soft-switching behavior. For instance, the MOSFET output capacitance helps facilitate ZVS turn-on by temporarily storing energy, but excessive parasitic capacitance can prolong the resonant transition time and require a longer dead time, compromising efficiency. Similarly, ESR in capacitors or leakage paths may lead to incomplete discharge of the leakage inductor current, degrading ZCS conditions for diodes. Therefore, a careful selection of components with optimized parasitic, particularly low ESR capacitors and fast-recovery diodes, is essential to maintain reliable soft-switching performance across the operating range.

2.3. Converter Operation and Analysis

The proposed converter operates in continuous conduction mode (CCM) under full-load conditions (360 W), as confirmed by experimental inductor current waveforms showing uninterrupted flow. CCM is preferred for high-power applications like this design because it minimizes peak currents, reducing component stress (critical for MOSFETs and diodes at 360 W) and lowering conduction losses. While discontinuous conduction mode (DCM) exhibits higher efficiency at light loads, its 60% larger peak currents would necessitate oversized components and increase EMI challenges at the studied power level. CCM also simplifies control stability due to its predictable second-order dynamics and reduces output voltage ripple (±1.2% measured), making it suitable for precision loads. The converter transitions to DCM only below 20% load (72 W), optimizing light-load efficiency without compromising full-load performance. This hybrid operation synergizes with the soft-switching design: ZVS/ZCS mitigates CCM’s traditional switching loss drawback, enabling 98.4% peak efficiency while maintaining thermal reliability.

3. Design of the Proposed Converter

3.1. Design of the Output Capacitors

The output capacitors are designed based on the maximum allowable output voltage ripple $\Delta V_O$:

$$C_{Oeq} \ge {\displaystyle \frac{I_{O}D}{f_S\times \Delta V_O}}$$

(34)

where $f_S$ is switching frequency, $I_o$ is the output current, and $C_{Oeq}$ is the equivalent output capacitor, derived as

$$C_{Oeq}={\displaystyle \frac{C_1{C}_2{C}_3}{C_1{C}_2+C_2{C}_3+C_3{C}_1}}$$

(35)

For symmetrical operation, all output capacitors are identical:

$$C_1=C_2=C_3=3C_{Oeq} \ge {\displaystyle \frac{3I_{O}D}{f_{SW}\times \Delta V_O}}$$

(36)

The leakage inductor is $L_{LK2}$, duty cycle is D, and the dead time is $T_d$.

Firstly, the minimum duty cycle $D_{min}$ can be calculated from the required voltage gain in the case when the leakage inductor $L_{LK2}$ equals zero.

$$D_{min}=1-\left(3+2N\right){\displaystyle \frac{V_S}{V_O}}$$

(37)

The voltage of the blocking capacitor $C_s$ in the case of the minimum duty cycle $D_{min}$ can be calculated as follows:

$$V_{{C_S}_{D_{min}}}=\left({\displaystyle \frac{1+N{D}_{min}}{1-D_{min}}} \right)V_s$$

(38)

Using Equations (18) and (23), the minimum required value of leakage inductor $L_{LK2}$ can be calculated with an assumption that the discharging time $T_r$ is equal to the deadtime $T_d$ of switches.

Once a value is selected for the leakage inductor $L_{LK2}$, the appropriate duty cycle can be determined from the output voltage equation shown in Equation (11).

It should be noted that if the leakage inductance is too large, the voltage gain will be significantly reduced. Moreover, $S_1$ must be turned on before the leakage inductor $L_{LK2}$ gets fully discharged, and then the dead time $T_d$ of switches must be shorter than the discharge time $T_r$ of leakage inductor $L_{LK2}$ to maintain ZVS condition.

In Mode 1, since the body diode of $S_1$ and $D_2$ are forward-biased, the leakage inductor $L_{LK2}$ will resonate with capacitor $C_s$. To maintain the ZVS condition, the resonant frequency must be much smaller than the switching frequency. Moreover, as an assumption before, the capacitors $C_s$ and $C_D$ have the same value to keep the symmetrical configuration; those values can be calculated using Equation (39).

$$C_S=C_D \gg {\displaystyle \frac{1}{(2\pi f_S{)}^2{L}_{LK2}}}$$

(39)

3.2. Design of the Main Inductor

The magnetizing inductance of coupled inductors is designed to operate the proposed converter in CCM mode. Then, its value can be calculated using Equation (40):

$$L_m \ge {\displaystyle \frac{V_{S}D}{\Delta I_{L_m}{f}_{SW}}}$$

(40)

where $\Delta I_{L_m}$ is the current ripple of the magnetizing inductor $L_m$.

Then, the primary inductance $L_1$ and secondary inductance $L_2$ are then determined using Equation (41):

$$L_1=L_m+L_{LK1}$$

(41)

$$L_2=N^2{L}_1$$

(42)

4. Experimental Results

To validate the proposed converter, a 360 W, 380 V prototype was built and tested using a photovoltaic module (Hyundai RI Series, 360 W, 72-cell). The specifications of the converter are presented in

Table 1. Specifications of the proposed converter.

Parameter	Designator	Value
Input voltage	$V_S$	40 V
Output voltage	$V_O$	380 V
Maximum output voltage ripple	$\Delta V_O$	0.8%
Output power	$P_O$	360 W
Switching frequency	$f_{SW}$	100 KHz

, and the component details are summarized in

Table 2. Specifications of the components used in the proposed converter.

Component	Part #	Specification
MOSFETs	IPP039N10N5	200 V/80 A
$\mathrm{Diodes} (D_1–D_4$)	DSSK10-18A	180 V/10 A
$\mathrm{Capacitors} C_2$	106MMR250K	10 µF/250 V
Coupled inductor turns ratio	――	17:18
$\mathrm{Leakage} \mathrm{inductance} L_{LK2}$	――	4.5 µH
$\mathrm{Primary} \mathrm{inductance} L_1$	――	103 µH
$\mathrm{Secondary} \mathrm{inductance} L_2$	――	115 µH

.

In the experimental setup, the gate signals $V_{GS1}$ and $V_{GS2}$ were generated using a TMS320F28335 DSP. The physical prototype is shown in Figure 4. All through-hole components were mounted on the top side of the PCB, while the gate driver circuits were placed on the bottom side. All capacitors used were film capacitors to ensure a low ESR.

The main MOSFET $S_1$ operated with a duty cycle of 0.52 to boost the input voltage from 40 V to an output of 380 V. The dead time between the two switches was set to 100 ns.

Figure 5 displays the experimental waveforms under full load. In Figure 5a, switch $S_1$ clearly turns on under ZVS. In Figure 5b, the body diode of $S_2$ is initially forward-biased during the early part of its conduction period (Mode 4) and later reverse-biased when the current reverses direction (Mode 5). Figure 5c,d show the voltage and current waveforms of the output diodes, confirming that all diodes are turned off under ZCS.

Figure 6 shows the waveforms under light-load conditions (20% load). Even at a reduced load, the converter maintains ZVS turn-on for the switches and ZCS turn-off for the diodes. These results confirm the reliable soft-switching performance across the full load range. Minor current oscillations observed during switch-off periods are due to small snubber capacitors added to mitigate hot-loop issues in the half-bridge layout.

In Figure 7, the output capacitor voltages are shown. Due to the symmetric configuration, capacitors $C_1$ and $C_3$ (from the voltage multipliers) maintain equal voltages. Capacitor $C_2$, which is part of the IBB output, shows a slightly lower voltage due to the small duty cycle. Figure 7b reveals interleaved charging between $C_1$ and $C_2$, resulting in ripple cancellation and thus a reduced overall output voltage ripple—allowing smaller capacitance values to be used effectively.

The experimental waveforms in Figure 8a demonstrate precise synchronization between switch and diode operations. The zoomed-in view in Figure 8b shows that $S_1$ turns on approximately 160 ns before diodes $D_1$ and $D_4$ conduct and $D_2{ \mathrm{and} D}_3$ turn off, exceeding the 100 ns dead time. This timing ensures both ZVS for $S_1$ and ZCS for the diodes, as discussed in Section 2.

Figure 9 presents the measured voltages of the coupled inductor windings and the current through the leakage inductor. High voltage spikes in the secondary side, caused by discharging of the leakage inductor $L_{LK2}$, are visible just before the polarity reversal of the coupled inductor, a critical behavior needed for reliable soft switching.

Finally, Figure 10 shows the measured efficiency curve using a Xitron 2802 power analyzer. The converter achieves 97% efficiency at a light load (20%) and 96% at full load (360 W). A peak efficiency of 98.4% is observed at a 150 W output.

Based on the theoretical analysis and experimental results from the 360 W prototype, the peak stresses occur under full-load operation, as shown in

Table 3. Peak stresses on components under full-load operation.

Component	Peak Voltage Stress	Peak Current Stress	Relative to Output
MOSFETs (S1, S2)	VS/(1 − D) = 83.3 V	ILm + ΔILm/2	0.22 × VO
Diodes (D1–D4)	VC1 = VC3 ≈ 127 V	IO/2 ≈ 0.47 A	0.33 × VO
Output Capacitors (C1–C3)	127 V each	Ripple current	0.33 × VO
Coupled Inductor	Primary: 40 V Secondary: 42 V	Peak magnetizing current	-

.

The symmetrical configuration ensures that voltage stresses remain well below 50% of the output voltage, enabling the use of lower-rated, more cost-effective components.

Thermal management is essential for the reliable operation of power converters, especially at higher power levels. For MOSFETs, the junction temperature TJTJ increases with power dissipation and total thermal resistance, following the relationship $T_J=T_A+P_D\times ({\theta }_{JC}+{\theta }_{CS}+{\theta }_{SA})$. The coupled inductor’s temperature rises due to core and copper losses, influenced by its thermal design and mounting configuration. To ensure long-term reliability, it is recommended to derate components by operating at 70–80% of their maximum power rating, selecting devices with voltage ratings at least 150% of the expected stress, and reducing the output power when ambient temperatures exceed approximately 70 °C. The component lifetime is strongly affected by temperature: for electrolytic capacitors, the lifetime approximately halves for every 10 °C rise above the rated temperature, as described by $L=L_0\times 2^{(T_0-T_a)/10}$, while for semiconductors, keeping the junction temperature below 105 °C helps achieve a long lifespan. Reliability can be further enhanced through effective cooling, choosing components with higher temperature ratings and lower thermal resistance, maintaining stable ambient conditions, and leveraging soft-switching techniques, which reduce thermal stress and extend the component lifetime compared to hard-switching designs.

4.1. Losses and Efficiency Analysis

The main sources of power loss in the proposed converter were analyzed to understand the efficiency characteristics. MOSFET conduction losses are calculated as $P_{cond}=I_{rms}^2\times R_{DS\left(on\right)}$ while switching losses are given by $P_{sw}=f_s\times V\times I\times t_{sw}$. Diode losses are estimated as $P_{diode}=V_F\times I_{avg}$. Inductor losses include the core loss $P_{core}=k\times f^{\alpha }\times B^{\beta }\times V_{core}$ and copper loss ($I_{rms}^2\times R_{ac}$). Capacitor losses are calculated as $ESR{P}_{ESR}=I_{rms}^2$.

Table 4. Estimated loss distribution of components at full-load operation.

Component	Loss Type	Equation	Contribution (%)
MOSFETs (S1, S2)	Conduction	$P_{cond}=I_{rms}^2\times R_{DS\left(on\right)}$	45%
	Switching	$P_{sw}=f_s\times V\times I\times t_{sw}$	15%
Diodes (D1–D4)	Conduction	$P_{diode}=V_F\times I_{avg}$	5%
Coupled Inductor	Core Loss	$P_{core}=k\times f^{\alpha }\times B^{\beta }\times V_{core}$	20%
	Copper Loss	$P_{copper}=I_{rms}^2\times R_{ac}$	10%
Capacitors (C1–C3)	ESR Loss	$ESR{P}_{ESR}=I_{rms}^2$	5%

summarizes the estimated loss distribution at full load, showing that MOSFET and inductor losses are dominant. This analysis supports the measured efficiency curves, confirming that ZVS and ZCS operation significantly reduces switching losses and contributes to the high overall efficiency.

4.2. Scalability Considerations for High Power

While the experimental prototype operates efficiently at 360 W, its extension to higher power levels poses several engineering challenges. Increased current levels demand power devices with a lower $R_{DS\left(on\right)}$ and higher thermal handling capacity. Passive components, especially inductors and capacitors, must be carefully rated to avoid core saturation and overheating. Thermal design becomes crucial to maintain reliability, necessitating advanced heat dissipation techniques such as thermal vias, heat sinks, or active cooling. Moreover, as switching power increases, EMI emissions may rise, requiring better layout, shielding, and EMI filtering techniques to comply with EMC standards. These factors must be considered in any high-power implementation of the proposed topology.

5. Comparison Study

A comparative analysis between the proposed converter and several recent topologies is presented in

Table 5. Comparison of the proposed converter with other existing topologies.

Topology	Voltage Gain $\mathit{M}=\frac{{\mathit{V}}_{\mathit{O}}}{{\mathit{V}}_{\mathit{i}\mathit{n}}}$	Voltage Stress on Switches (Vs/Vin)	Voltage Stress on Diodes $({\mathit{V}}_{\mathit{D}\mathit{m}\mathit{a}\mathit{x}}/{\mathit{V}}_{\mathit{i}\mathit{n}})$	Voltage Stress on Output Capacitors $({\mathit{V}}_{\mathit{C}\mathit{o}}/{\mathit{V}}_{\mathit{i}\mathit{n}})$	Conduction Mode	Soft-Switching Status	S/D/CI/I/C/T	Efficiency
[23]	$(1+2 \mathrm{kN})\left({\displaystyle \frac{1}{D(1-D)}}-2\right)$	${\displaystyle \frac{1}{(2\mathrm{N}+1)}}$	${\displaystyle \frac{2\mathrm{N}}{(2\mathrm{N}+1)}}$	NI	CCM	ZVS for MOSFETs, ZCS for diodes	2/3/2/0/5/12	96.5%
[28]	${\displaystyle \frac{D\left(N-1\right)+N+2}{\left(1-D\right)}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{N+1}{1-D}}$	${\displaystyle \frac{2}{1-D}}$	CCM	ZVS (switch) and ZCS (diode) via active clamp	2/3/1/1/5/12	96.8%
[18]	${\displaystyle \frac{1+\left(N+1\right)D}{\left(1-D\right)}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{N+1}{1-D}}$	${\displaystyle \frac{1+\left(N+1\right)D}{\left(1-D\right)}}$	CCM	None	1/2/1/1/3/8	94.1%
[21]	${\displaystyle \frac{1+N\left(1-D\right)}{1-2D}}$	${\displaystyle \frac{1}{1-2D}}$	${\displaystyle \frac{N}{1-2D}}$	${\displaystyle \frac{N\left(1-D\right)}{1-2D}}$	CCM	ZVS (switches) and ZVZCS (diodes)	2/2/1/1/4/10	95.6%
[24]	${\displaystyle \frac{2+2N}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{1+N}{1-D}}$	NI	CCM	None	2/6/2/0/6/16	96.7%
[16] (Figure 4a)	${\displaystyle \frac{2+N+DN}{(1-D{)}^2}}$	${\displaystyle \frac{1}{(1-D{)}^2}}$	${\displaystyle \frac{N+1}{(1-D{)}^2}}$	${\displaystyle \frac{N+1}{(1-D{)}^2}}$	CCM and DCM	None	1/6/1/1/5/14	94.4%
[22]	${\displaystyle \frac{2+2N}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{1+N}{1-D}}$	${\displaystyle \frac{1+2N-ND}{1-D}}$	CCM	ZCS (switch) only	1/4/1/0/4/10	97.1%
[30] (Figure 6b)	${\displaystyle \frac{N+1}{1-2D}}$	${\displaystyle \frac{1}{1-2D}}$	NI	${\displaystyle \frac{N}{1-2D}}$	CCM	None	1/4/1/1/5/12	95%
[25] (Figure 4)	${\displaystyle \frac{N+2}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{N+1}{1-D}}$	${\displaystyle \frac{N+2}{1-D}}$	CCM	None	1/3/1/0/3/8	96.4%
[19]	${\displaystyle \frac{N+2+D}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{N+1}{1-D}}$	${\displaystyle \frac{N+2+D}{1-D}}$	CCM	None	1/4/1/1/5/12	96.2%
[20]	${\displaystyle \frac{4+N\left(2-D\right)-D}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{N\left(2-D\right)-D}{1-D}}$	${\displaystyle \frac{4+N\left(2-D\right)-D}{1-D}}$	CCM	None	1/8/1/0/8/18	97.6%
[31]	${\displaystyle \frac{2\left(1+N\right)}{1-D}}$	${\displaystyle \frac{1}{1-D}}$	${\displaystyle \frac{\left(1+N\right)}{1-D}}$	${\displaystyle \frac{\left(1+N\right)}{1-D}}$	CCM	ZVS for main and clamp switches; ZCS on diodes	2/4/1/0/5/12	96.3%
[33]	${\displaystyle \frac{(N^2+(1+N\left)\right(3+D)}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{1}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{\left(2+N\right)}{{\left(1-D\right)}^2}}$	NI	CCM	None	2/5/2/5/14	95.2%
[34]	${\displaystyle \frac{2+2N+ND\left(1-D\right)}{\left(1-D^2\right)}}$	${\displaystyle \frac{1}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{N\left(2-D\right)}{\left(1-D\right)}}$	${\displaystyle \frac{\left(1+2N-ND\right)}{2+2N+ND\left(1-D\right)}}$	CCM	None	2/5/1/1/5/14	94.2%
[35]	${\displaystyle \frac{5-2ND+4N-D}{\left(1-D\right)}}$	${\displaystyle \frac{1}{\left(1-D\right)}}$	${\displaystyle \frac{K\left(N+1\right)}{1-D}}$	NI	CCM	ZCS on diodes only	2/8/2/0/8/20	94.6%
[36]	${\displaystyle \frac{1+N+D}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{1}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{1+N}{{\left(1-D\right)}^2}}$	${\displaystyle \frac{1+N}{1+N+D}}$	CCM	None	2/4/2/0/4/12	94.4%
[37]	${\displaystyle \frac{\left(\left(8N+2\right)+2D\left(1-4N\right)\right)}{\left(1-D\right)}}$	${\displaystyle \frac{3\left(1-D\right)}{\left(8N+2\right)+2D\left(1-4N\right)}}$	${\displaystyle \frac{N\left(4-3D\right)}{(\left(4\mathrm{N}+1)+\mathrm{D}(1-4\mathrm{N})\right)}}$	NI	CCM	None	2/5/3/0/5/15	95.96%
Proposed converter	(24)	${\displaystyle \frac{1}{1-D}}$	(22)	(22)	CCM	ZVS for switches, ZCS for diodes	2/4/2/0/5/13	98.4%

With S/D/CI/I/C/T, switch/diode/coupled inductor/single inductor/capacitor/total; N, turns ratio of the coupled inductor; NI, no information.

. The comparison considers critical metrics such as voltage gain, voltage stress on switches and diodes, capacitor voltage stress, component count, and efficiency.

As seen in Table 5, the proposed converter offers several key advantages:

• It achieves the highest efficiency (98.4%), outperforming all other referenced converters;
• The voltage stress on both switches and diodes is significantly lower due to the symmetrical configuration of the proposed design;
• The number of components—including switches, diodes, coupled inductors, and capacitors—is moderate, contributing to a lower cost and simplified implementation;
• The output capacitor and diode stress is substantially reduced (to less than 0.5× output voltage), eliminating the need for expensive high-voltage components.

Figure 11a illustrates the theoretical voltage gain of the proposed converter compared with other topologies, assuming a coupled inductor turns ratio of 1.05. Although some converters from [16,21,33,35,36,37] achieve higher voltage gains, they do so at the cost of greater voltage stress and lower efficiency.

For example, the topologies in [16,33] involve complex structures with a high number of passive and active components, leading to higher conduction losses and a larger size. Similarly, the converters in [21,33] operate in a narrow duty cycle range (typically between 0.1 and 0.5), which becomes problematic under high-load conditions. As the duty cycle increases, the current stress rises, reducing overall efficiency.

In contrast, the proposed converter maintains a high efficiency across a wide load range, while keeping voltage stress and the component count low.

Figure 11b further compares the theoretical maximum voltage stress on the output diodes across different converters. The proposed converter demonstrates significantly reduced stress, confirming its suitability for applications that demand compact, efficient, and reliable high step-up conversion.

6. Conclusions

In this paper, an ultra-high step-up converter using a coupled inductor with low voltage stress on components and high efficiency while achieving a high step-up voltage gain characteristic is proposed. The proposed topology is advantageous in terms of the following features:

• No spike voltage is applied to semiconductor devices and hence there is no need for an extra snubber;
• Very high efficiency with ZVS turn-on for MOSFET and ZVZCS for diodes;
• Reduced voltage stress on the components due to the symmetric configuration;
• Easy to obtain a higher voltage gain by either choosing the turns ratio of the coupled inductor, duty cycle, or cascading more VM stages.

The proposed converter can be a very good choice for ultra-high voltage step-up applications, such as the distributed power generation systems with renewable energy sources, which requires a high voltage gain without using a transformer.