Search Results (44)

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

This paper investigates the performance of vacuum gate dielectric doping-free carbon nanotube/nanoribbon field-effect transistors (VGD-DL CNT/GNRFETs) via computational analysis employing a quantum simulation approach. The methodology integrates the self-consistent solution of the Poisson solver with the mode space non-equilibrium Green’s function (NEGF) in the ballistic limit. Adopting the vacuum gate dielectric (VGD) paradigm ensures radiation-hardened functionality while avoiding radiation-induced trapped charge mechanisms, while the doping-free paradigm facilitates fabrication flexibility by avoiding the realization of a sharp doping gradient in the nanoscale regime. Electrostatic doping of the nanodevices is achieved via source and drain doping gates. The simulations encompass MOSFET and tunnel FET (TFET) modes. The numerical investigation comprehensively examines potential distribution, transfer characteristics, subthreshold swing, leakage current, on-state current, current ratio, and scaling capability. Results demonstrate the robustness of vacuum nanodevices for high-performance, radiation-hardened switching applications. Furthermore, a proposal for extrinsic enhancement via doping gate voltage adjustment to optimize band diagrams and improve switching performance at ultra-scaled regimes is successfully presented. These findings underscore the potential of vacuum gate dielectric carbon-based nanotransistors for ultrascaled, high-performance, energy-efficient, and radiation-immune nanoelectronics. Full article

In this study, we investigated the influence of quasi-one-dimensional (Quasi-1D) characteristics on the source and drain contact resistances within vertical nanowire (NW) field-effect transistors (FETs) of diminutive diameter. The top contact of the NW is segregated into two distinct regions: the first encompassing the upper surface, designated as the axial contact, and the second encircling the side surface, known as the radial contact, which is formed during the top-contact metal deposition process. Quantum confinement effects, prominent within Quasi-1D NWs, exert significant constraints on radial transport, consequently inducing a noticeable impact on contact resistance. Notably, in the radial direction, electron tunneling occurs only through quantized, discrete energy levels. Conversely, along the axial direction, electron tunneling freely traverses continuous energy levels. In a meticulous numerical analysis, these disparities in transport mechanisms unveiled that NWs with diameters below 30 nm exhibit a markedly higher radial contact resistance compared to their axial counterparts. Furthermore, an increase in the overlap length (less than 5 nm) contributes to a modest reduction in radial resistance; however, it remains consistently higher than the axial contact resistance. Full article

A new structure for PNPN tunnel field-effect transistors (TFETs) has been designed and simulated in this work. The proposed structure incorporates the polarity bias concept and the gate work function engineering to improve the DC and analog/RF figures of merit. The proposed device consists of a control gate (CG) and a polarity gate (PG), where the PG uses a dual-material gate (DMG) structure and is biased at −0.7 V to induce a P⁺ region in the source. The PNPN structure introduces a local minimum on the conduction band edge curve at the tunneling junction, which dramatically reduces the tunneling width. Furthermore, we show that incorporating the DMG architecture further enhances the drive current and improves the subthreshold slope (SS) characteristics by introducing an additional electric field peak. The numerical simulation reveals that the electrically doped PNPN TFET using DMG improves the DC and analog/RF performances in comparison to a conventional single-material gate (SMG) device. Full article

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell. Full article

Silicon (Si) nano-electronics is advancing towards the end of the Moore’s Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors. In the nanostructures that act as channels in transistors or depletion layers in pn diodes, the role of dopants becomes critical, since the transport properties depend on a small number of dopants and/or on their random distribution. Here, we present the possibility of single-charge tunneling in codoped Si nanodevices formed in silicon-on-insulator films, in which both phosphorus (P) donors and boron (B) acceptors are introduced intentionally. For highly doped pn diodes, we report band-to-band tunneling (BTBT) via energy states in the depletion layer. These energy states can be ascribed to quantum dots (QDs) formed by the random distribution of donors and acceptors in such a depletion layer. For nanoscale silicon-on-insulator field-effect transistors (SOI-FETs) doped heavily with P-donors and also counter-doped with B-acceptors, we report current peaks and Coulomb diamonds. These features are ascribed to single-electron tunneling (SET) via QDs in the codoped nanoscale channels. These reports provide new insights for utilizing codoped silicon nanostructures for fundamental applications, in which the interplay between donors and acceptors can enhance the functionalities of the devices. Full article

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 10¹³. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications. Full article

Biosensors based on tunnel FET for label-free detection in which a nanogap is introduced under gate electrode to electrically sense the characteristics of biomolecules, have been studied widely in recent years. In this paper, a new type of heterostructure junctionless tunnel FET biosensor with an embedded nanogap is proposed, in which the control gate consists of two parts, namely the tunnel gate and auxiliary gate, with different work functions; and the detection sensitivity of different biomolecules can be controlled and adjusted by the two gates. Further, a polar gate is introduced above the source region, and a P+ source is formed by the charge plasma concept by selecting appropriate work functions for the polar gate. The variation of sensitivity with different control gate and polar gate work functions is explored. Neutral and charged biomolecules are considered to simulate device-level gate effects, and the influence of different dielectric constants on sensitivity is also researched. The simulation results show that the switch ratio of the proposed biosensor can reach 10⁹, the maximum current sensitivity is 6.91 × 10², and the maximum sensitivity of the average subthreshold swing (SS) is 0.62. Full article

In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO₂ to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (I_amb). In contrast, the gate dielectric near the source region consists of high-k HfO₂ to increase the on-state current (I_on) through the method of gate control. To further increase I_on, an n⁺-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large I_on of 7.79 × 10⁻⁵ A/μm, a suppressed I_off of 8.16 × 10⁻¹⁸ A/μm, minimum subthreshold swing (SS_min) of 19 mV/dec, a cutoff frequency (f_T) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications. Full article

The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs). In addition to the selection of source materials with linearly decreasing density-of-states-energy relations (D(E)s), in this study, we further verified, by means of a computer simulation, that a 2D semiconductor-semiconductor combination could also be used as an efficient CS. As a test case, a HfS₂/MoTe₂ FET was studied. It was found that MoTe₂ can be spontaneously p-type-doped by interfacing with n-doped HfS₂, resulting in a truncated decaying hot-carrier density with an increasing p-type channel barrier. Compared to the conventional MoTe₂ FET, the subthreshold swing (SS) of the HfS₂/MoTe₂ FET can be significantly reduced to below 60 mV/decade, and the on-state current can be greatly enhanced by more than two orders of magnitude. It was found that there exists a hybrid transport mechanism involving the cold injection and the tunneling effect in such a p- and n-type HfS₂/MoTe₂ FET, which provides a new design insight into future low-power and high-performance 2D electronics from a physical point of view. Full article

In order to detect biomolecules, a biosensor based on a dielectric-modulated stacked source trench gate tunnel field effect transistor (DM-SSTGTFET) is proposed. The stacked source structure can simultaneously make the on-state current higher and the off-state current lower. The trench gate structure will increase the tunneling area and tunneling probability. Technology computer-aided design (TCAD) is used for the sensitivity study of the proposed structured biosensor. The results show that the current sensitivity of the DM-SSTGTFET biosensor can be as high as 10⁸, the threshold voltage sensitivity can reach 0.46 V and the subthreshold swing sensitivity can reach 0.8. As a result of its high sensitivity and low power consumption, the proposed biosensor has highly promising prospects. Full article

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N⁺/P⁻ starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (L_gap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10⁻¹⁶ A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical. Full article

In-memory computing is an attractive solution for reducing power consumption and memory access latency cost by performing certain computations directly in memory without reading operands and sending them to arithmetic logic units. Content-addressable memory (CAM) is an ideal way to smooth out the distinction between storage and processing, since each memory cell is a processing unit. CAM compares the search input with a table of stored data and returns the matched data address. The issues of constructing binary and ternary content-addressable memory (CAM and TCAM) based on ferroelectric devices are considered. A review of ferroelectric materials and devices is carried out, including on ferroelectric transistors (FeFET), ferroelectric tunnel diodes (FTJ), and ferroelectric memristors. Full article

Current–voltage characteristics of a quantum dot in double-barrier configuration, as formed in the nanoscale channel of silicon transistors, were analyzed both experimentally and theoretically. Single electron transistors (SET) made in a SOI-FET configuration using silicon quantum dot as well as phosphorus donor quantum dots were experimentally investigated. These devices exhibited a quantum Coulomb blockade phenomenon along with a detectable effect of variable tunnel barriers. To replicate the experimental results, we developed a generalized formalism for the tunnel-barrier dependent quantum Coulomb blockade by modifying the rate-equation approach. We qualitatively replicate the experimental results with numerical calculation using this formalism for two and three energy levels participated in the tunneling transport. The new formalism supports the features of most of the small-scaled SET devices. Full article

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications. Full article