Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance

In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO2 to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (Iamb). In contrast, the gate dielectric near the source region consists of high-k HfO2 to increase the on-state current (Ion) through the method of gate control. To further increase Ion, an n+-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large Ion of 7.79 × 10−5 A/μm, a suppressed Ioff of 8.16 × 10−18 A/μm, minimum subthreshold swing (SSmin) of 19 mV/dec, a cutoff frequency (fT) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications.


Introduction
With continuous improvements in chip integration and application requirements, the dimensions of conventional MOSFETs are continuously scaling down to a few nanometers. This results in a number of critical issues, such as leakage current, high-power dissipation, short channel effects (SCEs), and a sub-threshold slope restriction of 60 mV/decade for conventional MOSFETs at room temperature [1][2][3][4][5]. Moreover, the contradiction between static power consumption and device performance caused by off-state leakage current has become a serious problem.
To overcome the limitations of conventional MOSFETs, many novel device structures have been proposed in the past couple of years. Tunnel field-effect transistors (TFETs), one of the most promising candidates for MOSFETs, have been attracting more and more attention in recent years. Because the high-energy tail states of the Fermi distribution function in the source are removed, the off-state current (I off ) of TFETs is much lower than that of the MOSFETs [6]. In addition, because band-to-band tunneling (BTBT) is the main operation mechanism in TFETs, they can break the limitation of 60 mV/decade subthreshold swing (SS) in conventional MOSFETs, which relies on hot electron emission, especially at low voltages [7,8]. Finally, TFETs are more immune to short channel effects and temperature variations [9,10]. Therefore, these advantages make TFETs more favorable for circuits that are based on low-power applications.
However, the main problems of TFETs are low on-state current (I on ), high off-state current (I off ), and ambipolar behavior, which are the main challenges that traditional TFETs face [11][12][13]. The driven current of the conventional TFETs is determined by the gatemodulated tunneling diode. Furthermore, for the silicon-based TFET, the large bandgap

Device Architecture, Parameters, and Simulation Methods
A schematic diagram of the HJ-HD-P-DGTFET structure is shown in Figure 1, which has two symmetrical gate regions to increase the I on . In the proposed TFET, Si 0.6 Ge 0.4 (source)/ Si(channel) heterojunction is used to increase the drain current. The source/drain regions are symmetrically located on both sides of the channel, and the p-Si channel is inserted below the gate. Doping is performed in such a way so as to obtain maximum I on current. Here, we doped the p + source region with 1 × 10 20 atoms/cm 3 , n + drain region with 1 × 10 18 atoms/cm 3 , n + pocket region with 1 × 10 18 atoms/cm 3 , and the intrinsic channel with 1 × 10 16 atoms/cm 3 . Moreover, a conventional Si-DGTFET is used for comparison. All of the device parameters used in the simulation process are given in Table 1. highly doped. Moreover, the concentration-dependent and field-dependent mobility models are also adopted in the simulations. For validation of the models used in the Sentaurus TCAD tool, we calibrated our model against the work carried out by Narang R et al. [38]. Figure 2 shows our model calibration against the work carried out by Narang R et al. [38]. Good agreement between the simulated data and the reported results was observed. The inset shows the simulation result of the transmission characteristics of the HJ-HD-P-DGTFET. It is observed that the Ion of the HJ-HD-P-DGTFET can reach 7.79 × 10 −5 A/µm, and the Ioff is only 8.16 × 10 −18 A/µm. Additionally, the subthreshold swing (SS) of the device is only 19 mV/dec.
The proposed HJ-HD-P-DGTFET structure can be fabricated using similar steps as reported for DGTFET [1,2]. The possible fabrication steps of the proposed HJ-HD-P-DGT-FET are shown in Figure 3. The process begins by preparing the silicon substrate; then, the n+ drain doping region is introduced by vertical As implantation and annealing. Afterward, a thin layer of the n+ pocket is grown via epitaxy. Next, the source region is implanted, as shown in Figure 3a. Following this, the channel region is formed by etching. Subsequently, the isolation oxide is deposited to prevent the drain region from etching, as shown in Figure 3b. In Figure 3c, SiO2 can be grown on the channel using an oxidation process. In Figure 3d, the SiO2 gate dielectric is selectively etched away at the source side by using buffered hydrogen fluoride (BHF) solution. The SiO2 gate dielectric at the drain side is protected by photoresist masks. Part of the SiO2 gate dielectric layer will be replaced by high-k material in Figure 3e. For the next step, atomic layer deposition (ALD) of highk material HfO2 is performed to fill the gap. After this, HfO2 is deposited by ALD on the silicon surface to form a heterogeneous gate dielectric. In Figure 3f, the remaining processes are similar to conventional vertical TFET, involving gate deposition, silicon exposure, etc. [39,40].   The device simulations are carried out using a Synopsys Sentaurus device simulator, which solves Poisson's equation self-consistently with the carrier current continuity equations. The nonlocal BTBT model is used in the simulations to take spatial variation in the energy band into account, and it also considers that the generation/recombination of the opposite carrier type is not spatially coincident. Therefore, the BTBT tunneling process is modeled more accurately. The Shockley-Read-Hall (SRH) and Auger recombination models are considered to include the effect of carrier recombination. The band gap narrowing model and Fermi-Dirac statistics are included because the source regions are highly doped. Moreover, the concentration-dependent and field-dependent mobility models are also adopted in the simulations.
For validation of the models used in the Sentaurus TCAD tool, we calibrated our model against the work carried out by Narang R et al. [38]. Figure 2 shows our model calibration against the work carried out by Narang R et al. [38]. Good agreement between the simulated data and the reported results was observed. The inset shows the simulation result of the transmission characteristics of the HJ-HD-P-DGTFET. It is observed that the I on of the HJ-HD-P-DGTFET can reach 7.79 × 10 −5 A/µm, and the I off is only 8.16 × 10 −18 A/µm. Additionally, the subthreshold swing (SS) of the device is only 19 mV/dec. For validation of the models used in the Sentaurus TCAD tool, we calibrated our model against the work carried out by Narang R et al. [38]. Figure 2 shows our model calibration against the work carried out by Narang R et al. [38]. Good agreement between the simulated data and the reported results was observed. The inset shows the simulation result of the transmission characteristics of the HJ-HD-P-DGTFET. It is observed that the Ion of the HJ-HD-P-DGTFET can reach 7.79 × 10 −5 A/µm, and the Ioff is only 8.16 × 10 −18 A/µm. Additionally, the subthreshold swing (SS) of the device is only 19 mV/dec.
The proposed HJ-HD-P-DGTFET structure can be fabricated using similar steps as reported for DGTFET [1,2]. The possible fabrication steps of the proposed HJ-HD-P-DGT-FET are shown in Figure 3. The process begins by preparing the silicon substrate; then, the n+ drain doping region is introduced by vertical As implantation and annealing. Afterward, a thin layer of the n+ pocket is grown via epitaxy. Next, the source region is implanted, as shown in Figure 3a. Following this, the channel region is formed by etching. Subsequently, the isolation oxide is deposited to prevent the drain region from etching, as shown in Figure 3b. In Figure 3c, SiO2 can be grown on the channel using an oxidation process. In Figure 3d, the SiO2 gate dielectric is selectively etched away at the source side by using buffered hydrogen fluoride (BHF) solution. The SiO2 gate dielectric at the drain side is protected by photoresist masks. Part of the SiO2 gate dielectric layer will be replaced by high-k material in Figure 3e. For the next step, atomic layer deposition (ALD) of highk material HfO2 is performed to fill the gap. After this, HfO2 is deposited by ALD on the silicon surface to form a heterogeneous gate dielectric. In Figure 3f, the remaining processes are similar to conventional vertical TFET, involving gate deposition, silicon exposure, etc. [39,40].  Model calibration against the work from Narang R et al. [38]. The inset shows the transmission characteristics of the HJ-HD-P-DGTFET. Figure 2. Model calibration against the work from Narang R et al. [38]. The inset shows the transmission characteristics of the HJ-HD-P-DGTFET.
The proposed HJ-HD-P-DGTFET structure can be fabricated using similar steps as reported for DGTFET [1,2]. The possible fabrication steps of the proposed HJ-HD-P-DGTFET are shown in Figure 3. The process begins by preparing the silicon substrate; then, the n + drain doping region is introduced by vertical As implantation and annealing. Afterward, a thin layer of the n + pocket is grown via epitaxy. Next, the source region is implanted, as shown in Figure 3a. Following this, the channel region is formed by etching. Subsequently, the isolation oxide is deposited to prevent the drain region from etching, as shown in Figure 3b. In Figure 3c, SiO 2 can be grown on the channel using an oxidation process. In Figure 3d, the SiO 2 gate dielectric is selectively etched away at the source side by using buffered hydrogen fluoride (BHF) solution. The SiO 2 gate dielectric at the drain side is protected by photoresist masks. Part of the SiO 2 gate dielectric layer will be replaced by high-k material in Figure 3e. For the next step, atomic layer deposition (ALD) of high-k material HfO 2 is performed to fill the gap. After this, HfO 2 is deposited by ALD on the silicon surface to form a heterogeneous gate dielectric. In Figure 3f, the remaining processes are similar to conventional vertical TFET, involving gate deposition, silicon exposure, etc. [39,40].   (a) Silicon substrate preparation and the n + region is introduced, after which a n + pocket is deposited by epitaxy. Subsequently, the source region is implanted; (b) etching is performed in the channel region, and isolation oxide is deposited; (c) oxidation growth of SiO 2 ; (d) SiO 2 gate dielectric is selectively etched away at the source side; (e) the HfO 2 is deposited by ALD; (f) gate deposition, silicon exposure, etc.

Results and Discussion
This section analyzes the comparison between Si-DGTFET and HJ-HD-P-DGTFET. Additionally, the effects of device parameters on the transfer characteristics are analyzed, such as the Si 1-x Ge x /Si heterojunction, heterogeneous gate dielectric, and pocket. Finally, the RF performance of HJ-HD-P-DGTFET is also analyzed. Figure 4a compares the transfer characteristics of HJ-HD-P-DGTFET and conventional Si-DGTFET. Due to the use of a SiGe/Si heterostructure and auxiliary tunneling barrier layer (pocket) of n + -doped material, which can increase the tunneling rate, the HJ-HD-P-DGTFET reaches an on-state current (I on ) of 8.46 × 10 −5 A/µm compared with 2.83 × 10 −6 A/µm for the conventional Si-DGTFET. It is observed that the I on for HJ-HD-P-DGTFET is increased by nearly two orders of magnitude compared to conventional Si-DGTFET. Furthermore, a minimum subthreshold swing (SS min ) of 19 mV/dec and an average subthreshold swing (SS avg ) of 28.4 mV/dec are obtained, while the SS avg of the conventional Si-DGTFET is 49.9 mV/dec. As a result, HJ-HD-P-DGTFET has obvious improvements in I on and subthreshold swing compared to conventional Si-DGTFET. Finally, the ambipolar effect for HJ-HD-P-DGTFET is noticeably suppressed, as shown in Figure 4a. Figure 4b shows the on-state energy band condition of both HJ-HD-P-DGTFET and Si-DGTFET. It can be observed that in the on-state, the tunnel barrier of HJ-HD-P-DGTFET is evidently narrower than conventional Si-DGTFET at the channel and source junction.

The Physical Characteristics of Si-DGTFET and HJ-HD-P-DGTFET
Additionally, the effects of device parameters on the transfer characteristics are analyzed, such as the Si1-xGex/Si heterojunction, heterogeneous gate dielectric, and pocket. Finally, the RF performance of HJ-HD-P-DGTFET is also analyzed. Figure 4a compares the transfer characteristics of HJ-HD-P-DGTFET and conventional Si-DGTFET. Due to the use of a SiGe/Si heterostructure and auxiliary tunneling barrier layer (pocket) of n+-doped material, which can increase the tunneling rate, the HJ-HD-P-DGTFET reaches an on-state current (Ion) of 8.46 × 10 −5 A/µm compared with 2.83 × 10 −6 A/µm for the conventional Si-DGTFET. It is observed that the Ion for HJ-HD-P-DGT-FET is increased by nearly two orders of magnitude compared to conventional Si-DGT-FET. Furthermore, a minimum subthreshold swing (SSmin) of 19 mV/dec and an average subthreshold swing (SSavg) of 28.4 mV/dec are obtained, while the SSavg of the conventional Si-DGTFET is 49.9 mV/dec. As a result, HJ-HD-P-DGTFET has obvious improvements in Ion and subthreshold swing compared to conventional Si-DGTFET. Finally, the ambipolar effect for HJ-HD-P-DGTFET is noticeably suppressed, as shown in Figure 4a. Figure 4b shows the on-state energy band condition of both HJ-HD-P-DGTFET and Si-DGTFET. It can be observed that in the on-state, the tunnel barrier of HJ-HD-P-DGTFET is evidently narrower than conventional Si-DGTFET at the channel and source junction.

Si1-xGex/Si Heterojunction
As discussed in Section 2, the source region formed by Si1-xGex is used to improve the on-state current in the HJ-HD-P-DGTFET. It is essential to study the variation in the current value with the different germanium compositions in Si1-xGex, where Si1-xGex (x = 1) equals Ge. Figure 5a depicts the effect of different Ge compositions in the Si1-xGex source region on transfer characteristics, and it is very clear that the on-state current of the proposed device increases with the increase in x until x = 1. When the mole fraction of germanium is 0.1, the on-state current is approximately 1 × 10 −5 A/µm. Furthermore, the on-state current reaches about 8 × 10 −4 A/µm when the mole fraction is increased to 0.9. However, the increase in the Ioff is much greater than the increase in the Ion when the mole fraction is greater than 0.4. Figure 5b shows the effect of the composition ratio x of Si1-xGex on the on-state energy band diagram of HJ-HD-P-DGTFET. As can be seen from this figure, the energy valley value of the conduction band decreases with an increase in the germanium composition. Tunneling is defined as the injection of electrons from the source valence

Si 1-x Ge x /Si Heterojunction
As discussed in Section 2, the source region formed by Si 1-x Ge x is used to improve the on-state current in the HJ-HD-P-DGTFET. It is essential to study the variation in the current value with the different germanium compositions in Si 1-x Ge x , where Si 1-x Ge x (x = 1) equals Ge. Figure 5a depicts the effect of different Ge compositions in the Si 1-x Ge x source region on transfer characteristics, and it is very clear that the on-state current of the proposed device increases with the increase in x until x = 1. When the mole fraction of germanium is 0.1, the on-state current is approximately 1 × 10 −5 A/µm. Furthermore, the on-state current reaches about 8 × 10 −4 A/µm when the mole fraction is increased to 0.9. However, the increase in the I off is much greater than the increase in the I on when the mole fraction is greater than 0.4. Figure 5b shows the effect of the composition ratio x of Si 1-x Ge x on the on-state energy band diagram of HJ-HD-P-DGTFET. As can be seen from this figure, the energy valley value of the conduction band decreases with an increase in the germanium composition. Tunneling is defined as the injection of electrons from the source valence band to the channel conduction band. The smaller energy valley value of the conduction band in the source region represents the larger band-to-band tunneling rate without varying other conditions. Thus, x = 0.4 in Si 1-x Ge x makes a shorter tunneling width compared to other compositions. Consequently, x = 0.4 is chosen as the optimal value in Si 1-x Ge x to ensure a lower off-state leakage current and a higher on-state current.
band to the channel conduction band. The smaller energy valley value of the conduction band in the source region represents the larger band-to-band tunneling rate without varying other conditions. Thus, x = 0.4 in Si1-xGex makes a shorter tunneling width compared to other compositions. Consequently, x = 0.4 is chosen as the optimal value in Si1-xGex to ensure a lower off-state leakage current and a higher on-state current. Figures 6a-d show the transfer characteristics, on-state energy band diagram, electric field, and potential with different doping concentrations in the source region (Ns) when the mole fraction of germanium in Si1-xGex is 0.4. It is observed that the off-state current is decreased, while the on-state current increases as a result of higher source region doping concentration Ns. However, the on-state current slightly decreases when Ns increases from 1 × 10 20 cm −3 to 8 × 10 20 cm −3 . It is evident that the maximum value of the Ion occurs at a concentration of 1 × 10 20 cm −3 , and the corresponding Ion is 1.05 × 10 −4 A/µm, as shown in Figure 6b. It is also observed that the tunneling distance at the point of the tunnel junction decreases with an increase in the source region doping concentration Ns. Furthermore, the valence band increasing significantly in the source region leads to a smaller tunneling distance when Ns is 8 × 10 20 cm −3 . Meanwhile, there is a very large tunneling distance when Ns is 5 × 10 18 cm −3 , which diminishes electron BTBT rates. The value of the electric field under the pocket and channel (-10 nm-10 nm) increases as a result of higher source region doping concentration Ns, as seen in Figure 6C. Consequently, the increasing electric field under the pocket can help to improve the tunneling probability in this region, while increasing the electric field under the channel will raise the barrier height in the drain/channel interface. However, it is observed in Figure 6b that the conduction band spike at the SiGe/Si heterojunction interface appears when the Ns is more than 1 × 10 20 cm −3 , which leads to the carriers that pass through barriers being recombined with the opposite carriers at the interface. This results in the on-state current slightly decreasing when the source region doping concentration Ns exceeds 1 × 10 20 cm −3 . Therefore, the maximum current is attained at Ns = 1 × 10 20 cm −3 .  It is observed that the off-state current is decreased, while the on-state current increases as a result of higher source region doping concentration N s . However, the on-state current slightly decreases when N s increases from 1 × 10 20 cm −3 to 8 × 10 20 cm −3 . It is evident that the maximum value of the I on occurs at a concentration of 1 × 10 20 cm −3 , and the corresponding I on is 1.05 × 10 −4 A/µm, as shown in Figure 6b. It is also observed that the tunneling distance at the point of the tunnel junction decreases with an increase in the source region doping concentration N s . Furthermore, the valence band increasing significantly in the source region leads to a smaller tunneling distance when N s is 8 × 10 20 cm −3 . Meanwhile, there is a very large tunneling distance when N s is 5 × 10 18 cm −3 , which diminishes electron BTBT rates. The value of the electric field under the pocket and channel (-10 nm-10 nm) increases as a result of higher source region doping concentration N s , as seen in Figure 6C. Consequently, the increasing electric field under the pocket can help to improve the tunneling probability in this region, while increasing the electric field under the channel will raise the barrier height in the drain/channel interface. However, it is observed in Figure 6b that the conduction band spike at the SiGe/Si heterojunction interface appears when the N s is more than 1 × 10 20 cm −3 , which leads to the carriers that pass through barriers being recombined with the opposite carriers at the interface. This results in the on-state current slightly decreasing when the source region doping concentration N s exceeds 1 × 10 20 cm −3 . Therefore, the maximum current is attained at N s = 1 × 10 20 cm −3 . Figure 7a shows the transfer characteristic curve of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO 2 + SiO 2 or SiO 2 + HfO 2 ) and single gate dielectric material (HfO 2 or SiO 2 ). As shown in Figure 7a, it was observed that the I amb of HJ-HD-P-DGTFET with a heterogeneous gate dielectric structure (HfO 2 + SiO 2 ) and the single gate dielectric material with SiO 2 decrease by about three orders of magnitude compared with heterogeneous gate dielectric structure (SiO 2 + HfO 2 ) and the single gate dielectric material with SiO 2 when V gs = −1 V. This indicates using SiO 2 for the gate oxide layer near the leakage region effectively inhibits the ambipolar behavior of the device in the heterogeneous gate dielectric structure (HfO 2 + SiO 2 ). The I on of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO 2 + SiO 2 ) increases by four orders of magnitude compared with the single gate dielectric material (SiO 2 ) when V gs = 0.5 V, indicating that the gate oxide layer using HfO 2 near the source region can effectively improve the open current of the device. Therefore, the combined heterogate dielectric structure of HJ-HD-P-DGTFET can not only suppress the ambipolar behavior but also improve the on-state current.  Figure 7a shows the transfer characteristic curve of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO2 + SiO2 or SiO2 + HfO2) and single gate dielectric material (HfO2 or SiO2). As shown in Figure 7a, it was observed that the Iamb of HJ-HD-P-DGTFET with a heterogeneous gate dielectric structure (HfO2 + SiO2) and the single gate dielectric material with SiO2 decrease by about three orders of magnitude compared with heterogeneous gate dielectric structure (SiO2 + HfO2) and the single gate dielectric material with SiO2 when Vgs = −1 V. This indicates using SiO2 for the gate oxide layer near the leakage region effectively inhibits the ambipolar behavior of the device in the heterogeneous gate dielectric structure (HfO2 + SiO2). The Ion of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO2 + SiO2) increases by four orders of magnitude compared with the single gate dielectric material (SiO2) when Vgs = 0.5 V, indicating that the gate oxide layer using HfO2 near the source region can effectively improve the open current of the device. Therefore, the combined heterogate dielectric structure of HJ-HD-P-DGTFET can not only suppress the ambipolar behavior but also improve the on-state current. Figure 7b shows the transfer characteristics of HJ-HD-P-DGTFET with different gate dielectric thicknesses (To). As can be seen from the figure, the Ion of HJ-HD-P-DGTFET decreases with increasing gate oxide thickness. The maximum Ion of HJ-HD-P-DGTFET decreases from 1.38 × 10 −4 A/µm to 1.18 × 10 −5 A/µm when the gate dielectric thickness varies from 1 to 6 nm. Furthermore, the ambipolar current of HJ-HD-P-DGTFET with To = 1 nm increases by two orders of magnitude compared with To = 6 nm. Figure 7c explains Figure 7b from the electric field distribution with different gate dielectric thicknesses. It is  Figure 7b shows the transfer characteristics of HJ-HD-P-DGTFET with different gate dielectric thicknesses (T o ). As can be seen from the figure, the I on of HJ-HD-P-DGTFET decreases with increasing gate oxide thickness. The maximum I on of HJ-HD-P-DGTFET decreases from 1.38 × 10 −4 A/µm to 1.18 × 10 −5 A/µm when the gate dielectric thickness varies from 1 to 6 nm. Furthermore, the ambipolar current of HJ-HD-P-DGTFET with T o = 1 nm increases by two orders of magnitude compared with T o = 6 nm. Figure 7c explains Figure 7b from the electric field distribution with different gate dielectric thicknesses. It is observed that the maximum electric field at the source/pocket interface (−10 nm to −6 nm) increases with decreases in gate dielectric thicknesses, thus reducing the tunneling distance and improving the on-state current. In addition, the electric field at the drain/channel tunnel junction (10 nm) decreases with decreases in gate dielectric thickness, which weakens the band bending around the drain/channel tunnel junction and also reduces the tunneling window. Consequently, the tunneling probability of the carriers is reduced. and the I amb is also weakened with the increases in gate dielectric thickness at the drain/channel tunnel junction. The larger ambipolar current at T o = 1 nm is due to the interface trap at the gate oxide layer, which results in strong electric field bending. Considering the results above and the process conditions, a gate oxide thickness of 2 nm is considered more appropriate. Figure 7d shows the transfer characteristics of HJ-HD-P-DGTFET with different gate work function (Φ M ). Firstly, the selection of Φ M is critical for the I off , which increases rapidly with decreases in Φ M, as depicted in Figure 7d. Secondly, the I on of HJ-HD-P-DGTFET increases slowly with decreases in Φ M . Hence, taking into account the two factors, the optimal value of Φ M is chosen as 4.3 eV.

Gate Heterogeneous Dielectric Structures
tunneling window. Consequently, the tunneling probability of the carriers is reduced. and the Iamb is also weakened with the increases in gate dielectric thickness at the drain/channel tunnel junction. The larger ambipolar current at To = 1 nm is due to the interface trap at the gate oxide layer, which results in strong electric field bending. Considering the results above and the process conditions, a gate oxide thickness of 2 nm is considered more appropriate. Figure 7d shows the transfer characteristics of HJ-HD-P-DGTFET with different gate work function (ΦM). Firstly, the selection of ΦM is critical for the Ioff, which increases rapidly with decreases in ΦM, as depicted in Figure 7d. Secondly, the Ion of HJ-HD-P-DGT-FET increases slowly with decreases in ΦM. Hence, taking into account the two factors, the optimal value of ΦM is chosen as 4.3 eV.

Auxiliary Tunneling Barrier Layer (Pocket) Optimization Results
In order to improve the performance of the device, we introduced a structure with a lightly doped pocket near the source region in the HJ-HD-P-DGTFET. The proposed device is optimized for pocket length (L P ) by varying its value from 0 nm (without pocket) to 8 nm. When L P was varied in the channel region, the height of the pocket (T p ) was kept constant at 20 nm. All the other design parameters are the same as listed in Table 1. Figure 8 shows the effect of the pocket structure parameters on device performance. It can be seen from Figure 8a that the pocket can effectively improve the transfer characteristics of the device. The I off shows a slight dependence on pocket length, while I on and SS values are independent of pocket length L P, as shown in Figure 8a. It is clear that there is no obvious change in I on , but I off slightly increases as L P increases from 1 nm to 8 nm. The I off increases from 2.4 × 10 −18 A/µm to 8.5 × 10 −16 A/µm with the increase in L p from 1 nm to 8 nm. As seen in Figure 8b, the BTBT tunneling rate at the source channel junction is reduced with L P and extends towards the channel side, which eventually reduces I off with L P in the device. Therefore, 2 nm is considered as the optimum length of the pocket in order to obtain a lower I off and good process conditions. The variations in transfer characteristics with different pocket doping concentrations (Np) are shown in Figure 8d. It is seen that higher pocket doping concentrations (Np) cause a higher off-state current. This can be attributed to electric field distribution changes with different pocket doping concentrations, as shown in Figure 8e. The electric field in the source/channel interface (−10 nm) increases with increasing Np. Consequently, the increasing electric field near the source region helps to improve the tunneling probability in this region. Therefore, 1 × 10 18 cm −3 is regarded as the optimal Np.  Figure 9a shows a comparison of Cgd and Cgs of the four devices at a frequency of 1.0 × 10 6 Hz. There is not much difference in Cgs for the four studied TFETs, as shown in Figure  9a. Moreover, it is very clear that both Cgg and Cgd of HJ-P-DGTFET Hk (single gate dielectric material is HfO2, and other parameters are the same as HJ-HD-P-DGTFET) and HJ-HD-P-DGTFET increase rapidly with increasing Vgs, while the Cgg and Cgd of HJ-P-DGT-FET Lk (single gate dielectric material is SiO2, and other parameters are the same as HJ-HD-P-DGTFET) and Si-DGTFET (parameters are referred to in Table 1) maintain a very small value. Although the gate capacitance characteristics of HJ-HD-P-DGTFET are poor, capacitance is only one aspect that must be considered, and transconductance and Ion will also greatly affect device performance. For TFET, increasing the Ion benefits from reducing the tunneling barrier width, but this is bound to increase the capacitance. Therefore, it is  Figure 8c shows the influence of the height of the pocket (T p ) on the performance of the HJ-HD-P-DGTFET, under the condition that other parameters remain constant. It is observed that there is no significant change in I on when the T P increases from 4 nm to 16 nm, keeping the L P fixed at 2 nm. However, the I on increases when the T P increases up to 20 nm. This is due to the fact that the higher height of the pocket results in a larger tunneling surface. That is to say, increasing height of the pocket enhances the device characteristics. Thus, 20 nm is regarded as the optimal height of the pocket.

Comparison of Analog/RF Performance
The variations in transfer characteristics with different pocket doping concentrations (N p ) are shown in Figure 8d. It is seen that higher pocket doping concentrations (N p ) cause a higher off-state current. This can be attributed to electric field distribution changes with different pocket doping concentrations, as shown in Figure 8e. The electric field in the source/channel interface (−10 nm) increases with increasing N p . Consequently, the increasing electric field near the source region helps to improve the tunneling probability in this region. Therefore, 1 × 10 18 cm −3 is regarded as the optimal N p . Figure 9a shows a comparison of C gd and C gs of the four devices at a frequency of 1.0 × 10 6 Hz. There is not much difference in C gs for the four studied TFETs, as shown in Figure 9a. Moreover, it is very clear that both C gg and C gd of HJ-P-DGTFET Hk (single gate dielectric material is HfO 2 , and other parameters are the same as HJ-HD-P-DGTFET) and HJ-HD-P-DGTFET increase rapidly with increasing V gs , while the C gg and C gd of HJ-P-DGTFET Lk (single gate dielectric material is SiO 2 , and other parameters are the same as HJ-HD-P-DGTFET) and Si-DGTFET (parameters are referred to in Table 1) maintain a very small value. Although the gate capacitance characteristics of HJ-HD-P-DGTFET are poor, capacitance is only one aspect that must be considered, and transconductance and I on will also greatly affect device performance. For TFET, increasing the I on benefits from reducing the tunneling barrier width, but this is bound to increase the capacitance. Therefore, it is necessary to comprehensively consider its DC characteristics and capacitance characteristics. In fact, the large leakage capacitance of the TFET is attributed to its intrinsic capacitance, which is also related to the conduction mechanism. It is difficult to reduce the gate leakage intrinsic capacitance of the TFET, owing to the fact that the gate leakage intrinsic capacitance affects the tunneling current of the device. Therefore, solving the TFET gate leakage capacitance is still a challenging task.

Comparison of Analog/RF Performance
In the design of RF applications, the parameters of cut-off frequency (f T ) and gainbandwidth product (GWB) are figures of merit (FOMs). Figure 9b,c show the cut-off frequency and gain-bandwidth product calculated by Equations (1) and (2). The results show that the f T first increases with V gs due to an increased g m value. However, it subsequently decreases with V gs due to the increase in C gd and the reduction in g m . The decrease in g m can be attributed to the degradation of mobility with the gate field. It is found that the maximum f T of HJ-HD-P-DGTFET is 19.95 GHz, which is greater than the f T of the Si-DGTFET (0.22 GHz). This makes HJ-HD-P-DGTFET more suitable for RF applications.
where g m represents transconductance.
As shown in Figure 9c, it is observed that a higher GWB of 2.07 GHz is obtained for HJ-HD-P-DGTFET. Furthermore, it is noted that the GWB initially increases with V gs because of the increase in transconductance (g m ), then decreases as V gs continues to rise, resulting from an increase in C gd and a decrease in g m . Comparing the two devices, the GBW of the HJ-HD-P-DGTFET is less than that of the Si-DGTFET.

GBW= 2π10Cgd
(2) As shown in Figure 9c, it is observed that a higher GWB of 2.07 GHz is obtained for HJ-HD-P-DGTFET. Furthermore, it is noted that the GWB initially increases with Vgs because of the increase in transconductance (gm), then decreases as Vgs continues to rise, resulting from an increase in Cgd and a decrease in gm. Comparing the two devices, the GBW of the HJ-HD-P-DGTFET is less than that of the Si-DGTFET.

Comparison of Different TFETs with HJ-HD-P-DGTFET
In order to understand the potential of HJ-HD-P-DGTFET in ultra-low-power applications, Table 2 shows a performance comparison of different TFETs with HJ-HD-P-DGT-FET. Compared to other TFETs [41][42][43][44] with different heterogeneous gate dielectric structures, HJ-HD-P-DGTFET has obvious advantages in Ion, Ioff, and Ion/Ioff ratio. This is because of the improved tunneling rate by using p-type doped SiGe material in the source region

Comparison of Different TFETs with HJ-HD-P-DGTFET
In order to understand the potential of HJ-HD-P-DGTFET in ultra-low-power applications, Table 2 shows a performance comparison of different TFETs with HJ-HD-P-DGTFET. Compared to other TFETs [41][42][43][44] with different heterogeneous gate dielectric structures, HJ-HD-P-DGTFET has obvious advantages in I on , I off , and I on /I off ratio. This is because of the improved tunneling rate by using p-type doped SiGe material in the source region and auxiliary tunneling barrier layer (pocket) of n + -doped material between the source/channel junction. Compared to heterojunction TFETs [32,34,45,46], HJ-HD-P-DGTFET has obvious advantages in I on /I off ratio and I off . This is due to the reduced I amb and the increased I on by using a low K value near the drain region and a high K value near the source region. Compared to other novel structural TFETs [47,48], HJ-HD-P-DGTFET has obvious advantages in I off and I on /I off ratio. By combining the advantages of heterogeneous gate dielectric structures, heterojunction, and auxiliary tunneling barrier layer, HJ-HD-P-DGTFET can provide high operating current and low static power consumption in ultra-low-power applications. Table 2. Performance comparison of different TFETs with HJ-HD-P-DGTFET.

Conclusions
In this work, a novel HJ-HD-P-DGTFET is proposed, and its electrical characteristics are simulated and analyzed. The structural characteristics, physical mechanisms, performance with different parameters, and analog/RF performance of HJ-HD-P-DGTFET are discussed and studied. Simulation results show that the new design of HJ-HD-P-DGTFET performs well in terms of both switching and analog/RF characteristics compared with the conventional Si-DGTFET. Benefitting from SiGe(source)/Si(channel) heterojunction and the heavily doped pocket within the channel, the I on for HJ-HD-P-DGTFET is increased by nearly two orders of magnitude compared with conventional Si-DGTFET due to the increase in the tunneling rate. Owing to the use of a high-k HfO 2 gate dielectric in the source region and low-k SiO 2 gate dielectric in the drain region, which weakens the gate control of the channel-drain tunneling junction, the I amb is clearly suppressed, and the I on /I off ratio is greatly improved. Finally, a large I on of 7.79 × 10 −5 A/µm, a suppressed I off of 8.16 × 10 −18 A/µm, I on /I off of 9.55 × 10 12 , SS min of 19 mV/dec, f T of 19.95 GHz, and GBW of 2.07 GHz can be achieved by HJ-HD-P-DGTFET. Therefore, HJ-HD-P-DGTFET can be a potential candidate for future low-power IC applications.