Novel SiGe/Si Heterojunction Double-Gate Tunneling FETs with a Heterogate Dielectric for High Performance

Abstract

In this paper, a new SiGe/Si heterojunction double-gate heterogate dielectric tunneling field-effect transistor with an auxiliary tunneling barrier layer (HJ-HD-P-DGTFET) is proposed and investigated using TCAD tools. SiGe material has a smaller band gap than Si, so a heterojunction with SiGe(source)/Si(channel) can result in a smaller tunneling distance, which is very helpful in boosting the tunneling rate. The gate dielectric near the drain region consists of low-k SiO₂ to weaken the gate control of the channel-drain tunneling junction and reduce the ambipolar current (I_amb). In contrast, the gate dielectric near the source region consists of high-k HfO₂ to increase the on-state current (I_on) through the method of gate control. To further increase I_on, an n⁺-doped auxiliary tunneling barrier layer (pocket)is used to reduce the tunneling distance. Therefore, the proposed HJ-HD-P-DGTFET can obtain a higher on-state current and suppressed ambipolar effect. The simulation results show that a large I_on of 7.79 × 10⁻⁵ A/μm, a suppressed I_off of 8.16 × 10⁻¹⁸ A/μm, minimum subthreshold swing (SS_min) of 19 mV/dec, a cutoff frequency (f_T) of 19.95 GHz, and gain bandwidth product (GBW) of 2.07 GHz can be achieved. The data indicate that HJ-HD-P-DGTFET is a promising device for low-power-consumption radio frequency applications.

1. Introduction

With continuous improvements in chip integration and application requirements, the dimensions of conventional MOSFETs are continuously scaling down to a few nanometers. This results in a number of critical issues, such as leakage current, high-power dissipation, short channel effects (SCEs), and a sub-threshold slope restriction of 60 mV/decade for conventional MOSFETs at room temperature [1,2,3,4,5]. Moreover, the contradiction between static power consumption and device performance caused by off-state leakage current has become a serious problem.

To overcome the limitations of conventional MOSFETs, many novel device structures have been proposed in the past couple of years. Tunnel field-effect transistors (TFETs), one of the most promising candidates for MOSFETs, have been attracting more and more attention in recent years. Because the high-energy tail states of the Fermi distribution function in the source are removed, the off-state current (I_off) of TFETs is much lower than that of the MOSFETs [6]. In addition, because band-to-band tunneling (BTBT) is the main operation mechanism in TFETs, they can break the limitation of 60 mV/decade subthreshold swing (SS) in conventional MOSFETs, which relies on hot electron emission, especially at low voltages [7,8]. Finally, TFETs are more immune to short channel effects and temperature variations [9,10]. Therefore, these advantages make TFETs more favorable for circuits that are based on low-power applications.

However, the main problems of TFETs are low on-state current (I_on), high off-state current (I_off), and ambipolar behavior, which are the main challenges that traditional TFETs face [11,12,13]. The driven current of the conventional TFETs is determined by the gate-modulated tunneling diode. Furthermore, for the silicon-based TFET, the large bandgap and carrier mass in silicon material result in a small drive current. Thus, double-gate tunnel field-effect transistors (DGTFETs) are expected to extend the limitations of leakage current and subthreshold slope [10,14,15,16]. At present, various methods, such as gate dielectric engineering [17,18,19,20], hetero-structure [21,22,23,24], dielectric pocket [25,26,27,28,29] and work function engineering [15,30,31,32], are proposed to improve the I_on. However, most of these approaches significantly boost I_on at the expense of other device performance metrics, such as I_off, ambipolar current, and analog/RF performance.

Going forward, silicon germanium (SiGe) will most likely be adopted for future low-power very-large-scale integration (VLSI) technologies among all material systems for TFET applications, owing to its VLSI compatibility, mature synthesis techniques, and tunable bandgap [11,33,34]. In this work, we propose a new Si_1-xGe_x/Si heterostructure TFET with high-k/low-k dual material heterogeneous gate dielectric and a heavily doped pocket within the channel (HJ-HD-P-DGTFET). The use of p-type doped SiGe material in the source region instead of adopting germanium and III-V compound semiconductors in the source region of TFET can lead to higher ON/OFF ratios due to a smaller tunneling distance obtained by the heterojunction, which is very helpful to boost the tunneling rate [15]. Furthermore, an n⁺-doped auxiliary tunneling barrier layer (pocket) is added between the source/channel junction to further increase tunneling efficiency of the device at the tunnel junction [35]. Finally, the gate dielectric near the drain region consists of SiO₂ with low K values, which weakens the gate control of the channel-drain tunneling junction and can effectively reduce the ambipolar current (I_amb), while HfO₂ with a high K value near the source region is chosen to increase I_on through the method of gate control [36,37].

The structures of this paper are as follows: Section 2 incorporates the proposed device structure along with the design parameters, simulation models, and fabrication process. Section 3 is dedicated to the mechanism, characteristics, and analog/RF performance of the proposed devices (HJ-HD-P-DGTFET). The device parameter variability analysis of the proposed structure is also covered in this section. Furthermore, a performance comparison between Si DG-TFET and HJ-HD-P-DGTFET is also carried out in this section. Finally, Section 4 summarizes the conclusions of this work.

2. Device Architecture, Parameters, and Simulation Methods

A schematic diagram of the HJ-HD-P-DGTFET structure is shown in Figure 1, which has two symmetrical gate regions to increase the I_on. In the proposed TFET, Si_0.6Ge_0.4(source)/Si(channel) heterojunction is used to increase the drain current. The source/drain regions are symmetrically located on both sides of the channel, and the p-Si channel is inserted below the gate. Doping is performed in such a way so as to obtain maximum I_on current. Here, we doped the p⁺ source region with 1 × 10²⁰ atoms/cm³, n⁺ drain region with 1 × 10¹⁸ atoms/cm³, n⁺ pocket region with 1 × 10¹⁸ atoms/cm³, and the intrinsic channel with 1 × 10¹⁶ atoms/cm³. Moreover, a conventional Si-DGTFET is used for comparison. All of the device parameters used in the simulation process are given in

Table 1. Various structural specification parameters of the presented TFETs for the simulation.

Parameters	HJ-HD-P-DGTFET	Si-DGTFET
Source doping (p-type)	1 × 1020 cm−3	1 × 1020 cm−3
Drain doping (n-type)	1 × 1018 cm−3	1 × 1018 cm−3
Channel doping (p-type)	1 × 1016 cm−3	1 × 1016 cm−3
Pocket doping (n-type)	1 × 1018 cm−3	–
Gate oxide thickness (To)	2 nm	2 nm
Pocket length (Lp)	2 nm	–
Gate dielectric constant of SiO2 (ε)	3.9	3.9
Gate dielectric constant of HfO2 (ε)	25	–
Gate work function (Φm)	4.3 eV	4.3 eV

.

The device simulations are carried out using a Synopsys Sentaurus device simulator, which solves Poisson’s equation self-consistently with the carrier current continuity equations. The nonlocal BTBT model is used in the simulations to take spatial variation in the energy band into account, and it also considers that the generation/recombination of the opposite carrier type is not spatially coincident. Therefore, the BTBT tunneling process is modeled more accurately. The Shockley–Read–Hall (SRH) and Auger recombination models are considered to include the effect of carrier recombination. The band gap narrowing model and Fermi–Dirac statistics are included because the source regions are highly doped. Moreover, the concentration-dependent and field-dependent mobility models are also adopted in the simulations.

For validation of the models used in the Sentaurus TCAD tool, we calibrated our model against the work carried out by Narang R et al. [38]. Figure 2 shows our model calibration against the work carried out by Narang R et al. [38]. Good agreement between the simulated data and the reported results was observed. The inset shows the simulation result of the transmission characteristics of the HJ-HD-P-DGTFET. It is observed that the I_on of the HJ-HD-P-DGTFET can reach 7.79 × 10⁻⁵ A/μm, and the I_off is only 8.16 × 10⁻¹⁸ A/μm. Additionally, the subthreshold swing (SS) of the device is only 19 mV/dec.

The proposed HJ-HD-P-DGTFET structure can be fabricated using similar steps as reported for DGTFET [1,2]. The possible fabrication steps of the proposed HJ-HD-P-DGTFET are shown in Figure 3. The process begins by preparing the silicon substrate; then, the n⁺ drain doping region is introduced by vertical As implantation and annealing. Afterward, a thin layer of the n⁺ pocket is grown via epitaxy. Next, the source region is implanted, as shown in Figure 3a. Following this, the channel region is formed by etching. Subsequently, the isolation oxide is deposited to prevent the drain region from etching, as shown in Figure 3b. In Figure 3c, SiO₂ can be grown on the channel using an oxidation process. In Figure 3d, the SiO₂ gate dielectric is selectively etched away at the source side by using buffered hydrogen fluoride (BHF) solution. The SiO₂ gate dielectric at the drain side is protected by photoresist masks. Part of the SiO₂ gate dielectric layer will be replaced by high-k material in Figure 3e. For the next step, atomic layer deposition (ALD) of high-k material HfO₂ is performed to fill the gap. After this, HfO₂ is deposited by ALD on the silicon surface to form a heterogeneous gate dielectric. In Figure 3f, the remaining processes are similar to conventional vertical TFET, involving gate deposition, silicon exposure, etc. [39,40].

3. Results and Discussion

This section analyzes the comparison between Si-DGTFET and HJ-HD-P-DGTFET. Additionally, the effects of device parameters on the transfer characteristics are analyzed, such as the Si_1-xGe_x/Si heterojunction, heterogeneous gate dielectric, and pocket. Finally, the RF performance of HJ-HD-P-DGTFET is also analyzed.

3.1. The Physical Characteristics of Si-DGTFET and HJ-HD-P-DGTFET

Figure 4a compares the transfer characteristics of HJ-HD-P-DGTFET and conventional Si-DGTFET. Due to the use of a SiGe/Si heterostructure and auxiliary tunneling barrier layer (pocket) of n⁺-doped material, which can increase the tunneling rate, the HJ-HD-P-DGTFET reaches an on-state current (I_on) of 8.46 × 10⁻⁵ A/μm compared with 2.83 × 10⁻⁶ A/μm for the conventional Si-DGTFET. It is observed that the I_on for HJ-HD-P-DGTFET is increased by nearly two orders of magnitude compared to conventional Si-DGTFET. Furthermore, a minimum subthreshold swing (SS_min) of 19 mV/dec and an average subthreshold swing (SS_avg) of 28.4 mV/dec are obtained, while the SS_avg of the conventional Si-DGTFET is 49.9 mV/dec. As a result, HJ-HD-P-DGTFET has obvious improvements in I_on and subthreshold swing compared to conventional Si-DGTFET. Finally, the ambipolar effect for HJ-HD-P-DGTFET is noticeably suppressed, as shown in Figure 4a. Figure 4b shows the on-state energy band condition of both HJ-HD-P-DGTFET and Si-DGTFET. It can be observed that in the on-state, the tunnel barrier of HJ-HD-P-DGTFET is evidently narrower than conventional Si-DGTFET at the channel and source junction.

3.2. Si_1-xGe_x/Si Heterojunction

As discussed in Section 2, the source region formed by Si_1-xGe_x is used to improve the on-state current in the HJ-HD-P-DGTFET. It is essential to study the variation in the current value with the different germanium compositions in Si_1-xGe_x, where Si_1-xGe_x (x = 1) equals Ge. Figure 5a depicts the effect of different Ge compositions in the Si_1-xGe_x source region on transfer characteristics, and it is very clear that the on-state current of the proposed device increases with the increase in x until x = 1. When the mole fraction of germanium is 0.1, the on-state current is approximately 1 × 10⁻⁵ A/μm. Furthermore, the on-state current reaches about 8 × 10⁻⁴ A/μm when the mole fraction is increased to 0.9. However, the increase in the I_off is much greater than the increase in the I_on when the mole fraction is greater than 0.4. Figure 5b shows the effect of the composition ratio x of Si_1-xGe_x on the on-state energy band diagram of HJ-HD-P-DGTFET. As can be seen from this figure, the energy valley value of the conduction band decreases with an increase in the germanium composition. Tunneling is defined as the injection of electrons from the source valence band to the channel conduction band. The smaller energy valley value of the conduction band in the source region represents the larger band-to-band tunneling rate without varying other conditions. Thus, x = 0.4 in Si_1-xGe_x makes a shorter tunneling width compared to other compositions. Consequently, x = 0.4 is chosen as the optimal value in Si_1-xGe_x to ensure a lower off-state leakage current and a higher on-state current.

Figure 6a–d show the transfer characteristics, on-state energy band diagram, electric field, and potential with different doping concentrations in the source region (N_s) when the mole fraction of germanium in Si_1-xGe_x is 0.4. It is observed that the off-state current is decreased, while the on-state current increases as a result of higher source region doping concentration N_s. However, the on-state current slightly decreases when N_s increases from 1 × 10²⁰ cm⁻³ to 8 × 10²⁰ cm⁻³. It is evident that the maximum value of the I_on occurs at a concentration of 1 × 10²⁰ cm⁻³, and the corresponding I_on is 1.05 × 10⁻⁴ A/μm, as shown in Figure 6b. It is also observed that the tunneling distance at the point of the tunnel junction decreases with an increase in the source region doping concentration N_s. Furthermore, the valence band increasing significantly in the source region leads to a smaller tunneling distance when N_s is 8 × 10²⁰ cm⁻³. Meanwhile, there is a very large tunneling distance when N_s is 5 × 10¹⁸ cm⁻³, which diminishes electron BTBT rates. The value of the electric field under the pocket and channel (–10 nm–10 nm) increases as a result of higher source region doping concentration N_s, as seen in Figure 6C. Consequently, the increasing electric field under the pocket can help to improve the tunneling probability in this region, while increasing the electric field under the channel will raise the barrier height in the drain/channel interface. However, it is observed in Figure 6b that the conduction band spike at the SiGe/Si heterojunction interface appears when the N_s is more than 1 × 10²⁰ cm⁻³, which leads to the carriers that pass through barriers being recombined with the opposite carriers at the interface. This results in the on-state current slightly decreasing when the source region doping concentration N_s exceeds 1 × 10²⁰ cm⁻³. Therefore, the maximum current is attained at N_s = 1 × 10²⁰ cm⁻³.

3.3. Gate Heterogeneous Dielectric Structures

Figure 7a shows the transfer characteristic curve of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO₂ + SiO₂ or SiO₂ + HfO₂) and single gate dielectric material (HfO₂ or SiO₂). As shown in Figure 7a, it was observed that the I_amb of HJ-HD-P-DGTFET with a heterogeneous gate dielectric structure (HfO₂ + SiO₂) and the single gate dielectric material with SiO₂ decrease by about three orders of magnitude compared with heterogeneous gate dielectric structure (SiO₂ + HfO₂) and the single gate dielectric material with SiO₂ when V_gs = −1 V. This indicates using SiO₂ for the gate oxide layer near the leakage region effectively inhibits the ambipolar behavior of the device in the heterogeneous gate dielectric structure (HfO₂ + SiO₂). The I_on of the HJ-HD-P-DGTFET with heterogeneous gate dielectric structure (HfO₂ + SiO₂) increases by four orders of magnitude compared with the single gate dielectric material (SiO₂) when V_gs = 0.5 V, indicating that the gate oxide layer using HfO₂ near the source region can effectively improve the open current of the device. Therefore, the combined heterogate dielectric structure of HJ-HD-P-DGTFET can not only suppress the ambipolar behavior but also improve the on-state current.

Figure 7b shows the transfer characteristics of HJ-HD-P-DGTFET with different gate dielectric thicknesses (T_o). As can be seen from the figure, the I_on of HJ-HD-P-DGTFET decreases with increasing gate oxide thickness. The maximum I_on of HJ-HD-P-DGTFET decreases from 1.38 × 10⁻⁴ A/μm to 1.18 × 10⁻⁵ A/μm when the gate dielectric thickness varies from 1 to 6 nm. Furthermore, the ambipolar current of HJ-HD-P-DGTFET with T_o = 1 nm increases by two orders of magnitude compared with T_o = 6 nm. Figure 7c explains Figure 7b from the electric field distribution with different gate dielectric thicknesses. It is observed that the maximum electric field at the source/pocket interface (−10 nm to −6 nm) increases with decreases in gate dielectric thicknesses, thus reducing the tunneling distance and improving the on-state current. In addition, the electric field at the drain/channel tunnel junction (10 nm) decreases with decreases in gate dielectric thickness, which weakens the band bending around the drain/channel tunnel junction and also reduces the tunneling window. Consequently, the tunneling probability of the carriers is reduced. and the I_amb is also weakened with the increases in gate dielectric thickness at the drain/channel tunnel junction. The larger ambipolar current at T_o = 1 nm is due to the interface trap at the gate oxide layer, which results in strong electric field bending. Considering the results above and the process conditions, a gate oxide thickness of 2 nm is considered more appropriate. Figure 7d shows the transfer characteristics of HJ-HD-P-DGTFET with different gate work function (Φ_M). Firstly, the selection of Φ_M is critical for the I_off, which increases rapidly with decreases in Φ_M, as depicted in Figure 7d. Secondly, the I_on of HJ-HD-P-DGTFET increases slowly with decreases in Φ_M. Hence, taking into account the two factors, the optimal value of Φ_M is chosen as 4.3 eV.

3.4. Auxiliary Tunneling Barrier Layer (Pocket) Optimization Results

In order to improve the performance of the device, we introduced a structure with a lightly doped pocket near the source region in the HJ-HD-P-DGTFET. The proposed device is optimized for pocket length (L_P) by varying its value from 0 nm (without pocket) to 8 nm. When L_P was varied in the channel region, the height of the pocket (T_p) was kept constant at 20 nm. All the other design parameters are the same as listed in Table 1.

Figure 8 shows the effect of the pocket structure parameters on device performance. It can be seen from Figure 8a that the pocket can effectively improve the transfer characteristics of the device. The I_off shows a slight dependence on pocket length, while I_on and SS values are independent of pocket length L_P, as shown in Figure 8a. It is clear that there is no obvious change in I_on, but I_off slightly increases as L_P increases from 1 nm to 8 nm. The I_off increases from 2.4 × 10⁻¹⁸ A/μm to 8.5 × 10⁻¹⁶ A/μm with the increase in L_p from 1 nm to 8 nm. As seen in Figure 8b, the BTBT tunneling rate at the source channel junction is reduced with L_P and extends towards the channel side, which eventually reduces I_off with L_P in the device. Therefore, 2 nm is considered as the optimum length of the pocket in order to obtain a lower I_off and good process conditions.

Figure 8c shows the influence of the height of the pocket (T_p) on the performance of the HJ-HD-P-DGTFET, under the condition that other parameters remain constant. It is observed that there is no significant change in I_on when the T_P increases from 4 nm to 16 nm, keeping the L_P fixed at 2 nm. However, the I_on increases when the T_P increases up to 20 nm. This is due to the fact that the higher height of the pocket results in a larger tunneling surface. That is to say, increasing height of the pocket enhances the device characteristics. Thus, 20 nm is regarded as the optimal height of the pocket.

The variations in transfer characteristics with different pocket doping concentrations (N_p) are shown in Figure 8d. It is seen that higher pocket doping concentrations (N_p) cause a higher off-state current. This can be attributed to electric field distribution changes with different pocket doping concentrations, as shown in Figure 8e. The electric field in the source/channel interface (−10 nm) increases with increasing N_p. Consequently, the increasing electric field near the source region helps to improve the tunneling probability in this region. Therefore, 1 × 10¹⁸ cm⁻³ is regarded as the optimal N_p.

3.5. Comparison of Analog/RF Performance

Figure 9a shows a comparison of C_gd and C_gs of the four devices at a frequency of 1.0 × 10⁶ Hz. There is not much difference in C_gs for the four studied TFETs, as shown in Figure 9a. Moreover, it is very clear that both C_gg and C_gd of HJ-P-DGTFET Hk (single gate dielectric material is HfO₂, and other parameters are the same as HJ-HD-P-DGTFET) and HJ-HD-P-DGTFET increase rapidly with increasing V_gs, while the C_gg and C_gd of HJ-P-DGTFET Lk (single gate dielectric material is SiO₂, and other parameters are the same as HJ-HD-P-DGTFET) and Si-DGTFET (parameters are referred to in Table 1) maintain a very small value. Although the gate capacitance characteristics of HJ-HD-P-DGTFET are poor, capacitance is only one aspect that must be considered, and transconductance and I_on will also greatly affect device performance. For TFET, increasing the I_on benefits from reducing the tunneling barrier width, but this is bound to increase the capacitance. Therefore, it is necessary to comprehensively consider its DC characteristics and capacitance characteristics. In fact, the large leakage capacitance of the TFET is attributed to its intrinsic capacitance, which is also related to the conduction mechanism. It is difficult to reduce the gate leakage intrinsic capacitance of the TFET, owing to the fact that the gate leakage intrinsic capacitance affects the tunneling current of the device. Therefore, solving the TFET gate leakage capacitance is still a challenging task.

In the design of RF applications, the parameters of cut-off frequency (f_T) and gain-bandwidth product (GWB) are figures of merit (FOMs). Figure 9b,c show the cut-off frequency and gain-bandwidth product calculated by Equations (1) and (2). The results show that the f_T first increases with V_gs due to an increased g_m value. However, it subsequently decreases with V_gs due to the increase in C_gd and the reduction in g_m. The decrease in g_m can be attributed to the degradation of mobility with the gate field. It is found that the maximum f_T of HJ-HD-P-DGTFET is 19.95 GHz, which is greater than the f_T of the Si-DGTFET (0.22 GHz). This makes HJ-HD-P-DGTFET more suitable for RF applications.

$${\mathrm{f}}_{\mathrm{T}}=\frac{\mathrm{g}\mathrm{m}}{2\mathsf{\pi }(\mathrm{C}\mathrm{g}\mathrm{s}+\mathrm{C}\mathrm{g}\mathrm{d})}$$

(1)

where g_m represents transconductance.

$$\mathrm{GBW}=\frac{\mathrm{g}\mathrm{m}}{2\mathsf{\pi }10\mathrm{C}\mathrm{g}\mathrm{d}}$$

(2)

As shown in Figure 9c, it is observed that a higher GWB of 2.07 GHz is obtained for HJ-HD-P-DGTFET. Furthermore, it is noted that the GWB initially increases with V_gs because of the increase in transconductance (g_m), then decreases as V_gs continues to rise, resulting from an increase in C_gd and a decrease in g_m. Comparing the two devices, the GBW of the HJ-HD-P-DGTFET is less than that of the Si-DGTFET.

3.6. Comparison of Different TFETs with HJ-HD-P-DGTFET

In order to understand the potential of HJ-HD-P-DGTFET in ultra-low-power applications,

Table 2. Performance comparison of different TFETs with HJ-HD-P-DGTFET.

Device	Ion (A/μm)	Ioff (A/μm)	Ion/Ioff Ratio
CP-DGTFET [41]	5.8 × 10−7	10−15	108
SP-GDU-DGTFET [42]	10−7	10−17	1010
DF-TFET [43]	3.8 × 10−6	2.7 × 10−17	1011
DS-TFET [44]	1.0 × 10−8	1.9 × 10−16	107
Mg2Si source CP-DGTFET [45]	4.6 × 10−3	10−16	1013
Ge CP-DGTFET [32]	10−6	10−18	1012
Si0.8Ge0.2 pocket TFET [34]	10−6	10−13	107
SiGe/Si TFET [46]	6.7 × 10−6	2.0 × 10−10	104
CS-DL-NT-TFET [47]	1.7 × 10−5	2.0 × 10−17	1011
HD-HJLTFET [48]	4.5 × 10−5	1.5 × 10−16	1011
This work	7.8 × 10−5	8.2 × 10−18	1012

shows a performance comparison of different TFETs with HJ-HD-P-DGTFET. Compared to other TFETs [41,42,43,44] with different heterogeneous gate dielectric structures, HJ-HD-P-DGTFET has obvious advantages in I_on, I_off, and I_on/I_off ratio. This is because of the improved tunneling rate by using p-type doped SiGe material in the source region and auxiliary tunneling barrier layer (pocket) of n⁺-doped material between the source/channel junction. Compared to heterojunction TFETs [32,34,45,46], HJ-HD-P-DGTFET has obvious advantages in I_on/I_off ratio and I_off. This is due to the reduced I_amb and the increased I_on by using a low K value near the drain region and a high K value near the source region. Compared to other novel structural TFETs [47,48], HJ-HD-P-DGTFET has obvious advantages in I_off and I_on/I_off ratio. By combining the advantages of heterogeneous gate dielectric structures, heterojunction, and auxiliary tunneling barrier layer, HJ-HD-P-DGTFET can provide high operating current and low static power consumption in ultra-low-power applications.

4. Conclusions

In this work, a novel HJ-HD-P-DGTFET is proposed, and its electrical characteristics are simulated and analyzed. The structural characteristics, physical mechanisms, performance with different parameters, and analog/RF performance of HJ-HD-P-DGTFET are discussed and studied. Simulation results show that the new design of HJ-HD-P-DGTFET performs well in terms of both switching and analog/RF characteristics compared with the conventional Si-DGTFET. Benefitting from SiGe(source)/Si(channel) heterojunction and the heavily doped pocket within the channel, the I_on for HJ-HD-P-DGTFET is increased by nearly two orders of magnitude compared with conventional Si-DGTFET due to the increase in the tunneling rate. Owing to the use of a high-k HfO₂ gate dielectric in the source region and low-k SiO₂ gate dielectric in the drain region, which weakens the gate control of the channel-drain tunneling junction, the I_amb is clearly suppressed, and the I_on/I_off ratio is greatly improved. Finally, a large I_on of 7.79 × 10⁻⁵ A/μm, a suppressed I_off of 8.16 × 10⁻¹⁸ A/μm, I_on/I_off of 9.55 × 10¹², SS_min of 19 mV/dec, f_T of 19.95 GHz, and GBW of 2.07 GHz can be achieved by HJ-HD-P-DGTFET. Therefore, HJ-HD-P-DGTFET can be a potential candidate for future low-power IC applications.