Search Results (41)

This study presents a photoresist-free patterning method for solution-processed indium zinc oxide (IZO) thin films using two photochemical exposure techniques, namely pulsed ultraviolet (UV) light and UV-ozone, and a plasma-based method using oxygen (O₂) plasma. Pulsed UV light delivers short, high-intensity flashes of light that induce localised photochemical reactions with minimal thermal damage, whereas UV-ozone enables smooth and uniform surface oxidation through continuous low-pressure UV irradiation combined with in situ ozone generation. By contrast, O₂ plasma generates ionised oxygen species via radio frequency (RF) discharge, allowing rapid surface activation, although surface damage may occur because of energetic ion bombardment. All three approaches enabled pattern formation without the use of conventional photolithography or chemical developers, and the UV-ozone method produced the most uniform and clearly defined patterns. The patterned IZO films were applied as active layers in bottom-gate top-contact thin-film transistors, all of which exhibited functional operation, with the UV-ozone-patterned devices exhibiting the most favourable electrical performance. This comparative study demonstrates the potential of photochemical and plasma-assisted approaches as eco-friendly and scalable strategies for next-generation IZO patterning in electronic device applications. Full article

A two-step annealing treatment was applied on a fully transparent amorphous InGaZnO4 (a-IGZO) top-gate thin-film transistor (TG-TFT) to improve the device performance. The electrical properties and stabilities of a-IGZO TG TFTs were significantly improved as the first-annealing temperature increased from 150 °C to 350 °C with a 300 °C second-annealing treatment. The a-IGZO TG-TFT with the 300 °C first-annealing treatment demonstrated the overall best performance, which has a mobility of 13.05 cm²/(V·s), a threshold voltage (V_th) of 0.33 V, a subthreshold swing of 130 mV/dec, and a I_on/I_off of 1.73 × 10⁸. The V_th deviation (ΔV_th) was −0.032 V and −0.044 V, respectively, after a 7200 s positive and negative bias stress under the gate bias voltage V_G = ±3 V and V_D = 0.1 V. The Photoluminescence spectra results revealed that the distribution and the density of defects in a-IGZO films were changed after the first-annealing treatment, whereas the X-ray photoelectron spectroscopy results displayed that contents of the oxygen vacancy and Ga-O bond varied in annealed a-IGZO films. In addition, a-IGZO TG-TFTs had achieved a transmittance of over 90%. Research on the effects of the first-annealing treatment will contribute to the fabrication of highly stable top-gate TFTs in the fields of transparent flexible electronics. Full article

In this work, we report the properties of molybdenum disulfide (MoS₂) thin films deposited on the p-type silicon substrate using RF magnetron sputtering. The structural, vibrational and morphological properties of MoS₂ thin films were investigated using the Raman spectroscopy, X-ray diffraction technique (XRD), atomic force microscope (AFM) and scanning electron microscope (SEM). Raman spectroscopy result showed the appearance of broad E¹_2g and A_1g Raman peaks even without DC biasing the substrate and becomes sharp and distinct when the substrate is DC biased at 60 V. Post-deposition annealing in sulfur ambient resulted in sharp and distinct Raman E¹_2g and A_1g peaks confirming the formation of MoS₂ thin film and improved Mo-S bonding on the top surface. X-ray diffraction spectra of the samples validates the formation of MoS₂ thin film with the appearance of [002] XRD peak, when the substrates are biased. Improved morphological effects with the reduction in nano-sized defects, advent of continuous film and low surface rms roughness value of 0.872 nm, were observed on samples deposited with substrate biasing and post sulfur annealing. A back-gated thin film transistor was fabricated with Al as source-drain contacts and MoS₂ as the semiconducting channel. The fabricated transistor exhibited p-type transfer characteristics with threshold voltage of −3.8 V. As a result of annealing and ambient exposure, MoO₃ fragments on the top of thinned MoS₂ layer resulted in extraction of hole from MoS₂, resulting in the p-type behavior in the fabricated thin film transistor. The combination of XRD analysis, Raman measurements and EDS data of the film confirmed MoO₃ inclusions in the MoS₂ thin film. Full article

Inductively coupled plasma–reactive etching (ICP-RIE) of InGaZnO (IGZO) thin films was studied with variations in gas mixtures of hydrochloride (HCl) and argon (Ar). The dry etching characteristics of the IGZO films were investigated according to radiofrequency bias power, gas mixing ratio, and chamber pressure. The IGZO film showed an excellent etch rate of 83.2 nm/min from an optimized etching condition such as a plasma power of 100 W, process pressure of 3 mTorr, and HCl ratio of 75% (HCl:Ar at 30 sccm:10 sccm). In addition, this ICP-RIE etching condition with a high HCl composition ratio at a moderate RIE power of 100 W showed a low etched pattern skew and low photoresist damage on the IGZO patterns. It also provided excellent surface morphology of the SiO₂ film underneath after the entire dry etching of the IGZO layer. The IGZO thin film as an active layer was successfully patterned under the ICP-RIE dry etching under the HCl-Ar gas mixture, affording an excellent electrical characteristic in the resultant top-gate IGZO thin-film transistor. Full article

The Cu undercut is a recently discovered new defect generated in the wet stripping process of MoNb/Cu gate stacked electrodes for thin-film transistors (TFTs). The formation mechanism and preventive strategy of this defect were identified and investigated in this paper. The impact of stripper concentration and stripping times on the morphology and the corrosion potential (E_corr) of Cu and MoNb were studied. It is observed that the undercut is Cu tip-deficient, not the theoretical MoNb indentation, and the undercut becomes severer with the increase in stripping times. The in-depth mechanism analysis revealed that the abnormal Cu undercut was not ascribed to the galvanic corrosion between MoNb and Cu but to the local crevice corrosion caused by the corrosive medium intruding along the MoNb/Cu interface. Based on this newly found knowledge, three possible prevention schemes (MoNiTi (abbreviated as Mo technology development (MTD) layer/Cu), MoNb/Cu/MTD, and MoNb/Cu/MoNb) were proposed. The experimental validation shows that the Cu undercut can only be completely eliminated in the MoNb/Cu/MTD triple-stacked structure with the top MTD layer as a sacrificial anode. This work provides an effective and economical method to avoid the Cu undercut defect. The obtained results can help ensure TFT yield and improve the performance of TFT devices. Full article

In this paper, the effect of a buffer layer created using different hydrogen-containing ratios of reactive gas on the electrical properties of a top-gate In-Ga-Zn-O thin-film transistor was thoroughly investigated. The interface roughness between the buffer layer and active layer was characterized using atomic force microscopy and X-ray reflection. The results obtained using Fourier transform infrared spectroscopy show that the hydrogen content of the buffer layer increases with the increase in the hydrogen content of the reaction gas. With the increase in the hydrogen-containing materials in the reactive gas, field effect mobility and negative bias illumination stress stability improve nearly twofold. The reasons for these results are explained using technical computer-aided design simulations. Full article

Printing technology will improve the complexity and material waste of traditional deposition and lithography processes in device fabrication. In particular, the printing process can effectively control the functional layer stacking and channel shape in thin-film transistor (TFT) devices. We prepared the patterning indium gallium zinc oxide (IGZO) semiconductor layer with Ga, In, and Zn molar ratios of 1:2:7 on Si/SiO₂ substrates. And the patterning source and drain electrodes were printed on the surface of semiconductor layers to construct a TFT device with the top contact and bottom gate structures. To overcome the problem of uniform distribution of applied voltages between electrode centers and edges, we investigated whether the circular arc channel could improve the carrier regulation ability under the field effect in printed TFTs compared with a traditional structure of rectangular symmetry and a rectangular groove channel. The drain current value of the IGZO TFT with a circular arc channel pattern was significantly enhanced compared to that of a TFT with rectangular symmetric source/drain electrodes under the corresponding drain–source voltage and gate voltage. The field effect properties of the device were obviously improved by introducing the arc-shaped channel structure. Full article

The effect of the channel interface of top-gate InGaZnO (IGZO) thin film transistors (TFTs) on the electrical properties caused by exposure to various wet chemicals such as deionized water, photoresist (PR), and strippers during the photolithography process was studied. Contrary to the good electrical characteristics of TFTs including a protective layer (PL) to avoid interface damage by wet chemical processes, TFTs without PL showed a conductive behavior with a negative threshold voltage shift, in which the ratio of Ga and Zn on the IGZO top surface reduced due to exposure to a stripper. In addition, the wet process in photolithography increased oxygen vacancy and oxygen impurity on the IGZO surface. The photo-patterning process increased donor-like defects in IGZO due to organic contamination on the IGZO surface by PR, making the TFT characteristics more conductive. The introduction of ozone (O₃) annealing after photo-patterning and stripping of IGZO reduced the increased defect states on the surface of IGZO due to the wet process and effectively eliminated organic contamination by PR. In particular, by controlling surface oxygens on top of the IGZO surface excessively generated with O₃ annealing using UV irradiation of 185 and 254 nm, IGZO TFTs with excellent current–voltage characteristics and reliability could be realized comparable to IGZO TFTs containing PL. Full article

The preparation of thin-film transistors (TFTs) with InGaZnO (IGZO) channels using sol–gel technology has the advantages of simplicity in terms of process and weak substrate selectivity. We prepared a series of TFT devices with a top contact and bottom gate structure, in which the top contact was divided into rectangular and circular structures of drain/source electrodes. The field-effect performance of TFT devices with circular pattern drain/source electrodes was better than that with a traditional rectangular structure on both substrates. The uniform distribution of the potential in the circular electrode structure was more conducive to the regulation of carriers under the same channel length at different applied voltages. In addition, with the development of transparent substrate devices, we also constructed a hafnium oxide (HfO₂) insulation layer and an IGZO active layer on an indium tin oxide conductive substrate, and explored the effect of circular drain/source electrodes on field-effect properties of the semitransparent TFT device. The IGZO deposited on the HfO₂ dielectric layer by spin-coating can effectively reduce the surface roughness of the HfO₂ layer and optimize the scattering of carriers at the interface in TFT devices. Full article

In this paper, a facile modifying technique of source/drain regions conductivity was proposed for self-aligned top-gate In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) by controlling the process parameter of the passivation layer at relatively low temperatures. The sheet resistance of the source and drain regions of IGZO was approximately 365 Ω/□, and there was no significant change within a month. The device parameters of mobility, threshold voltage, subthreshold swing, and current switching ratio of the fabricated device were 15.15 cm²V⁻¹s⁻¹, 0.09 V, 0.15 V/dec, and higher than 10⁹, respectively. The threshold voltage drift under negative bias illumination stress was −0.34 V. In addition, a lower channel width-normalized contact resistance of 9.86 Ω·cm was obtained. Full article

Solution-processed single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs) in the research stage often have large active areas. This results in unusual gate leakage currents with high magnitudes that vary with applied voltages. In this paper, we report an improved structure for solution-processed SWCNT-based TFTs. The unusual gate leakage current in the improved structure is resolved by patterning the SWCNT active layer to confine it to the channel region. For comparative purposes, this improved structure is compared to a traditional structure whose unpatterned SWCNT active layer expands well beyond the channel region. As TFT performance also varies with oxide layer thickness, 90 nm and 300 nm thick oxides were considered. The improved TFTs have gate leakage currents far lower than the traditional TFT with the same dimensions (aside from the unpatterned active area). Moreover, the unusual variation in gate leakage current with applied voltages is resolved. Patterning the SWCNT layer, increasing the oxide thickness, and reducing the top electrode length all help prevent a rapid dielectric breakdown. To take advantage of solution-based fabrication processes, the active layer and electrodes of our TFTs were fabricated with solution-based depositions. The performance of the TFT can be further improved in the future by increasing SWCNT solution incubation time and reducing channel size. Full article

In this work, a promising dual-gated thin film transistor (TFT) structure has been proposed and introduced in the shift register (SR)-integrated circuits to reduce the rising time. The threshold voltage can be simultaneously changed by the top gate and the bottom gate in the proposed dual-gated TFTs. When the SR circuits start to export the scan signals in the displays, the driving currents in the SR circuits are increased by switching the working station of driving TFTs from the enhancement characterization to the depletion characterization. Subsequently, the detailed smart spice simulation has been used to study the function of the proposed SR circuits. In the next step, the proposed SR circuits have been fabricated in a G4.5 active-matrix organic light-emitting diode manufacture factory. The simulated and experimental results indicate that the shift register pulses with the full swing amplitude can be obtained in the SR circuits. Moreover, in contrast to the conventional SR circuits employing with the single-gated TFTs, it has been found that the rising time of the output signals can be reduced from 3.75 μs to 1.23 μs in the proposed SR circuits with the dual-gated TFTs, thus exhibiting the significant improvement of the driving force in the proposed SR circuits. Finally, we demonstrated a 31-inch 4K AMOLED display with the proposed SR circuits. Full article

We prepared amorphous indium–gallium–zinc oxide (a-IGZO) thin films with various Ga content ratios and investigated their feasibility as the active channel layers of top-gate thin-film transistors (TFT). First, the 2-inch IGZO sputtering targets with stoichiometric ratios of InGaZn₂O₅, InGaZnO₄, and InGa₂ZnO_5.5 were fabricated using In₂O₃, Ga₂O₃, and ZnO oxide powders as raw materials via sintering treatments at temperatures ranging from 900 °C to 1300 °C for 6 h or 8 h. X-ray diffraction analysis indicated that the InGaZn₂O₅ and InGaZnO₄ targets are single-phase structures whereas the InGa₂ZnO_5.5 target is a two-phase structure. Hall effect measurement indicated that the a-InGaZn₂O₅ and a-InGaZnO₄ layers possess a carrier concentration (N) of about 10¹⁹ cm⁻³ and a resistivity (ρ) of about 10⁻² Ω·cm; however, the N of the a-InGa₂ZnO_5.5 layer is only 10¹⁷ cm⁻³, and the ρ is about 1 to 4 Ω·cm. Moreover, the a-InGaZn₂O₅ layer exhibited the highest Hall-effect mobility (μ_Hall) of 21.17 cm²·V⁻¹·sec⁻¹. This indicated that the impedance of Ga³⁺ ions to carrier migration is the main factor affecting the electrical properties of a-IGZO layers. Ga content in the a-IGZO channel similarly affects the performance of the TFT devices prepared in this study. The annealing at 300 °C for 1 h in an ambient atmosphere was found to significantly improve the electrical properties of the TFT devices. The best performance was observed in the a-InGaZnO₄ TFT sample subjected to post-annealing at 300 °C with V_th = −0.85 V, μ_FE = 8.46 cm², V⁻¹·sec⁻¹, SS = 2.31, V·decade⁻¹, and I_on/I_off = 2.9 × 10⁴. Full article

The gate insulator is one of the most crucial factors determining the performance of a graphene field effect transistor (GFET). Good electrostatic control of the conduction channel by gate voltage requires thin gate oxides. Due to the lack of the dangling bond, a seed layer is usually needed for the gate dielectric film grown by the atomic layer deposition (ALD) process. The seed layer leads to the high-quality deposition of dielectric films, but it may lead to a great increase in the thickness of the final dielectric film. To address this problem, this paper proposes an improved process, where the self-oxidized Al₂O₃ seed layer was removed by etching solutions before atomic layer deposition, and the Al₂O₃ residue would provide nucleation sites on the graphene surface. Benefiting from the decreased thickness of the dielectric film, the transconductance of the GFET using this method as a top-gate dielectric film deposition process shows an average 44.7% increase compared with the GFETs using the standard Al evaporation seed layer methods. Full article

Transparent conductive oxides (TCO) have been extensively investigated as channel materials for thin-film transistors (TFTs). In this study, highly transparent and conductive InSnO (ITO) and ZnO films were deposited, and their material properties were studied in detail. Meanwhile, we fabricated ZnO/ITO heterojunction TFTs, and explored the effects of channel structures on the hump characteristics of ZnO/ITO TFTs. We found that V_hump–V_ON was negatively correlated with the thickness of the bottom ZnO layer (10, 20, 30, and 40 nm), while it was positively correlated with the thickness of the top ITO layer (3, 5, 7, and 9 nm), where V_hump is the gate voltage corresponding to the occurrence of the hump and V_ON is the turn-on voltage. The results demonstrated that carrier transport forms dual current paths through both the ZnO and ITO layers, synthetically determining the hump characteristics of the ZnO/ITO TFTs. Notably, the hump was effectively eliminated by reducing the ITO thickness to no more than 5 nm. Furthermore, the hump characteristics of the ZnO/ITO TFTs under positive gate-bias stress (PBS) were examined. This work broadens the practical application of TCO and provides a promising method for solving the hump phenomenon of oxide TFTs. Full article