A Simple Doping Process Achieved by Modifying the Passivation Layer for Self-Aligned Top-Gate In-Ga-Zn-O Thin-Film Transistors at 200 °C

In this paper, a facile modifying technique of source/drain regions conductivity was proposed for self-aligned top-gate In-Ga-Zn-O (IGZO) thin-film transistors (TFTs) by controlling the process parameter of the passivation layer at relatively low temperatures. The sheet resistance of the source and drain regions of IGZO was approximately 365 Ω/□, and there was no significant change within a month. The device parameters of mobility, threshold voltage, subthreshold swing, and current switching ratio of the fabricated device were 15.15 cm2V−1s−1, 0.09 V, 0.15 V/dec, and higher than 109, respectively. The threshold voltage drift under negative bias illumination stress was −0.34 V. In addition, a lower channel width-normalized contact resistance of 9.86 Ω·cm was obtained.


Introduction
Nowadays, amorphous indium gallium zinc oxide (a-IGZO) receives significant attention as an active layer of thin film transistors (TFTs) in the display industry because of its high mobility, very low off-state current, low process temperature, and intermittent refreshing [1][2][3][4][5][6][7]. The typical bottom gate structure of AOS TFTs, including back-channeletch and etch-stopper-layer, inevitably suffer from resistor-capacitor delay and image lagging, which is mainly due to the parasitic capacitance formed by the overlap between the gate (G)-source/drain (S/D) electrodes [8]. However, the source/drain and gate of the self-aligned top gate (SATG) structure are located on the same side of the active layer and have relatively small parasitic capacitance, so they have drawn the attention of more and more researchers [5,[9][10][11][12][13][14]. The key technical challenge of SATG TFT is how to form sourcedrain regions with low resistance. Up to now, several solutions have been put forward to rise to this challenge, such as ion implantations [9], metal reaction-induced [5,10], plasma treatment [11], and hydrogen (H) doping in time of interlayer dielectric or passivation deposition [12,13]. Nevertheless, some problems with these methods cannot be ignored. Regarding the high activation temperature of ion implantations, guaranteed precise film thickness with metal reaction-induced, plasma-induced damages effect the plasma as a result of the uncontrollable rapid hydrogen diffusion of the high-temperature activation process with hydrogen incorporation. Furthermore, low-resistance IGZO films can also be prepared by coating with organic interlayer dielectric [15] or ultraviolet irradiation [16], which may result in an undercut and worse step coverage due to the gate stack directly formed by one-step dry etching. Based on the key technical challenges of SATG TFTs, there are currently few reports on the indirect processing of IGZO source-drain regions to form highly conductive regions in active oxide channels. Thus, in this study, we propose the vertical diffusion of hydrogen by modifying the hydrogen content of the passivation layer process to form low-resistance IGZO source-drain regions for indirectly realizing self-aligns. This simple doping process not only optimizes the process steps for reducing Nanomaterials 2022, 12, 4021 2 of 7 the resistance of the source/drain regions but also improves the water and oxygen barrier capabilities of the device. SATG TFTs with good electrical properties and excellent negative bias illumination stress (NBIS) stability were successfully fabricated under a low-temperature process.

Materials and Methods
First of all, a 200 nm thick buffer layer with SiO 2 was deposited on 200 × 200 mm glass by plasma-enhanced chemical vapor deposition (PECVD). Then, the IGZO with a thickness of 40 nm was sputtered as an active layer and was patterned using a wet etchant. Furthermore, SiO 2 (SiH 4 /N 2 O = 6/94) with the thickness of 300 nm was deposited as a gate insulating layer (GI) by PECVD at 200 • C. Secondly, Mo (30 nm)/ITO (5 nm) was sputtered as a gate electrode using magnetron sputtering. Next, the gate electrode was formed by a two-step wet etch of the Mo/ITO stack. After SiO 2 (SiH 4 /N 2 O = 6/94) or Si 3 N 4 (SiH 4 /NH 3 /N 2 = 6/22/72) with a thickness of 200 nm was deposited as a passivation layer (PA) at 200 • C., the n + IGZO extension regions (the size of one side is 25 × 50 µm 2 ) were automatically formed through the gate. Moreover, the contact holes were exposed by dry etching. In the end, the ITO with a thickness of 35 nm was sputtered again by sputtering as a source-drain electrode. It is worth noting that the process temperature during device fabrication was not higher than 200 • C. The channel width of the device was fixed at 50 µm, and the channel length (L) was 4 µm, 6 µm, and 8 µm, respectively. Figure 1a,b represents the schematic cross-section and top optical image of the SATG IGZO TFT, respectively. of the passivation layer process to form low-resistance IGZO source-drain region directly realizing self-aligns. This simple doping process not only optimizes the steps for reducing the resistance of the source/drain regions but also improves th and oxygen barrier capabilities of the device. SATG TFTs with good electrical prope excellent negative bias illumination stress (NBIS) stability were successfully fabricate a low-temperature process.

Materials and Methods
First of all, a 200 nm thick buffer layer with SiO2 was deposited on 200 × 200 m by plasma-enhanced chemical vapor deposition (PECVD). Then, the IGZO with ness of 40 nm was sputtered as an active layer and was patterned using a wet Furthermore, SiO2 (SiH4/N2O = 6/94) with the thickness of 300 nm was deposited insulating layer (GI) by PECVD at 200 °C. Secondly, Mo (30 nm)/ITO (5 nm) was sp as a gate electrode using magnetron sputtering. Next, the gate electrode was form two-step wet etch of the Mo/ITO stack. After SiO2 (SiH4/N2O = 6/94) or Si3N4 (SiH4 = 6/22/72) with a thickness of 200 nm was deposited as a passivation layer (PA) at the n + IGZO extension regions (the size of one side is 25 × 50 μm 2 ) were autom formed through the gate. Moreover, the contact holes were exposed by dry etchin end, the ITO with a thickness of 35 nm was sputtered again by sputtering as a drain electrode. It is worth noting that the process temperature during device fab was not higher than 200 °C. The channel width of the device was fixed at 50 μm, channel length (L) was 4 μm, 6 μm, and 8 μm, respectively. Figure 1a,b repres schematic cross-section and top optical image of the SATG IGZO TFT, respective

Results and Discussion
To verify the effect of the passivation layer process with different hydrogen on device characteristics, SATG IGZO TFTs with three passivation layers were fa without a passivation layer (w/o). SiO2 and Si3N4, respectively, represent the low, m and high hydrogen content in the passivation layer film.
The transfer performance with SATG IGZO TFTs with different passivation i in Figure  The electrical characteristics for the fabricated a-IGZO TFTs were measured using Keithley 4200. We define the corresponding gate voltage (V GS ) when the leakage current (I DS ) is 1 nA as the threshold voltage (V TH ) of the TFT device. The mobility (µ) was calculated according to the following equation where C i is the gate of the capacitance per unit area. The sheet resistance was measured by the 3 m mini type four-probe tester in the dark at 300 K. The light source used in the NBIS tests was white light with a brightness of 10,000 lux by applying V G-Stress = −10 V of 1000 s with source and drain electrodes grounded. The light source was emitted from the bottom of the device.

Results and Discussion
To verify the effect of the passivation layer process with different hydrogen contents on device characteristics, SATG IGZO TFTs with three passivation layers were fabricated without a passivation layer (w/o). SiO 2 and Si 3 N 4 , respectively, represent the low, medium, and high hydrogen content in the passivation layer film.
The transfer performance with SATG IGZO TFTs with different passivation is shown in Figure 2a. When the hydrogen concentration of the passivation layer increases, the µ increases from 0.31 to 15.15 cm 2 V −1 s −1 , threshold voltage (V TH ) from 3.91 V to 0.09 V, subthreshold swing (SS) from 0.10 V/dec to 0.15 V/dec, and I on /I off increases from 1.17 × 10 8 to 2.86 × 10 9 . Figure 2b show the output characteristic of TFT with Si 3 N 4 as passivation. The output characteristics show good ohmic contact at low drain voltages and low source/drain resistance [17]. This can be attributed to not only higher electron mobility but also lower contact resistance [10,18].  Figure 2b show the output characteristic of TFT with Si3N4 as passivation.
The output characteristics show good ohmic contact at low drain voltages and low source/drain resistance [17]. This can be attributed to not only higher electron mobility but also lower contact resistance [10,18]. It can be intuitively seen from Figure 2a that the Ion of the device gradually increases from ~10 6 A to ~10 4 A as the hydrogen content increases. Although the IGZO/GI interface will have a serious impact on Ion, the fabrication processes of the three devices are basically the same, that is, the IGZO/GI interface defects should be the same, which can be reflected from the SS value with no obvious change. Therefore, the increase of Ion is mainly due to the decrease of the contact resistance. After the passivation layer is deposited, since the passivation layer contains a high concentration of hydrogen, a large amount of hydrogen will first pass through the insulating layer from the passivation layer and then vertically diffuse to the IGZO layer [19]. In addition, because the densified gate can block the diffusion of hydrogen, hydrogen will vertically diffuse down to the IGZO layer along the edge of the gate, reducing the resistance and self-aligning to form the IGZO source and drain regions. Although a small amount of hydrogen will diffuse laterally, it will only remain in the insulating layer above the channel. As the hydrogen content in the passivation layer increases, the hydrogen diffused into the IGZO layer must increase, so the formed IGZO source and drain regions have better conductivity, and the TFT device has smaller parasitic resistance. At the same time, the channel carrier concentration increases, and the VTH shifts to the left.
To demonstrate that the contact resistance is reduced, the sheet resistance of S/D regions in the IGZO was measured. Figure 3a show the variation of sheet resistance of the IGZO source and drain regions with deposition temperature. The sheet resistance decreases gradually with the increase of deposition temperature. At 150 °C, the sheet resistance corresponding to the Si3N4 passivation layer is much lower than that of SiO2, but when the temperature increases to 200 °C, the effects of the two passivation layers are similar and remain basically unchanged. The sheet resistance varies around 365 Ω/. Therefore, its resistivity is 1.5 × 10 −3 Ω·cm because its thickness is 40 nm. Table 1 summarize the resistance and device mobility obtained by different treatments for the source and drain regions of IGZO. In this work, the PA/GI processing approach exhibits low resistivity and high device mobility and achieves a level comparable to other methods.  It can be intuitively seen from Figure 2a that the I on of the device gradually increases from~10 6 A to~10 4 A as the hydrogen content increases. Although the IGZO/GI interface will have a serious impact on I on , the fabrication processes of the three devices are basically the same, that is, the IGZO/GI interface defects should be the same, which can be reflected from the SS value with no obvious change. Therefore, the increase of I on is mainly due to the decrease of the contact resistance. After the passivation layer is deposited, since the passivation layer contains a high concentration of hydrogen, a large amount of hydrogen will first pass through the insulating layer from the passivation layer and then vertically diffuse to the IGZO layer [19]. In addition, because the densified gate can block the diffusion of hydrogen, hydrogen will vertically diffuse down to the IGZO layer along the edge of the gate, reducing the resistance and self-aligning to form the IGZO source and drain regions. Although a small amount of hydrogen will diffuse laterally, it will only remain in the insulating layer above the channel. As the hydrogen content in the passivation layer increases, the hydrogen diffused into the IGZO layer must increase, so the formed IGZO source and drain regions have better conductivity, and the TFT device has smaller parasitic resistance. At the same time, the channel carrier concentration increases, and the V TH shifts to the left.
To demonstrate that the contact resistance is reduced, the sheet resistance of S/D regions in the IGZO was measured. Figure 3a show the variation of sheet resistance of the IGZO source and drain regions with deposition temperature. The sheet resistance decreases gradually with the increase of deposition temperature. At 150 • C, the sheet resistance corresponding to the Si 3 N 4 passivation layer is much lower than that of SiO 2 , but when the temperature increases to 200 • C, the effects of the two passivation layers are similar and remain basically unchanged. The sheet resistance varies around 365 Ω/ . Therefore, its resistivity is 1.5 × 10 −3 Ω·cm because its thickness is 40 nm. Table 1 summarize the resistance and device mobility obtained by different treatments for the source and drain regions of IGZO. In this work, the PA/GI processing approach exhibits low resistivity and high device mobility and achieves a level comparable to other methods.  As shown in Figure 3b, with the passage of time, the two passivation layers have different changes to the IGZO source and drain regions. The Si3N4 passivation layer maintained good stability for one month, while the SiO2 passivation layer showed poor stability. After 3 days, the sheet resistance increased to more than 156 kΩ/, increased to about 526 kΩ/ after a week, and exceeded the test limit of the device after a month. This can be attributed to the low hydrogen content in the SiO2 film, which has an insufficient degree of influence on the IGZO film. With the increase of the standing time, the hydrogen in the SiO2 film diffused outward, reducing the hydrogen content in the IGZO film, and thus the sheet resistance increased.
The contact resistance (RC) was calculated according to the transmission line method. It includes the contact resistance between the metal and semiconductor and the resistance of the S/D extension part inside the semiconductor. The following equation may be used to calculate the Rtot [15]: RS is the channel resistance. Figure 3c show the total resistance (Rtot) corresponding to different L at various VGS. The transmission line method was used to extract the widthnormalized RC (RC·W ) and the diffusion distance, as shown in Figure 3d [5]. For SATG IGZO TFT with Si3N4 passivation layer, the RC·W values were approximately 9.86 Ω·cm, and the lateral diffusion distance was only 0.07 μm.  As shown in Figure 3b, with the passage of time, the two passivation layers have different changes to the IGZO source and drain regions. The Si 3 N 4 passivation layer maintained good stability for one month, while the SiO 2 passivation layer showed poor stability. After 3 days, the sheet resistance increased to more than 156 kΩ/ , increased to about 526 kΩ/ after a week, and exceeded the test limit of the device after a month. This can be attributed to the low hydrogen content in the SiO 2 film, which has an insufficient degree of influence on the IGZO film. With the increase of the standing time, the hydrogen in the SiO 2 film diffused outward, reducing the hydrogen content in the IGZO film, and thus the sheet resistance increased.
The contact resistance (R C ) was calculated according to the transmission line method. It includes the contact resistance between the metal and semiconductor and the resistance of the S/D extension part inside the semiconductor. The following equation may be used to calculate the R tot [15]: R S is the channel resistance. Figure 3c show the total resistance (R tot ) corresponding to different L at various V GS . The transmission line method was used to extract the widthnormalized R C (R C ·W) and the diffusion distance, as shown in Figure 3d [5]. For SATG Nanomaterials 2022, 12, 4021 5 of 7 IGZO TFT with Si 3 N 4 passivation layer, the R C ·W values were approximately 9.86 Ω·cm, and the lateral diffusion distance was only 0.07 µm.
To verify the prospect of passivation in practical applications of SATG IGZO TFT, the NBIS is shown in Figure 4. As the time of illumination and gate voltage are increased, the V TH drifts in the negative direction. However, the threshold voltage drift (∆V TH ) of TFTs with w/o or SiO 2 is reduced from −1.19 V or −1.04 V to −0.34 V compared to TFTs with Si 3 N 4 . This shows that the Si 3 N 4 can improve device stability. The V TH drift under NBIS is mainly due to the formation of positively ionized oxygen vacancies under the combined effect of illumination and negative gate voltage [20]. The ∆V TH for SATG IGZO TFTs with Si 3 N 4 as passivation is as low as −0.32 V, which may be due to the reduction of positive charge  [21]. In addition, as the hydrogen in the passivation layer increases, the lateral diffusion of hydrogen remaining in the insulating layer also increases. In subsequent processes, hydrogen will diffuse from the GI to the IGZO/GI interface, passivate the V O -related point defects, and reduce the deep donor electron traps [4,20]. At the same time, hydrogen implantation from GI to the IGZO/GI interface also increases the carrier concentration and reduces the interfacial trap states, thereby reducing ∆V TH [22,23]. To verify the prospect of passivation in practical applications of SATG IGZO TFT, the NBIS is shown in Figure 4. As the time of illumination and gate voltage are increased, the VTH drifts in the negative direction. However, the threshold voltage drift (VTH) of TFTs with w/o or SiO2 is reduced from −1.19 V or −1.04 V to −0.34 V compared to TFTs with Si3N4. This shows that the Si3N4 can improve device stability. The VTH drift under NBIS is mainly due to the formation of positively ionized oxygen vacancies under the combined effect of illumination and negative gate voltage (VO → V  [21]. In addition, as the hydrogen in the passivation layer increases, the lateral diffusion of hydrogen remaining in the insulating layer also increases. In subsequent processes, hydrogen will diffuse from the GI to the IGZO/GI interface, passivate the VO-related point defects, and reduce the deep donor electron traps (H O + O 2− → OH − + e − ) [4,20]. At the same time, hydrogen implantation from GI to the IGZO/GI interface also increases the carrier concentration and reduces the interfacial trap states, thereby reducing VTH [22,23].

Conclusions
In this paper, SATG TFTs were successfully fabricated by modifying the hydrogen content of the passivation layer process under a low-temperature process. The influence of the passivation layer on the electrical properties was compared, and it was proven that the modification of the passivation layer process can effectively reduce the resistance of the source and drain regions of IGZO. The prepared TFT had a low RC·W of 9.86 Ω·cm and a low lateral diffusion distance of 0.07 μm. The fabricated SATG TFT exhibited excellent electrical properties with μ of 15.15 cm 2 V −1 s −1 and Ion/Ioff higher than 10 9 , respectively. Meanwhile, NBIS stability was remarkably improved from −1.19 to −0.34 V.

Conclusions
In this paper, SATG TFTs were successfully fabricated by modifying the hydrogen content of the passivation layer process under a low-temperature process. The influence of the passivation layer on the electrical properties was compared, and it was proven that the modification of the passivation layer process can effectively reduce the resistance of the source and drain regions of IGZO. The prepared TFT had a low R C ·W of 9.86 Ω·cm and a low lateral diffusion distance of 0.07 µm. The fabricated SATG TFT exhibited excellent electrical properties with µ of 15.15 cm 2 V −1 s −1 and I on /I off higher than 10 9 , respectively. Meanwhile, NBIS stability was remarkably improved from −1.19 to −0.34 V.