Search Results (73)

This paper proposed an adaptive bandwidth Phase-Locked Loop (PLL) that integrates integer-N and fractional-N switching for energy-efficient RF synthesis in IoT and mobile applications. The architecture exploits wide-bandwidth integer-N mode for rapid lock acquisition, then seamlessly transitions to narrow-bandwidth fractional-N mode for high-resolution synthesis and noise optimization. The architecture features a bandwidth-reconfigurable loop filter with intelligent switching control that monitors phase error dynamics. A novel adaptive digital noise filter mitigates $\Delta \Sigma$ quantization noise, replacing conventional synchronous delay lines. The multi-loop structure incorporates a high-resolution digital phase detector to enhance frequency accuracy and minimize jitter across both operating modes. With 180 nm CMOS technology, the PLL consumes 13.2 mW, while achieving $-119$ dBc/Hz in-band phase noise and 1 $p{s}_{rms}$ integrated jitter. With an operating frequency range at 2.9–3.2 GHz from a 1.8 V supply, the circuit achieves a worst case fractional spur of −62.7 dBc, which corresponds to a figure of merit (FOM) of −228.8 dB. Lock time improvements of 70% are demonstrated compared to single-mode implementations, making it suitable for high-precision, low-power wireless communication systems requiring agile frequency synthesis. Full article

Push–pull switch-mode power supplies are widely employed due to their high efficiency and power density. However, traditional designs typically depend on multiple auxiliary circuits to achieve functions such as power-up control, voltage regulation, and system protection, resulting in structural complexity and difficulty in debugging. Additionally, dual-power high-voltage amplifier systems often suffer from voltage deviations caused by supply imbalances or load fluctuations, potentially leading to equipment failure and significant economic losses. To overcome these limitations, we propose a novel digital signal-controlled push–pull driver power supply topology in this paper. Specifically, this design utilizes digital pulse-width modulation (PWM) signals to control multi-stage metal-oxide-semiconductor field-effect transistors (MOSFETs), incorporating adjustable duty-cycle drives, multi-channel current sensing, and fault protection mechanisms. Experimental validation was performed on a ±220 V, 20 kHz, 180 W power supply prototype. The results demonstrate excellent performance, notably enhancing stability and reliability in dual-side synchronous power supply scenarios. Thus, this digital-control topology effectively addresses the drawbacks of conventional push–pull designs and offers potential applications in nondestructive testing and high-voltage driving systems. Full article

The 2 × 25 kV flexible traction power supply system (FTPSS), using a three-phase-single-phase converter as its power source, effectively addresses the challenges of neutral section transitions and power quality issues inherent in traditional power supply systems (TPSSs). However, the bidirectional fault current and low short-circuit current characteristics degrade the effectiveness of traditional TPSS protection schemes. This paper analyzes the fault characteristics of FTPSS and proposes a fault identification method based on empirical wavelet transform (EWT) and 1-sequence faulty energy. First, a composite sequence network model is developed to reveal the characteristics of three typical fault types, including ground faults and inter-line short circuits. The 1-sequence differential faulty energy is then calculated. Since the 1-sequence component is unaffected by the leakage impedance of autotransformers (ATs), the proposed method uses this feature to distinguish the TPSS faults from disturbances caused by electric multiple units (EMUs). Second, EWT is used to decompose the 1-sequence faulty energy, and relevant components are selected by permutation entropy. The fault variance derived from these components enables reliable identification of TPSS faults, effectively avoiding misjudgment caused by AT excitation inrush or harmonic disturbances from EMUs. Finally, real-time digital simulator experimental results verify the effectiveness of the proposed method. The fault identification method possesses high tolerance to transition impedance performance and does not require synchronized current measurements from both sides of the TPSS. Full article

Femtosecond lasers have evolved continuously over the past three decades, enabling the transition of research from fundamental studies in atomic and molecular physics to the realm of practical applications. In femtosecond laser amplifiers, to ensure strict synchronization between the seed laser pulse and the pump laser, enabling their precise overlap during the amplification process and avoiding a decline in pulse amplification efficiency and the generation of undesired phase noise, this study designed a synchronous timing signal generation system based on the combination of FPGA and analog delay. This system was investigated from three aspects: delay pulse width adjustment within a certain range, precise delay resolution, and external trigger jitter compensation. By using a FPGA digital counter to achieve coarse-delay control over a wide range and combining it with the method of passive precise fine delay, the system can generate synchronous delay signals with a large delay range, high precision, and multiple channels. Regarding the problem of asynchronous phase between the external trigger and the internal clock, a jitter compensation circuit was proposed, consisting of an active gated integrator and an output comparator, which compensates for the uncertainty of trigger timing through analog delay. The verification of this study shows that the system operates stably under an external trigger with a repetition frequency of 80 MHz. The output delay range is from 10 ns to 100 $\mu$s, the coarse-delay resolution is 10 ns, the fine-delay adjustment step is 1.25 ns, and the pulse jitter is reduced from a maximum of 10 ns to the hundred-picosecond level. This meets the requirements of femtosecond laser amplifiers for synchronous trigger signals and offers essential technical support and fundamental assurance for the high-power and high-efficiency amplification of Ti:sapphire ultrashort laser pulses. Full article

Precise time interval generation is a cornerstone of modern measurement, automation, and distributed control systems, particularly within Internet of Things (IoT) architectures. This paper presents the design, implementation, and evaluation of a low-cost and high-precision time interval generator based on Complementary Metal-Oxide Semiconductor (CMOS) logic counters (Integrated Circuit (IC) IC 7493 and IC 4017) and inverter-based crystal oscillators (IC 74LS04). The proposed system enables frequency division from 1 MHz down to 1 Hz through a cascade of binary and Johnson counters, enhanced with digitally controlled multiplexers for output signal selection. Unlike conventional timing systems relying on expensive Field-Programmable Gate Array (FPGA) or Global Navigation Satellite System (GNSS)-based synchronization, this approach offers a robust, locally controlled reference clock suitable for IoT nodes without network access. The hardware is integrated with Arduino and ESP32 microcontrollers via General-Purpose Input/Output (GPIO) level interfacing, supporting real-time timestamping, deterministic task execution, and microsecond-level synchronization. The system was validated through Python-based simulations incorporating Gaussian jitter models, as well as real-time experimental measurements using Arduino’s micros() function. Results demonstrated stable pulse generation with timing deviations consistently below ±3 µs across various frequency modes. A comparative analysis confirms the advantages of this CMOS-based timing solution over Real-Time Clock (RTC), Network Time Protocol (NTP), and Global Positioning System (GPS)-based methods in terms of local autonomy, cost, and integration simplicity. This work provides a practical and scalable time reference architecture for educational, industrial, and distributed applications, establishing a new bridge between classical digital circuit design and modern Internet of Things (IoT) timing requirements. Full article

The rapid development of digital technologies is opening up new avenues for transforming education, particularly in fields that require practical training, such as electronic circuit design. In this context, this paper presents the development of a multiplayer virtual learning platform that makes use of digital twins technology to offer a realistic, collaborative experience in a simulated environment. Users can interact in real time through synchronized avatars, voice communication, and multiple viewing angles, simulating a physical classroom. Evaluation of the platform with undergraduate students showed positive results in terms of usability, collaboration, and learning effectiveness. Despite the limitations of the sample, the findings reinforce the prospect of virtual laboratories as a modern tool in technical education. Full article

This paper presents an ultrasonic driving and detection system based on a CMUT array using MEMS technology. Among them, the core component CMUT array is composed of 8 × 8 CMUT array elements, and each CMUT array element contains 6 × 6 CMUT units. The collapse voltage of a single CMUT unit obtained through finite element analysis is 95.91 V, and the resonant frequency is 3.16 MHz. The driving section achieves 64-channel synchronous driving, with key parameters including an adjustable excitation signal frequency ranging from 10 kHz to 5.71 MHz, a delay precision of up to 1 ns, and an excitation duration of eight pulse cycles. For the echo reception, a two-stage amplification circuit for high-frequency weak echoes with 32 channels was designed, achieving a gain of 113.72 dB and −3 dB bandwidth of 3.89 MHz. Simultaneously, a 32-channel analog-to-digital conversion based on a self-calibration algorithm was implemented, with a sampling rate of 50 Mbps and a data width of 10 bits. Finally, the experimental results confirm the successful implementation of the driving system’s designed functions, yielding a center frequency of 1.4995 MHz and a relative bandwidth of 127.9%@−6 dB for the CMUT operating in silicone oil. This paper successfully conducted the transmit–receive integrated experiment of the CMUT and applied Butterworth filtering to the echo data, resulting in high-quality ultrasonic echo signals that validate the applicability of the designed CMUT-based system for ultrasonic imaging. Full article

The synchronization of chaotic systems is a fundamental phenomenon in nonlinear dynamics. Most known synchronization techniques suggest that the trajectories of coupled systems converge at an exponential rate. However, this requires transferring a substantial data array to achieve complete synchronization between the master and slave oscillators. A recently developed approach, called time-reversible synchronization, has been shown to accelerate the convergence of trajectories. This approach is based on the special properties of time-symmetric integration. This technique allows for achieving the complete synchronization of discrete chaotic systems at a superexponential rate. However, the validity of time-reversible synchronization between discrete and continuous systems has remained unproven. In the current study, we expand the applicability of fast time-reversible synchronization to a case of digital and analog chaotic systems. A circuit implementation of the Sprott Case B was taken as an analog chaotic oscillator. Given that real physical systems possess more complicated dynamics than simplified models, analog system reidentification was performed to achieve a reasonable relevance between a discrete model and the circuit. The result of this study provides strong experimental evidence of fast time-reversible synchronization between analog and digital chaotic systems. This finding opens broad possibilities in reconstructing the phase dynamics of partially observed chaotic systems. Utilizing minimal datasets in such possible applications as chaotic communication, sensing, and system identification is a notable development of this research. Full article

This work focuses on evaluating the behavior of analog chaos oscillators in field-programmable gate arrays (FPGAs). This work is motivated by a new approach to designing chaos-based communication systems using chaos oscillator circuits implemented in hardware in the transmitter and the mathematical models of the oscillator implemented on an FPGA in the receiver. Such a hybrid approach opens new possibilities for chaos-based modulation schemes for wireless sensor network (WSN) applications. This work brings a hybrid chaos-based communication system closer to realization by implementing the chaos oscillators on an FPGA and achieving analog–discrete and discrete–analog chaotic synchronization. First, this paper derives a model that simulates the dynamics of Vilnius and RC chaos oscillators using Euler–Cromer numerical integration in fixed-point arithmetic. The derived MATLAB model precisely describes the digital design and is thus directly transferred to VHDL. The synthesized digital design is compiled onto an FPGA chip and is then used to achieve analog–discrete and discrete–analog Pecora–Carroll chaotic synchronization. Full article

The digital integrated circuit (IC) design industry is continuously evolving. However, the rapid advancements in technology are accompanied by major reliability concerns. Conventional clock-based synchronous designs become exceedingly susceptible to transient errors, caused by radiation rays, power jitters, electromagnetic interferences (EMIs), and/or other noise sources, primarily due to aggressive device and voltage scaling. quasi-delay-insensitive (QDI) asynchronous (clockless) circuits demonstrate inherent robustness against such transient errors, owing to their unique architecture. However, they are not completely immune. This article presents a hardened QDI Sleep Convention Logic (SCL) asynchronous architecture, which can fully recover from radiation-induced single-event effects such as single-event upset (SEU) and single-event latch-up (SEL). Multiple benchmark circuits are designed based on the proposed architecture. The simulation results indicate that the proposed designs offer substantial energy savings per operation, dissipate substantially less power during idle phases, and have lower area footprints in comparison to designs based on an existing resilient Null Convention Logic (NCL) architecture at the cost of increased latency. In addition, a formal verification framework for the proposed architecture is also presented. The performance and scalability of the proposed verification scheme are demonstrated using several multiplier benchmark circuits of varying width. Full article

This study presents an innovative approach utilizing the new Shimizu–Morioka chaotic system. By integrating adaptive backstepping control with GYC partial region stability theory, we successfully achieve synchronization of a slave system with the proposed Shimizu–Morioka chaotic system. The architecture, encompassing the chaotic master system, synchronized slave system, adaptive backstepping controllers, and parameter update laws, has been implemented on an FPGA platform. Comparative analysis demonstrates that the synchronization convergence times (e1, e2, e3, and e4) are significantly reduced compared to conventional adaptive backstepping control methods, exhibiting speed enhancements of approximately 3.42, 3.55, 5.89, and 9.23 times for e1, e2, e3, and e4, respectively. Furthermore, the synchronization results obtained from continuous-time, discrete-time systems, and FPGA implementations exhibit consistent outcomes, validating the effectiveness of the proposed model and controller. Leveraging this validated synchronization framework, chaotic synchronization and secure image encryption are successfully implemented on the FPGA platform. The chaotic signal circuits are meticulously designed and integrated into the FPGA to facilitate a robust image encryption algorithm. In this system, digital signals generated by the synchronized slave chaotic system are utilized for image decryption, while the master chaotic system’s digital signals are employed for encryption. This dual-system architecture highlights the efficacy of the chaotic synchronization method based on the novel Shimizu–Morioka system for practical applications in secure communication. Full article

At present, the error calibration of electricity meters in operation generally adopts an off-site method; that is, the electricity meter is taken out of operation and then calibrated in the laboratory. Off-site calibration, while beneficial, may not fully capture the operational error of the electricity meter due to potential differences in environmental conditions. An on-site calibration device for electricity meters based on pulse detection is designed, which obtains the error of the electricity meter under calibration by comparing the energy pulses of the standard electricity meter with those of the electricity meter under calibration. High-precision voltage and current sampling channels are designed, with a voltage measurement error of less than 0.02% and a current measurement error of less than 0.03%. In response to the non-synchronous sampling problem caused by frequency fluctuations in the on-site verification environment, a fast optimal frequency estimation algorithm is applied to accurately calculate the signal frequency within two cycles. The sampling time interval is adjusted to achieve lock-frequency synchronous sampling, and ensure the accurate calculation of electrical parameters. In order to reduce the complexity of the device circuit structure and equipment cost, a standard electric energy pulses generation method based on digital integration-to-frequency is proposed, which uses software to generate electric energy pulses, with a maximum output frequency of up to 10 kHz. Tests conducted in the laboratory on the developed on-site calibration device for electricity meters show that its accuracy is better than the 0.05 accuracy class, meeting the application requirements for on-site verification of electricity energy meters. Full article

Meteor radar is a widely used technique for measuring wind in the mesosphere and lower thermosphere, with the key advantage of being unaffected by terrestrial weather conditions, thus enabling continuous operation. In all-sky interferometric meteor radar systems, amplitude and phase consistencies between multiple channels exhibit dynamic variations over time, which can significantly degrade the accuracy of wind measurements. Despite the inherently dynamic nature of these inconsistencies, the majority of existing research predominantly employs static calibration methods to address these issues. In this study, we propose a dynamic adaptive calibration method that combines normalized least mean square and correlation algorithms, integrated with hardware design. We further assess the effectiveness of this method through numerical simulations and practical implementation on an independently developed meteor radar system with a five-channel receiver. The receiver facilitates the practical application of the proposed method by incorporating variable gain control circuits and high-precision synchronization analog-to-digital acquisition units, ensuring initial amplitude and phase consistency accuracy. In our dynamic calibration, initial coefficients are determined using a sliding correlation algorithm to assign preliminary weights, which are then refined through the proposed method. This method maximizes cross-channel consistencies, resulting in amplitude inconsistency of <0.0173 dB and phase inconsistency of <0.2064°. Repeated calibration experiments and their comparison with conventional static calibration methods demonstrate significant improvements in amplitude and phase consistency. These results validate the potential of the proposed method to enhance both the detection accuracy and wind inversion precision of meteor radar systems. Full article

This paper proposes a DEVS (Discrete Event System Specification) formalism-based approach to analyze Clock Domain Crossing (CDC) issues in digital circuit design. As modern System on Chip (SoC) designs increasingly integrate multiple clock domains, the verification of CDC-related metastability becomes more challenging and costly. While conventional EDA tools offer solutions for CDC analysis, they often involve substantial computational resources and licensing costs. We present a DEVS-based simulation framework that leverages its inherent advantages in time management and modular structuring to model and analyze CDC scenarios. The framework includes a CDC synchronizer model implemented within the HDL partially compatible DEVS environment, enabling precise analysis of metastability violations based on setup time and hold time requirements. Circuit designers or related engineers can potentially solve timing issues such as CDC by incorporating DEVS-based analysis tools into the design pipeline. Full article

During the in-orbit operation of spacecraft, permanent magnet synchronous motors are commonly used as power sources in the drive mechanisms of solar panel arrays and the high-precision servo control systems based on satellites. Apart from the performance of the motors themselves and the software control algorithms, the accuracy of the entire control system is also influenced by angle sensors used to detect the rotor position of the motors. As a high-precision angular measuring instrument, the inductosyn possesses excellent environmental adaptability and long service life. Effectively utilizing the inductosyn can greatly enhance the performance of servo control systems. To address the complexity of the decoding process for dual-channel round inductosyn-to-digital converters, this paper proposes a design of the decoding circuit for dual-channel round inductosyn based on the parallel-synchronization decoding method of two AD2S1210 Resolver-to-Digital Converter (RDC) decoding chips. The decoding circuit amplifies the excitation signal outputted by the AD2S1210 for driving the round inductosyn, and processes the sine and cosine induction signals outputted by the round inductosyn through filtering, amplification, and other methods; by using analog circuitry, the output signals of the dual-channel round inductosyn are processed to meet the input requirements of the AD2S1210. Finally, through both the Multisim (circuit simulation software Version 14.1) simulation and physical experiments, it was verified that the decoding circuit designed in this paper could process the input/output signals of the dual-channel round inductosyn and AD2S1210, and successfully decoded the analog induction signal of the round inductosyn. This greatly simplifies the signal decoding process for the dual-channel round inductosyn. Full article