Field-Programmable Gate Array-Based Chaos Oscillator Implementation for Analog–Discrete and Discrete–Analog Chaotic Synchronization Applications

Abstract

This work focuses on evaluating the behavior of analog chaos oscillators in field-programmable gate arrays (FPGAs). This work is motivated by a new approach to designing chaos-based communication systems using chaos oscillator circuits implemented in hardware in the transmitter and the mathematical models of the oscillator implemented on an FPGA in the receiver. Such a hybrid approach opens new possibilities for chaos-based modulation schemes for wireless sensor network (WSN) applications. This work brings a hybrid chaos-based communication system closer to realization by implementing the chaos oscillators on an FPGA and achieving analog–discrete and discrete–analog chaotic synchronization. First, this paper derives a model that simulates the dynamics of Vilnius and RC chaos oscillators using Euler–Cromer numerical integration in fixed-point arithmetic. The derived MATLAB model precisely describes the digital design and is thus directly transferred to VHDL. The synthesized digital design is compiled onto an FPGA chip and is then used to achieve analog–discrete and discrete–analog Pecora–Carroll chaotic synchronization.

1. Introduction

The increasing application of smart interconnected devices in the Internet of Things (IoT) has led to the transformation of various industry sectors. While the primary motivation for this development is to facilitate control, data acquisition, and processing for industrial, medical, agricultural, and many other applications, it is also driven by advances in cellular network technology like 5G. According to the Ericsson mobility report [1], 5G is set to increase the range of IoT use cases, and the number of IoT connections is forecast to surpass 7 billion by 2030.

The increase in data transmission and reliance on interconnected devices poses security challenges. In [2,3], the authors described the taxonomy of security attacks on the IoT, breaking them down into physical, network, and application layers. Over the years, the security question has been addressed by introducing techniques such as encryption, blockchain, and cloud computing [4]. However, these techniques mainly covered the network and application layers, and data transfer security on the physical layer has received considerably less attention. One possible solution is the use of chaos phenomena to enhance communication security.

Chaotic systems are characterized by their sensitivity to initial conditions, wide spectrum, and noise-like waveforms. However, chaotic systems are deterministic, meaning that the system’s dynamics are not random like noise and thus can be exploited controllably. Chaotic systems are based on nonlinearity and can have different physical implementations. In the literature, chaos oscillators are low-power analog circuits that exhibit chaotic behavior and are deliberately designed to act as a source of chaotic signals. The first widely studied chaos oscillators were the Chua chaos oscillator [5], the Colpitts chaos oscillator [6], the Vilnius chaos oscillator [7], the RC chaos oscillator [8], and the Memristor chaos oscillator [9]. Over the years, some authors have introduced modifications to the original circuits [10,11,12], and other circuits have been proposed [13,14,15,16]. Chaos oscillators consist of inductors, capacitors, resistors, diodes, transistors, and operational amplifiers. Chaotic behavior can also be seen in other circuits under specific conditions, such as DC-DC converters, as demonstrated in [17,18].

Regarding discrete chaotic sources, the most common approach is chaotic maps—discrete nonlinear functions. Chaotic maps are commonly used for encryption due to their straightforward, discrete nature [19,20,21,22]. Another way of implementing discrete chaos is by acquiring numerical solutions to nonlinear circuit equations. Although this is a novel approach, it has gained popularity in recent years [23,24] due to better control over initial conditions and mitigation of imprecision of analog components. Discrete chaotic sources have also gained popularity due to the possibility of implementing them in field-programmable gate arrays (FPGAs), as demonstrated in [25,26,27,28,29,30,31,32].

Data transmission security on the physical layer can be addressed by using chaotic signals as carriers. Many chaos-based modulation schemes have been introduced, which can be divided into coherent and non-coherent schemes [33]. Coherent schemes require chaotic synchronization [34,35]; the two chaotic sources are asynchronous due to sensitivity to the initial conditions. Non-coherent schemes do not require chaotic synchronization [36,37]. The key feature of coherent schemes is that data recovery in the receiver is possible only using synchronized sources.

Previously, modulation schemes were designed to use either analog hardware circuits or chaotic maps. Our previous work [38] suggested a hybrid communication system that utilizes low-power analog chaos oscillators at sensor nodes and discrete chaos oscillators in the gateway. The core of such a system is the possibility of analog–discrete and discrete–analog chaotic synchronization. In [38], we demonstrated the possibility of this synchronization in the case of Vilnius and RC chaos oscillators. However, the discrete chaotic oscillator was modeled and implemented only in MATLAB. The current work further develops this system by implementing discrete chaos oscillators on an FPGA and exploring analog–discrete and discrete–analog chaotic synchronization. To summarize, the key contributions of this work are as follows:

• We implement discrete chaos oscillator models in fixed-point arithmetic for FPGA applications;
• We experimentally demonstrate the possibility of chaotic synchronization of the chaos oscillator circuit and discrete model implemented on an FPGA.

Studies centered on chaotic synchronization mainly focus on synchronization techniques for analog chaos oscillators or discrete chaotic maps [39,40,41,42]. In [43,44,45,46,47], the authors focused on the application of chaotic synchronization, while the authors of [25,26,27,28,29,30,31,32] presented the implementation of chaos on FPGAs. To the best of our knowledge, the only notable works that have explored the possibility of synchronizing the analog chaos oscillator and the discrete model of the oscillator are [23,48]. However, the authors only explored the analog–discrete synchronization case. The novelty of this work lies in the implementation and verification of FPGA-based analog–discrete and discrete–analog chaotic synchronization.

This paper is structured as follows. Section 2 details the steps of implementing Vilnius and RC chaos oscillators on an FPGA. It starts with the chaos oscillators and their state-variable differential equations, followed by the discrete implementation of these equations in fixed-point arithmetic, which leads to hardware implementation and the derivation of an accurate model. Section 3 verifies the possibility of chaotic synchronization between chaos oscillators implemented in circuit form and their FPGA-based counterparts. Section 4 studies the noise immunity of chaotic synchronization by comparing analog–discrete and discrete–analog synchronization methods. Section 4 concludes this work.

2. Chaos Oscillator FPGA Implementation

This section describes the FPGA implementation of chaos oscillators. It also describes the chaos oscillators, including their theory of operation through state-variable differential equations, followed by crucial details and design solutions for their digital implementation. In addition, it provides the implementation details for the Vilnius [7] and RC [8] chaos oscillators; however, the approach can also be applied to other chaos systems.

2.1. Vilnius Chaos Oscillator

The first oscillator used in this work is the Vilnius chaos oscillator [7]. The circuit of the oscillator is shown in Figure 1a, while the hardware implementation of the circuit, using discrete components on an FR4 PCB, is shown in Figure 1b.

The dynamics of this oscillator are described using differential equations in (1). The state variables are the voltages across $C_1$ and $C_2$ and the current through $L_1$.

$$\left\{\begin{array}{c}{C}_1{\displaystyle \frac{\mathrm{d}{v}_{C_1}}{\mathrm{d}t}}=i_{L_1},\hfill \\ L_1{\displaystyle \frac{\mathrm{d}{i}_{L_1}}{\mathrm{d}t}}=(k-1)·R_1·i_{L_1}-v_{C_1}-v_{C_2},\hfill \\ C_2{\displaystyle \frac{\mathrm{d}{v}_{C_2}}{\mathrm{d}t}}=i_0+i_{L_1}-i_D,\hfill \end{array}\right.$$

(1)

where $i_D$ is the current of the diode $D_1$; $i_0$ is the current of the resistor $R_4$; and k is the gain of the operational amplifier circuit. The system’s nonlinearity is introduced with the diode’s current:

$$i_D=i_S·\left[exp\left({\displaystyle \frac{e·v_{C_2}}{k_B·T}}\right)-1\right],$$

(2)

where e is the electron charge; T is the temperature; $i_S$ is the saturation current; and $k_B$ is the Boltzmann constant.

In our previous work [38], we obtained the discrete solution to the system (1) using Euler–Cromer numerical integration. The discrete system is expressed by the difference equations in (4).

$$\begin{array}{ccc}x={\displaystyle \frac{v_{C_1}}{V_T}},& y={\displaystyle \frac{\rho ·i_{L_1}}{V_T}},& z={\displaystyle \frac{v_{C_2}}{V_T}},\\ V_T={\displaystyle \frac{k_{B}T}{e}},& \rho =\sqrt{{\displaystyle \frac{L_1}{C_1}}},& \epsilon ={\displaystyle \frac{C_2}{C_1}},\\ a=(k-1){\displaystyle \frac{R_1}{\rho }},& b={\displaystyle \frac{\rho ·i_0}{V_T}},& c={\displaystyle \frac{\rho ·i_S}{V_T}}.\end{array}$$

(3)

$$\left\{\begin{array}{c}{x}_{n+1}=y_n·\Delta \theta +x_n,\hfill \\ y_{n+1}=\left(a·y_n-x_n-z_n\right)·\Delta \theta +y_n,\hfill \\ z_{n+1}={\displaystyle \frac{\Delta \theta }{\epsilon }}·(b+y_n-c·(exp\left(z_n\right)-1))+z_n,\hfill \end{array}\right.$$

(4)

where $a=0.5$; $b=5.769$; $c=9.155·{10}^{-5}$; $\epsilon =0.15$; and $\Delta \theta =2^{-10}$. It is important to note that in (3), c depends on the current $i_S$, meaning that this constant is variable. However, this constant is very small, and the original study [7] explicitly states that the chaotic mode is insensitive to c; thus, taking c as a constant is valid.

2.2. Vilnius Chaos Oscillator FPGA Implementation

This subsection describes the implementation of the Vilnius chaos oscillator difference Equation (4) in a digital design that is intended for an FPGA. Our previous work [38] explored the possibility of analog–discrete and discrete–analog synchronization using (4) implemented in MATLAB. This work implements (4) on an FPGA.

The first step of FPGA implementation is to outline the mathematical operations of (4) from the perspective of the sequential digital design. This is highlighted in (5).

$$\left\{\begin{array}{c}\underset{\mathrm{Next}\mathrm{value}}{\underbrace{x_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{x_n}}+\underset{\mathrm{Derivative}}{\underbrace{y_n}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }},\hfill \\ \underset{\mathrm{Next}\mathrm{value}}{\underbrace{y_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{y_n}}+\underset{\mathrm{Derivative}}{\underbrace{\left(a·y_n-x_n-z_n\right)}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }},\hfill \\ \underset{\mathrm{Next}\mathrm{value}}{\underbrace{z_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{z_n}}+\underset{\mathrm{Derivative}}{\underbrace{\left({\displaystyle \frac{b}{\epsilon }}+{\displaystyle \frac{1}{\epsilon }}·y_n-{\displaystyle \frac{c}{\epsilon }}·(exp\left(z_n\right)-1)\right)}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }}.\hfill \end{array}\right.$$

(5)

The equation clearly shows that each new value of the oscillator’s state variable is obtained by taking the current value and adding the derivative, which is a combination of state variables’ current states multiplied by a time step. This can be easily transferred to a digital circuit. Figure 2 demonstrates the circuit for the state variable x.

The circuit in the figure contains a register that, on the rising edge of the clock signal $clk$, registers the next value of the state variable x, thus acquiring the current state $x_n$ each clock cycle. The increment for the next state $x_{n+1}$ is obtained by passing the $x_n$, $y_n$, and $z_n$ values to the block calculating the derivatives. It processes all three state variables simultaneously, taking the current state-variable values and storing the constants from (5) required for the derivative calculations. For the case of x, this block will output $y_n$ as described in (5). Next, the derivative is multiplied by the time step $\Delta \theta$. The multiplication result is added to the current state-variable value, $x_n$, thus obtaining $x_{n+1}$. The design performs similar operations to calculate updates for state variables y and z. The derivative calculation block is common for x, y, and z, with separate outputs for each state variable.

After establishing the general design for the digital implementation of the oscillator, the next step is designing the derivative calculation block, which is the core of the oscillator. The initial design choice was to utilize a pipeline approach. This means that the derivative calculation is split into simple mathematical operations followed by registers. The process requires the same delay for all results obtained in the pipeline when used for the particular operation. The pipelining process for the derivative calculation (5) is demonstrated in (6).

$$\left\{\begin{array}{c}\mathrm{d}x=\underset{1}{\underbrace{y_n}},\hfill \\ \mathrm{d}y=\underset{2}{\underbrace{{\underbrace{a·y_n}}_1-{\underbrace{x_n-z_n}}_1}},\hfill \\ \mathrm{d}z=\underset{4}{\underbrace{\underset{3}{\underbrace{\underset{2}{\underbrace{\underset{1}{\underbrace{{\displaystyle \frac{1}{\epsilon }}·y_n}}-{\displaystyle \frac{b}{\epsilon }}}}}}+\underset{3}{\underbrace{{\displaystyle \frac{c}{\epsilon }}·\underset{2}{\underbrace{(\underset{1}{\underbrace{exp\left(z_n\right)}}-1)}}}}}}.\hfill \end{array}\right.$$

(6)

For example, calculating $\mathrm{d}y$ would need to perform an $a·y_n$ in the first clock cycle, while $x_n-z_n$ is done in parallel at the same clock cycle. After both results are registered, their sum is performed in the second clock cycle. Notably, the increment calculations of the state variables differ by the number of clock cycles required. However, oscillators must update all state variables simultaneously, which means that extra registers are required to match the delay of the longest pipeline, $\mathrm{d}z$ in this case.

Another point to consider is calculating the nonlinear function $exp\left(z_n\right)$. To obtain the exponent value in one clock cycle, we decided to use read-only memory (ROM) with the pre-calculated $exp\left(z_n\right)$ values for the possible $z_n$ range. This idea was further expanded by implementing the $-{\displaystyle \frac{b}{\epsilon }}+{\displaystyle \frac{c}{\epsilon }}·(exp\left(z_n\right)-1)$ in ROM, as it contains the aforementioned exponents and constants. This simplifies the pipeline, as shown in (7).

$$\left\{\begin{array}{c}\mathrm{d}x=\underset{1}{\underbrace{y_n}},\hfill \\ \mathrm{d}y=\underset{2}{\underbrace{{\underbrace{a·y_n}}_1-{\underbrace{x_n-z_n}}_1}},\hfill \\ \mathrm{d}z=\underset{2}{\underbrace{{\underbrace{{\displaystyle \frac{1}{\epsilon }}·y_n}}_1+{\underbrace{\mathrm{ROM}\left(z_n\right)}}_1}}.\hfill \end{array}\right.$$

(7)

The system was initially implemented in MATLAB to speed up the debugging process. The environment allows for manageable adjustment of the bit widths of the integer and fractional parts of the signals, which are required for fixed-point implementation on an FPGA. The ROM implementation is demonstrated for the MATLAB model; it is identical to the digital design.

The design of the memory is shown in Figure 3. The bit widths of the integer and fractional parts are identical for the three state variables. The MATLAB model showed that $x_n$ requires at least 8 bits for the signed integer bit width. For this reason, the integer bit width was set to 8 bits for $x_n$, $y_n$, and $z_n$. According to MATLAB simulations, 14 bits are required for the fractional part, making the word length 22 bits. Figure 3 demonstrates that for the $z_n$, 6 integer part bits and 6 fractional part bits are used to form the ROM read address. Thus, the ROM is generated with a 12-bit address space, capable of storing 4096 data records, each consisting of 8 integer bits and 14 fractional bits.

Figure 4 demonstrates the contents of the ROM in the case of the Vilnius chaos oscillator. The y-axis is used for the stored memory values of $-{\displaystyle \frac{b}{\epsilon }}+{\displaystyle \frac{c}{\epsilon }}·(exp\left(z_n\right)-1)$ for all possible read address ($z_n$ rounded to 12 bits) values on the x-axis. The input range is from −32 to 31.984375. For $z_n$ inputs greater than 12, the integer part of the in-memory expression exceeds 7 bits, so it is clipped to −128.

After establishing the complete digital design of the oscillator, including the block calculating the derivatives and the ROM storing the nonlinearity in MATLAB, the VHDL (Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)) implementation was performed by translating the expressions.

2.3. RC Chaos Oscillator

The second oscillator is the RC chaos oscillator [8]. The circuit of the oscillator is shown in Figure 5a, while the hardware implementation of the circuit using discrete components on an FR4 PCB is shown in Figure 5b.

System (8) describes the dynamics of this oscillator. The circuit’s state variables are the capacitor’s $C_1,$$C_2$, and $C_3$ voltages. The nonlinearity in this case is modeled using the Heaviside step function H.

$$\left\{\begin{array}{c}{C}_1{\displaystyle \frac{\mathrm{d}{v}_{C_1}}{\mathrm{d}t}}=-{\displaystyle \frac{v_{C_1}}{R_1}}-{\displaystyle \frac{v_{C_1}-v_{C_2}}{R_3}},\hfill \\ C_2{\displaystyle \frac{\mathrm{d}{v}_{C_2}}{\mathrm{d}t}}={\displaystyle \frac{v_{C_1}-v_{C_2}}{R_3}}-{\displaystyle \frac{v_{C_2}-v_{C_3}}{R_5}},\hfill \\ C_3{\displaystyle \frac{\mathrm{d}{v}_{C_3}}{\mathrm{d}t}}={\displaystyle \frac{v_{C_2}-v_{C_3}}{R_5}}-{\displaystyle \frac{v_{C_3}}{R_7}}+{\displaystyle \frac{R_1}{R_8}}(v_{C_3}-1)H(v_{C_3}-1).\hfill \end{array}\right.$$

(8)

The work in [8] presented Equation (9) by introducing the parameters shown in (10).

$$\left\{\begin{array}{c}{\displaystyle \frac{\mathrm{d}x}{\mathrm{d}t}}=-x+\left(k_1-1\right)·y-\left(k_1-1\right)·z\hfill \\ {\displaystyle \frac{\mathrm{d}y}{\mathrm{d}t}}=-x+\left(k_1-2\right)·y-\left(k_1-1\right)·z\hfill \\ {\displaystyle \frac{\mathrm{d}z}{\mathrm{d}t}}=k_1·y+\left(k_1+\alpha \right)·z+\beta ·\left(z-1\right)·H\left(z-1\right)\hfill \end{array}\right.$$

(9)

$$\begin{array}{ccc}x={\displaystyle \frac{v_{C_1}}{v^{*}}},& y={\displaystyle \frac{v_{C_2}}{v^{*}}},& z={\displaystyle \frac{v_{C_3}}{v^{*}}},\\ v^{*}={\displaystyle \frac{v_0}{k_2-1}},& \alpha ={\displaystyle \frac{R_1}{R_6}},& \beta ={\displaystyle \frac{R_1}{R_8}},\\ k_1={\displaystyle \frac{R_3}{R_4}}+1,& k_2={\displaystyle \frac{R_7}{R_8}}+1,& \theta ={\displaystyle \frac{1}{R_1·C_1}}.\end{array}$$

(10)

Similarly, [38] derived the discrete Equation (11) by applying Euler–Cromer numerical integration to (9).

$$\left\{\begin{array}{c}{x}_{n+1}=\left(\left(k_1-1\right)·y_n-\left(k_1-1\right)·z_n-x_n\right)·\Delta \theta +x_n\hfill \\ y_{n+1}=\left(\left(k_1-2\right)·y_n-\left(k_1-1\right)·z_n-x_n\right)·\Delta \theta +y_n\hfill \\ z_{n+1}=\left(k_1·y_n+\left(k_1+\alpha \right)·z_n+\beta ·\left(z_n-1\right)·H\left(z_n-1\right)\right)·\Delta \theta +z_n\hfill \end{array}\right.$$

(11)

The final equation has the following parameters: $k_1=5.5$; $\alpha =10$; $\beta =14.1026$; $\epsilon =0.15$; and $\Delta \theta =2^{-10}$.

2.4. RC Chaos Oscillator FPGA Implementation

Similar to the Vilnius chaos oscillator, the first step in adapting the RC chaos oscillator’s state-variable differential Equation (11) to a digital design is to outline the mathematical operations from the perspective of a sequential digital design.

$$\left\{\begin{array}{c}\underset{\mathrm{Next}\mathrm{value}}{\underbrace{x_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{x_n}}+\underset{\mathrm{Derivative}}{\underbrace{(\left(k_1-1\right)·y_n-\left(k_1-1\right)·z_n-x_n)}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }}\hfill \\ \underset{\mathrm{Next}\mathrm{value}}{\underbrace{y_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{y_n}}+\underset{\mathrm{Derivative}}{\underbrace{\left(\left(k_1-2\right)·y_n-\left(k_1-1\right)·z_n-x_n\right))}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }}\hfill \\ \underset{\mathrm{Next}\mathrm{value}}{\underbrace{z_{n+1}}}=\underset{\mathrm{Current}\mathrm{value}}{\underbrace{z_n}}+\underset{\mathrm{Derivative}}{\underbrace{\left(k_1·y_n+\left(k_1+\alpha \right)·z_n+\beta ·\left(z_n-1\right)·H\left(z_n-1\right)\right)}}·\underset{\mathrm{Time}\mathrm{step}}{\underbrace{\Delta \theta }}\hfill \end{array}\right.$$

(12)

The equation demonstrates that the system in (12) is very similar to (5) in the case of the Vilnius chaos oscillator. The only difference is the operations performed in the “derivative” part of the system. For this reason, it is possible to use the digital design presented in Figure 2, only adjusting the operations performed in the derivative calculation block. The next step is the pipeline implementation of the derivative calculation block. From (12), it can be seen that the nonlinearity (Heaviside function) has $z_n$ as an argument. Following the Vilnius oscillator implementation procedure described above, $\left(k_1+\alpha \right)·z_n+\beta ·\left(z_n-1\right)·H\left(z_n-1\right)$ was replaced with a ROM. The simplified pipeline is shown in (13).

$$\left\{\begin{array}{c}\mathrm{d}x=\underset{3}{\underbrace{{\underbrace{{\underbrace{\left(k_1-1\right)·y_n}}_1-{\underbrace{\left(k_1-1\right)·z_n}}_1}}_2-{\underbrace{{\underbrace{x_n}}_1}}_2}}\hfill \\ \mathrm{d}y=\underset{3}{\underbrace{{\underbrace{{\underbrace{\left(k_1-1\right)·y_n}}_1-{\underbrace{\left(k_1-2\right)·z_n}}_1}}_2-{\underbrace{{\underbrace{x_n}}_1}}_2}}\hfill \\ \mathrm{d}z=\underset{2}{\underbrace{{\underbrace{k_1·y_n}}_1+{\underbrace{\mathrm{ROM}\left(z_n\right)}}_1}}\hfill \end{array}\right.$$

(13)

.

The ROM design is identical to that in Figure 3. The ROM contents for the RC chaos oscillator are shown in Figure 6. In this case, for $z_n<-8$, the in-memory expression values exceed the 8-bit signed integer value range, so the stored values are truncated to $128-2^{-14}$ (maximum signed 8-bit integer and 14-bit fractional parts fixed-point number).

Similarly, after establishing the complete digital design in MATLAB, the expressions were translated to VHDL for FPGA implementation.

2.5. MATLAB Model and VHDL Design Comparison

This subsection discusses the FPGA resource utilization and verifies the correspondence of the VHDL and MATLAB designs. A comparison was made between the two chaos oscillators.

The FPGA implementation was targeted at the Altera (Intel) Cyclone 5CSXFC6D6F31C6 chip on a DE10-Standard board. The utilization of FPGA resources for the VHDL design of the chaos oscillators is presented in

Table 1. FPGA resource utilization of chaos oscillators.

Chaos Oscillator	Adaptive Logic Modules (ALMs)	Digital Signal-Processing (DSP) Blocks	Block Memory Bits
Vilnius	67 (<1%)	1 (1%)	90,122 (2%)
RC	115 (<1%)	5 (6%)	90,122 (2%)

. The FPGA resource utilization results demonstrate that the designed oscillators use only a small fraction of FPGA resources in their current form, meaning that the oscillators can be used in chips with fewer resources or in resource-intensive designs that may additionally utilize chaos oscillators. By comparing the two oscillators, the RC oscillator requires more adaptive logic modules (ALMs) and digital signal-processing (DSP) blocks, although the difference is minimal.

To verify that the VHDL-based design performs identically to the MATLAB (2023) model, a functional simulation was performed using the Questa/Modelsim (2023.3) Intel FPGA simulation tool. The simulation results were exported to MATLAB for verification. Figure 7 and Figure 8 demonstrate that, with identical parameters and initial conditions, the chaos oscillators’ signals of the MATLAB model and VHDL-based design were identical and did not diverge in the ${10}^5$ clock cycles, n, meaning that the MATLAB model precisely described the behavior of the VHDL-based digital design.

3. Experimental Verification of FPGA-Based Analog–Discrete and Discrete–Analog Synchronization

This section is devoted to studying analog–discrete and discrete–analog synchronization using the chaos oscillators implemented on the PCB and FPGA-based chaos oscillators. The two chaos oscillators are asynchronous by default due to differences in initial conditions and mismatches in the parameters. The synchronization technique utilized to achieve analog–discrete and discrete–analog synchronization is known as Pecora–Carroll synchronization. This technique is depicted in Figure 9 for the two cases of chaotic synchronization. The state variables of the FPGA-based chaos oscillator are $x_1$, $y_1$, and $z_1$, while the state variables of the analog oscillator are $x_2$, $y_2$, and $z_2$.

In Figure 9a, the FPGA-based oscillator is a drive system, while the analog oscillator is a response system. Synchronization is achieved by passing the $y_1$ state variable to the response system and replacing $y_2$. By doing this, $x_2$ starts following the behavior of $x_1$, and $z_2$ starts following the behavior of $z_1$. Analog–discrete synchronization is shown in Figure 9b, where the analog oscillator is a drive system and the FPGA-based oscillator is a response system. By passing $y_2$ to the response system and replacing $y_1$, $x_1$ starts following the behavior of $x_2$, and $z_1$ starts following the behavior of $z_2$. The similarity of signals is evaluated by calculating the correlation of the corresponding signals. Our previous work [38] addressed analog–discrete and discrete–analog synchronization via modeling, whereas this work focuses on hardware.

Figure 10 demonstrates the experimental evaluation of discrete–analog synchronization. The FPGA-based chaos oscillator operates on a DE10-Standard board. An ADA-HSMC daughter card is connected via a High-Speed Mezzanine Card (HSMC) connector, providing a two-channel analog-to-digital converter (ADC) and a two-channel digital-to-analog converter (DAC). The first DAC channel outputs a $y_1$ synchronization signal applied to the analog chaos oscillator. The second DAC channel outputs $x_1$ in the first set of measurements and $z_1$ in the second set of measurements. ADP3450 oscilloscope channels are used to record and save $x_1$, $x_2$ and $z_1$, $z_2$. Next, a correlation between the corresponding signals is estimated in MATLAB.

Figure 11 demonstrates the experimental evaluation of analog–discrete synchronization. In this case, the $y_2$ signal is passed to the ADC input and forwarded to the FPGA-based oscillator. FPGA signals $x_1$ and $z_1$ are passed to the DAC. In this case, the ADP3450 oscilloscope channels record $x_1$, $x_2$ and $z_1$, $z_2$ simultaneously. The correlation is also estimated in MATLAB.

Figure 12 and Figure 13 demonstrate the recorded waveforms of the Vilnius and RC chaos oscillators with applied synchronization in the case of discrete–analog synchronization. The figures demonstrate that with the synchronization signal applied to the analog oscillator from the FPGA board, the behavior of the analog oscillator matches that of the FPGA-based oscillator. In the case of the Vilnius chaos oscillator, the $x_1$, $x_2$ and $z_1$, $z_2$ signals match almost perfectly. In the case of the RC chaos oscillator, it is important to note that the analog and FPGA-based oscillators are synchronized since $z_1$ and $z_2$ match, but the $x_1$ and $x_2$ signals do not coincide.

Figure 14 and Figure 15 demonstrate the recorded waveforms of the Vilnius and RC chaos oscillators with applied synchronization for analog–discrete synchronization. The figures demonstrate that, when the synchronization signal is applied to the FPGA-based oscillator from the analog oscillator, the FPGA-based oscillator’s behavior matches that of the analog oscillator. The $x_1$, $x_2$ and $z_1$, $z_2$ signals match between the two oscillators, demonstrating successful synchronization.

Table 2. Synchronization evaluation using correlation coefficient.

	Discrete–Analog		Analog–Discrete
Chaos Oscillator	${\mathbf{x}}_{\mathbf{1}}$ and ${\mathbf{x}}_{\mathbf{2}}$	${\mathbf{z}}_{\mathbf{1}}$ and ${\mathbf{z}}_{\mathbf{2}}$	${\mathbf{x}}_{\mathbf{1}}$ and ${\mathbf{x}}_{\mathbf{2}}$	${\mathbf{z}}_{\mathbf{1}}$ and ${\mathbf{z}}_{\mathbf{2}}$
Vilnius	0.97	0.98	0.93	0.92
RC	0.72	0.97	0.89	0.90

presents the correlation coefficients calculated for every Vilnius and RC chaos oscillator’s state variable in the discrete–analog and analog–discrete synchronization cases. The correlation coefficient equaled 1 for identical signals, while 0 indicates that the signals were completely uncorrelated. The table shows that, in most cases, the correlation coefficient was over 0.9 and very close to 1, thus confirming that analog–discrete and discrete–analog synchronization were achieved between the analog and FPGA-based chaos oscillators. The fact that the signals did not coincide perfectly can be attributed to mismatched parameters in the analog and FPGA-based oscillators. Another contributing factor was noise.

4. Conclusions

This work focused on the FPGA implementation of analog chaos oscillators for analog–discrete and discrete–analog chaotic synchronization applications. The key achievement of this work is the experimentally verified analog–discrete and discrete–analog synchronization between the FPGA-based and analog chaos oscillators. This work developed an approach for the parallel implementation of such chaos oscillators on an FPGA, allowing the application of the technique to other chaos oscillators and integrating the oscillators into FPGA-based designs. Additionally, the developed FPGA implementation approach demonstrated acceleration by using ROM for nonlinearity approximation. This achievement also enables the use of the FPGA to modify the parameters of the chaos oscillators, increasing the oscillation frequency and changing the signal bandwidths. The developed precise MATLAB model of the digital design allows for studying the performance of the FPGA-based oscillators without the need for hardware, as well as testing and debugging design ideas for the FPGA-based oscillators.

Regarding analog–discrete and discrete–analog synchronization, the synchronization pattern for the RC chaos oscillator was observed previously, where the shape of the x state variables did not perfectly match in the case of discrete–analog synchronization; however, the correlation in this case was sufficiently high. The achieved analog–discrete and discrete–analog synchronization of the analog and FPGA-based oscillators introduces new possibilities for chaos-based data transmission, as the systems can now utilize both types of oscillators, creating a hybrid analog–discrete chaos-based transmission system.