Search Results (647)

This paper proposes a two-phase high-step-down converter with zero-voltage switching (ZVS) and automatic current sharing, which is suitable for power conversion systems requiring a high step-down voltage conversion ratio. The proposed structure consists of three power switches, two energy-transferring capacitors, two freewheeling diodes, and one differential-mode transformer. This structure is compared with the conventional two-phase series-capacitor buck converter, which requires two independent inductors at the output side and thereby limits the power density. Therefore, in this paper, the dual-inductor structure with a differential-mode transformer is presented. The turns ratio of the differential-mode transformer is designed as one, enabling the two phases to achieve good symmetry. This design not only effectively improves the overall power density, but also realizes current sharing between the two-phase output currents by means of the differential-mode transformer. In addition, due to the leakage inductance continuity of the differential-mode transformer and the discharge path of the energy-transferring capacitors, the power switches can achieve zero-voltage switching during switching transitions, thereby significantly reducing switching losses. On the other hand, the voltage-dividing characteristic of the series capacitors can effectively reduce the voltage stress on the power switches. According to the above features, the proposed converter not only significantly improves the overall conversion efficiency, but also enhances the operational stability and reliability of the system. In this study, the operating principle of the proposed circuit is first analyzed, with some experimental results to verify effectiveness. Full article

In this paper, a new topology of a step-up DC converter is presented for renewable energy applications, yielding a high step-up conversion ratio and reduced voltage stress across the switches. The proposed converter uses a hybrid switched-inductor and switched-capacitor cell to achieve the high voltage gain. Additionally, the capacitors in the switched cell also perform the function of clamping the voltage across switches. The proposed converter utilizes only a single controlled switch and operates in only two modes of conduction. The steady-state analysis and operating principle of the proposed hybrid step-up converter are discussed in detail and various mathematical equations have been derived. The analysis shows numerous improvements over the traditional DC-DC converters. Simulation was carried out in MATLAB Simulink 2021b on a 55% duty cycle and simulation results are compared with theoretical analysis. From simulation results, it is clear the proposed converter exhibits better performance compared to conventional boost and other traditional step-up converters with the same design parameters. Finally, a 31.5-watt hardware prototype was constructed and tested in the laboratory to experimentally validate the theoretical and simulation results. Full article

This paper proposes a CLDD lossless snubber for application in SEPIC converters. Unlike conventional designs, this snubber employs no active components, utilizing instead two diodes, a snubber inductor, and a snubber capacitor to reduce switching losses and enhance efficiency. The paper thoroughly explains its operating principle, derives detailed mathematical expressions related to the components for better understanding its mechanism, and calculates the voltage and current stresses on the switching components. During the design of this lossless snubber, particular attention is paid to component selection to ensure stable converter operation. This lossless snubber effectively enhances the conversion efficiency of the circuit topology. Finally, a 60 W prototype DC-DC SEPIC converter with 30 V output was designed and tested to evaluate the proposed circuit. Experimental validation demonstrates that the proposed topology boosts peak efficiency from 85.63% to 93.72% (8.10% improvement) across the entire load range, confirming its structural simplicity and effectiveness. Full article

This paper is devoted to the design and implementation of a high-performance onboard Supercapacitor energy storage system (ESS) with a SiC power MOSFET-based buck–boost converter for railway applications. The SiC power MOSFET-based buck–boost converter can be switched at higher frequencies than those of Si-IGBT and Hybrid-IGBT counterparts, resulting in significant volume and cost reduction in the buck–boost inductor. A new operating strategy is proposed for a Supercapacitor ESS to optimize the electrical energy savings of a light rail transportation system (LRTS) while running on a prespecified rail track. In the Optimized Operating Strategy, regenerative braking torque and power profiles are pre-programmed before departing from each station to allow the storage of almost all of the kinetic energy of the vehicle in a Supercapacitor ESS. Details of the proposed Optimized Operating Strategy are described in a comparative manner with the Standard Operating Strategy in the paper. Furthermore, effects of the type of interface circuit between the DC catenary line and the AC grid are also discussed in view of the net energy consumption of the LRTS from the AC grid while operating on a typical rail track. All theoretical results are verified by experimental work conducted on a physical simulator. The results obtained show that an onboard Supercapacitor ESS with an Optimized Operating Strategy provides 36% energy savings with respect to the base case with no ESS of a railway vehicle moving on a prespecified track and supplied from a unidirectional interface circuit between the DC catenary and AC grid. This paper is accompanied by a video demonstrating the experimental work. Full article

This paper introduces a non-isolated high step-up DC–DC converter suitable for distributed generation system applications. The proposed topology uses the zero-voltage-transition (ZVT) technique to achieve soft-switching conditions over a wide range of output power levels, resulting in improved efficiency and reliability. Since the main switch turns on under ZVS conditions, the capacitive turn-on loss is eliminated, thereby reducing switching losses. In addition to the soft-switching capability, the converter provides a continuous input current, which reduces the input filter requirement and improves both power density and cost-effectiveness. Moreover, the converter design effectively increases the voltage gain by utilizing coupled-inductor, switched-capacitor, and voltage-multiplier techniques, allowing the proposed converter to be used in high-voltage applications. The proposed converter employs an independent input inductor and a four-winding coupled inductor implemented using two magnetic cores. Furthermore, the proposed converter features lower voltage stress across the switches, enabling the use of cost-effective, low-resistance MOSFETs, which further improve efficiency. Finally, a common ground structure, the absence of floating switches, and the elimination of the reverse-recovery problem in all diodes are additional valuable advantages of the proposed converter. Comprehensive analytical investigations, together with experimental evaluations conducted at a power level of 200 W, demonstrate that the proposed converter achieves enhanced performance characteristics and outperforms previously reported converter topologies. Full article

Aiming at the unstable power output of single-source piezoelectric energy harvesters for ecological monitoring in bird nature reserves, this work develops a novel combined wind–rain piezoelectric energy harvester and establishes a complete numerical modeling framework. The proposed device integrates a snowflake-shaped bluff body for broadband vortex-induced wind energy capture and a self-tilting water container for raindrop gravitational potential energy collection, with both excitation sources equipped with independent piezoelectric cantilevers that share a unified passive parallel-synchronized switch harvesting on inductor (P-SSHI) interface circuit for coordinated energy conversion of two ambient energy sources. A full set of closed-loop theoretical formulas covering rain potential energy, vortex-induced aerodynamic excitation, electromechanical coupling, and LC-resonance-based voltage inversion is derived. Static finite element analysis, Multisim circuit simulation, and oscilloscope-based bench-scale experiments are implemented to evaluate structural deformation, stress distribution, output voltage, impedance-matched power, and steady-state load performance. Simulation and experimental results validate the rationality of the structural scheme and mathematical model. All validations are performed under laboratory-simulated conditions, and long-term field meteorological tests are reserved for future investigations. The compact low-noise proof-of-concept prototype shows application potential for field monitoring nodes, and the established modeling framework provides design references for multi-source kinetic-energy harvesters. Full article

The new inductor-capacitor-trap (LCT) filter can further suppress high-frequency current harmonics around the switching frequency, so it is important for the permanent magnet synchronous motor (PMSM); however, resonance problems caused by the LCT filter will affect system stability. Active damping is essential to suppress the system resonance. However, with the traditional damping schemes, such as capacitor current feedback (CCF) control, the damping effect and the dynamic response of the LCT-filtered PMSM are difficult to improve simultaneously. In this article, based on the inverter current and motor voltage, a novel two-variable feedback active damping method for the LCT-filtered (TVF-LCT) PMSM is proposed to enhance the damping effect with fast dynamic performance. The TVF-LCT damping parameters are designed; moreover, the stability, damping effect and dynamic performance of the proposed TVF-LCT damping current loop are analyzed. With the undamped LCT, traditional CCF-LCT, and the proposed TVF-LCT damping schemes, the comparative experimental results verify the effectiveness of the proposed TVF-LCT damping scheme. Full article

In this communication, a balanced Colpitts VCO with low phase noise and a wide tuning range is presented, which was implemented using a 2 μm GaAs BiHEMT process. To improve phase noise, a noise-shifting technique introduced by the cross-coupled pair was applied. A deep-learning-assisted genetic algorithm was employed to optimize the quality factor of an on-chip inductor, further improving the phase noise. Additionally, three-bit switches were utilized to expand the tuning range of this VCO. Finally, a VCO prototype was implemented and fabricated for verification. The measurement results demonstrate that the proposed VCO can achieve a wide tuning range of 33% (2.56–3.57 GHz) and an excellent phase noise of −136.25 dBc/Hz at a 1 MHz offset, validating the efficiency of the adopted circuit techniques and the machine learning-assisted optimization strategy for low-phase-noise design. Consequently, this VCO proves to be a highly competitive candidate for signal sources in S-band satellite communication systems. Full article

Resonant DC–DC converter design requires family selection, feasible operating regions and component targets to be evaluated consistently. ResoSym-RD links topology-aware normalized screening to physical-unit synthesis based on the fundamental-harmonic approximation (FHA), rounded component targets and independently tested timing schedules. Series resonant (SRC), parallel-loaded resonant (PLRC), inductor–capacitor–capacitor (LCC) and inductor–inductor–capacitor (LLC) families retain their native reduced models. Nested search domains expose boundary-dependent coverage and trade-offs rather than a universal topology ranking. For a 360–420 V/48 V, 1 kW LLC case, the retained 20 µH/88 nF/106 µH targets have a minimum nominal normalized margin of 1.441. A prespecified rounded FHA comparator has a lower nominal margin and a higher ranking proxy, but a higher fixed-timing sampled pass fraction. With matched timing perturbations, an independent 20,000-realization test gives 99.925% charge-only feasibility for the locked schedule versus 98.860% for fixed 250 ns timing. A new common parasitic switched-circuit assessment compares both tanks over all nine corners. At equal 48 V output, the ResoSym-RD tank has 1.42% lower uniformly averaged modeled dissipation, but not at every corner. The uncorrected FHA schedule produces output errors up to 5.61%, and the ResoSym-RD peak-current error reaches 21.06%, establishing the need for time-domain closure. Executed commutation traces, step refinement and a separate numerical integrator support the declared generic circuit results. The study is an auditable pre-synthesis methodology, not a claim of measured efficiency, field reliability, electromagnetic interference (EMI) compliance or hardware qualification. Full article

The phase-shifted full-bridge high-frequency-link (PSFB-HFL) inverter adopts a DC to sinusoidal-half-wave to sinusoidal-wave conversion structure, which uses few passive components with small parameter values, and the switching frequency of the subsequent stage is low, resulting in low losses. This makes it well suited for airborne applications requiring large currents on the low-voltage side and a high step-up ratio, and it has the potential to realize combined three-phase output. To meet the dynamic-performance requirements of this structure, this paper adopts a peak current control strategy. However, this control method suffers from a sub-harmonic oscillation problem, for which a corresponding slope compensation scheme is designed. Furthermore, based on the small-signal model of the Buck converter, an accurate small-signal model of the PSFB peak current inner loop, based on the average value of the filter inductor current, is derived. Accordingly, a voltage-outer-loop PI controller is designed to implement closed-loop control and improve the dynamic performance of the system. An experimental prototype of a PSFB-HFL inverter with a 28 V DC input and a rated power of 4 kW was built. Experimental results show that the proposed control strategy ensures robust large-signal stability, maintaining high-quality sinusoidal waveforms under varying load conditions, thus verifying the effectiveness and engineering feasibility of the PSFB-HFL inverter. Full article

Input current ripple reduction in DC-DC boost converters is a persistent challenge because input current ripples are driving up filter requirements, electromagnetic interference (EMI), and stress on sources and loads. This ultimately limits power density and efficiency in many applications, from photovoltaic systems to fuel cells and electric vehicle powertrains. While classical interleaving and passive filtering approaches have been proposed, recent years have brought promising advances in magnetic coupling, higher switching frequency, novel interleaved topologies, and control-based reduction strategies. The current state of the art offers a solid foundation, and further investigations could help enable a more comprehensive comparison and better guide the selection of the most appropriate approach according to performance objectives. An increasing number of recent publications are focusing on the topic of current ripple reduction. Indeed, a recent analysis of international scientific databases shows a steady increase in publications addressing current ripple in DC-DC converters, reflecting both the intensifying demands of modern power electronics applications and the recognition that traditional solutions may not be the most suitable for next-generation converters and systems. This review fills that gap in the case of DC-DC boost converters, where the literature remains fragmented, and a unified comparison of these approaches is still lacking. It compiles, analyses, and compares all current techniques for reducing input current ripple, covering passive filter and inductor sizing methods, component-level improvements such as coupled inductors and wide-bandgap devices, interleaving-based converter architectures, closed-loop control strategies, and hybrid approaches that combine multiple techniques based on papers published over the last decade (2016–2026). More particularly, the dependence of LC filter sizing on the duty cycle and switching frequency is examined, mutual inductance design for ripple cancellation is explored, and the operation of destructive interference in parallel-phase and multilevel converter configurations is compared. The techniques reviewed in this paper highlight remarkable results: A 60–90% ripple reduction by using magnetic coupling at 50% duty cycle, near-zero input current ripple with multiphase interleaving in N-phase converters with optimal phase shift, and dynamic ripple suppression across wide operating ranges through advanced control. The review concludes with a qualitative comparison of the main input current ripple reduction technique families in terms of advantages, limitations, application domains, and reduction potential, and discusses opportunities for hybrid passive–active strategies in next-generation high-efficiency boost converters. Full article

Conventional quadratic boost DC–DC converters can achieve high voltage gain; however, the main switch is subjected to voltage stress approaching the output voltage. Some improved topologies also suffer from limitations such as the absence of a common ground, discontinuous input current, or increased control complexity arising from multiple switches. To address these limitations, this paper proposes a single-switch quadratic high step-up DC–DC converter that integrates a coupled inductor with expandable coupled-inductor switched-capacitor (CLSC) cells. By adjusting the turns ratio of the coupled inductor and the number of CLSC stages, the proposed converter achieves high voltage gain at a relatively low duty cycle while providing a common-ground configuration, continuous low-ripple input current, and reduced voltage stress on the main switch. An integrated passive clamp circuit recycles leakage-inductance energy and suppresses voltage spikes across the main switch, while several diodes operate under zero-current switching (ZCS). The operating modes, steady-state characteristics, component stresses, and design guidelines are comprehensively analyzed. A 200 W prototype operating at 50 kHz with an input voltage of 20 V and an output voltage of 320 V was developed for verification. At an output power of 120 W, the measured voltage stress on the main switch was 125 V, substantially lower than the 320 V output voltage. Over an output power range of 30–200 W, the prototype achieved a peak efficiency of 94.96% at 50 W, while the deviations between the simulated and experimental voltage values remained within ±1%. These results verify the feasibility and high step-up performance of the proposed converter and demonstrate its potential for renewable-energy and high-voltage conversion systems. Full article

Inductor–inductor–capacitor (LLC) resonant converters can produce nearly symmetric waveforms without achieving low-loss switching. This paper separates these properties, using a common framework for a resonant circuit containing two inductive elements and one capacitor. An analytical gain model is combined with a time-domain model that distinguishes positive secondary conduction, an open secondary circuit, and negative secondary conduction. The framework compares the two switching half-cycles, their conduction sequences, the gain at reciprocal normalized frequencies, and the current available for zero-voltage switching (ZVS). Finite magnetizing inductance breaks reciprocal gain symmetry, while a balanced converter can retain close half-cycle correspondence. Controlled bridge, timing, and rectifier asymmetries increase the waveform mismatch. Independent LTspice checks reproduce three representative mode families and agree with the low-order gain within 0.45–3.55%. They also confirm that a high-gain operating point can fail ZVS despite good waveform symmetry. Highlighted current paths, a datasheet-informed semiconductor-loss budget, and input/output ripple spectra connect the descriptors to practical design questions. The loss estimates are conditional analytical scenarios, and the filtering study uses a separate coupled reduced-order model. The framework supports reproducible design screening; it does not replace detailed device simulation or hardware validation. Full article

To address receiver-side weight constraints, resonance detuning, and output-current variations caused by coil misalignment in unmanned aerial vehicle (UAV) wireless charging, this paper proposes an inductive power transfer system employing an inductor-series/none (L-S/N) compensation topology and primary-side-sensing-based constant-current control. The topology eliminates the secondary compensation network, while its tuning conditions and constant-current characteristics are derived using a T-network immittance-inverter model. The mutual inductance is identified from two primary-current magnitude measurements without secondary-side sensing or wireless communication. A switched capacitor controlled by pulse-width modulation (PWM) is then used to restore resonance, and inverter phase-shift control compensates for the output-gain variation caused by changes in mutual inductance. In addition, a three-layer stacked magnetic coupler is designed to improve mutual-inductance stability under horizontal misalignment. Experimental results demonstrate stable operation at different misalignment positions, achieving a DC-to-DC efficiency of 84.3% at an output power of approximately 98 W. Full article

Inverse-coupled inductors suppress phase-current ripple in interleaved buck converters, whereas high-side zero-voltage switching (ZVS) requires sufficient negative valley current for switch-node commutation. These opposing requirements create an inherent tradeoff between ripple suppression and ZVS capability. This paper develops a ripple–ZVS operating-boundary framework for a two-phase interleaved GaN buck converter using a PCB air-core inverse-coupled inductor. Ripple and ZVS boundaries are derived for the low- and high-duty regions, with loss sensitivities analyzed in terms of the phase-current trajectory and switching frequency. At 10 MHz, measurements on a 12 V-input prototype show ripple reductions of 4.2% at 3.3 V and 18.5% at 5 V, with corresponding efficiency changes of $+3.9$ and $-1.4$ percentage points. The ZVS boundary frequency is approximately 3 MHz for both configurations at 3.3 V, but decreases from 2.8 to 1.5 MHz with inverse coupling at 5 V. Load sweeps show that frequency-reduced ZVS is more efficient at light load, whereas 10 MHz fixed-frequency operation is more efficient at high load. Thus, neither ripple suppression nor ZVS alone determines which operating strategy is more efficient; their operating boundaries and loss tradeoffs must be considered jointly. Full article