Search Results (448)

The dual-active-bridge series resonant converter (DBSRC) is attractive for bidirectional DC conversion, but its output voltage may respond slowly and exhibit overshoot during start-up, load-step, and reference-step transients when conventional controllers are designed mainly from steady-state or small-signal models. This paper addresses the problem of improving the large-signal transient regulation of a DBSRC while avoiding undesired charging and discharging of the switching capacitor and output capacitor. A finite-state-machine-based state-trajectory control method is proposed. Thus, the converter consists of two full-bridge circuits, each with four switches. The proposed technique enhances the dynamic response of output voltage regulation. By examining the system dynamics in two state-plane domains, the switching behavior of the converter can be clearly characterized, enabling an accurate geometric representation of its operating mechanism. Consequently, a finite-state machine controller is designed based on state-trajectory planning. Switching conditions are utilized to achieve fast start-up and step-load transient responses. Finally, experiments are conducted to validate the effectiveness of the proposed control method. Full article

This paper presents a passive residue-coupled discrete-time delta–sigma ($\Delta \Sigma$) modulator for low-power narrowband sensing applications. Instead of adding a fourth active integrator, the proposed architecture keeps a third-order switched-capacitor main loop and reuses the intrinsic top-plate residue of an 8-bit asynchronous successive-approximation-register (SAR) quantizer. The retained capacitive digital-to-analog converter (CDAC) residue is passively reinjected through a charge-redistribution path, introducing an additional high-pass error-propagation factor in the effective noise transfer function (NTF). Under a bounded effective coupling coefficient, the proposed loop approaches fourth-order-like in-band noise suppression while retaining third-order active-loop complexity. Behavioral simulations show that the Enhanced mode improves the peak signal-to-noise-and-distortion ratio (SNDR) by 16.9 dB over the Baseline third-order mode at an oversampling ratio (OSR) of 128. Circuit-level corner verification of the standalone SAR confirms correct bit cycling and a settled residue-retention window under typical–typical (TT), slow–slow (SS), and fast–fast (FF) conditions: with the slowest conversion window of about 21.4 ns at the SS corner and a sampling period of 39.06 ns at $f_s=25.6$ MHz, roughly 17.66 ns of timing margin remains for residue holding, passive reinjection, and clock non-overlap. The proposed method provides an architecture-level route for improving in-band noise shaping without increasing the number of active integrator stages, and is particularly attractive for low-power, narrowband, and sensor-oriented analog-to-digital converter (ADC) applications. Full article

The rapid growth of electromobility and the increasing deployment of EV chargers emphasize the importance of pulse rectifiers with built-in power factor correction (PFC) filters. The new switching power devices offer higher converter switching frequencies, which enable a decrease in nominal values of passive components, such as inductors and capacitors, and their physical dimensions. Devices like CoolMOS and GaN enable operation with low switching power, but are usually constructed for lower drain-source voltage. From this point of view, the Vienna Rectifier is a prospective type of pulse rectifier with built-in PFC because of its reduced blocking-voltage requirements for the power transistors. Nevertheless, faster switching semiconductor devices with lower switching gate charge require more precise driving circuit tuning and setup. There are many scientific papers focused on the driving setup and techniques of the power transistors applied in H-bridge topologies. The purpose of this paper is to investigate the commutation loop and the related switching phenomena of the Vienna Rectifier topology. This paper evaluates the driver setup for a CoolMOS-based Vienna Rectifier with anti-serial connection of transistors forming a bidirectional switch. The switching transients are analyzed and simulated. Subsequently, the real driver settings are evaluated on the real prototype. Full article

This paper proposes a new single-stage bipolar Boost DC/DC converter topology, hereafter referred to as the Full-bridge Boost converter. The proposed architecture enables the generation of a bipolar output voltage with a magnitude equal to or greater than the input voltage, reducing the passive component count. Specifically, a single inductor and a single capacitor are employed, in conjunction with a full-bridge structure and auxiliary switches, to achieve both voltage boosting and polarity inversion within a unified conversion stage. A comprehensive switching configuration is presented, and a mathematical model based on the system switching dynamics is derived. Furthermore, the steady-state behavior is analyzed, yielding an explicit expression for the voltage gain as a function of the control input. In addition, ripple analysis and continuous conduction mode (CCM) boundary conditions are derived to establish design constraints for the converter operation. The characteristic waveforms under both CCM and discontinuous conduction mode (DCM) operation are also analyzed. The validity of the proposed topology and its mathematical representation is verified through MATLAB/Simulink simulations. The detailed switching-level converter is implemented using the Simscape Electrical environment, and the numerical results of the averaged model are compared against the circuit-level simulation through waveform analysis and root mean square error (RMSE) indices to assess modeling accuracy. Finally, implementation feasibility considerations, including semiconductor stress, dead-time requirements, conduction and switching losses, and efficiency analysis, are discussed. Full article

The central adjustment coil of a gasdynamic Electron Cyclotron Resonance (ECR) ion source requires wide-range bipolar current regulation over ±100 A with flat-top stability within 0.1% (1000 ppm) and a current rise time below 4 ms. Conventional fully controlled H-bridge converters operating under hard-switching conditions are unable to satisfy these requirements simultaneously, as the switching loss penalty restricts the control bandwidth and degrades flat-top stability. This paper presents an Asymmetrical Half-Bridge Flyback (AHB-Flyback) converter specifically designed for this application. By incorporating a dedicated resonant branch $L_r$–$C_r$ on the primary side, the converter achieves primary-side Zero-Voltage Switching (ZVS) and secondary-side Zero-Current Switching (ZCS) over the full operating range, enabling 100 kHz operation without incurring the switching losses that would otherwise limit control bandwidth. A decoupled energy management architecture is adopted in which the primary circuit pre-charges an energy storage capacitor during idle intervals, and the coil current is subsequently established through an autonomous capacitor-to-coil discharge, effectively decoupling the peak power demand from the upstream supply network. The operating modes of the flat-top maintenance stage are analyzed through time-domain state equations, yielding an explicit closed-form expression for the Mode 3 duty cycle $D_{T3}$. This expression demonstrates that $D_{T3}$ is determined solely by the switching frequency and circuit parameters, independent of the load current setpoint, which is the fundamental mechanism enabling stable wide-range current regulation without parameter re-tuning. Parameter selection guidelines are derived from this result. Simulation results across the 20–100 A operating range and experimental validation on a scaled prototype confirm flat-top current stability within 1000 ppm and a current rise time of 4 ms, demonstrating the suitability of the proposed converter for precision ECR ion source power supply applications. Full article

This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm², the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms. Full article

Wind energy harvesting based on triboelectric nanogenerators (TENGs) is a promising solution for powering distributed Internet of Things (IoT) nodes, yet its practical efficiency and stability are often hindered by the fluctuating and unpredictable nature of wind. Here, we propose a self-regulating TENG (SR-TENG) that leverages the synergistic effects of centrifugal, elastic, and frictional forces to automatically switch between non-contact and contact modes based on wind speed. This configuration achieves an ultra-low start-up wind speed of 0.86 m/s, ensures sustainable high-performance output across a broad wind speed range, and exhibits excellent durability with no observable performance degradation during 23,000 s of continuous operation at 375 rpm. Systematic structural optimization enables the SR-TENG to reach a peak open-circuit voltage of 140 V, a short-circuit current of 12.5 μA, and a transferred charge of 300 nC at 375 rpm. When integrated with a customized power management circuit, the system delivers a 30.39-fold increase in effective output power at a 1 MΩ load and a 4-fold faster charging rate for a 10 μF capacitor. For practical validation, the harvested ambient wind energy successfully powers a wireless temperature-humidity sensor for real-time cloud data transmission. These results highlight that the SR-TENG holds great potential for advanced wind energy harvesting and self-powered sensing applications in distributed IoT systems. Full article

In offshore wind farms, modular multilevel converters (MMCs) may operate under a deloading condition to accommodate wind-speed volatility and dispatch constraints. Here, deloading is defined as transmitted power < 0.2 pu (scenario S2, low-power non-reversal). Under this condition, submodule capacitor-voltage fault signatures are weak and exhibit strong operating-point-dependent drift, which degrades conventional threshold-based or offline-trained methods. We propose a lightweight switch-level IGBT open-circuit fault localization framework for deloaded MMCs. Wavelet packet decomposition is used to extract time–frequency energy features, and principal component analysis reduces feature dimensionality for lightweight deployment. An enhanced XGBoost model further integrates severity-index weighting to alleviate class imbalance and incremental learning to adapt to condition drift induced by wind-power fluctuations. MATLAB2024b/Simulink results show 99.6% accuracy in S2 with less than 2 ms inference latency, and robust performance in extended scenarios including partial-power operation and power reversal. Full article

This paper reviews circuit topologies in the literature that aim to suppress submodule (SM) capacitor-voltage ripple of modular multilevel converters (MMCs), since this low-frequency ripple largely determines the required SM capacitance and thus the overall converter volume, cost, and reliability. The circuit topologies covered in this review include high-frequency (HF) magnetic or switched power channels, transformerless active channel or bridging cells with mid-cell connections, hybrid-MMC and DC-bus management options, SM-level active power decoupling (APD) and active power filters (APF), and structural modifications. Physical power-channel topologies (HF magnetic or switched auxiliary paths) suppress the $2\omega$ capacitor-voltage ripple by transferring the associated low-frequency ripple power to an auxiliary high-frequency path. Hybrid-MMC and direct-current (DC) bus management reduce the required capacitance with only a modest increase in hardware requirements. SM-level APD and APF cells transfer the ripple power into auxiliary storage. Structural and topological arrangements modify the converter architecture itself, leading to architectural simplification, passive attenuation, and a reduced need for measurement or balancing. The reviewed topologies are then compared in terms of ripple reduction, hardware complexity, additional components, cost, and control complexity, and the resulting evidence is synthesised into application-driven design trade-offs and selection guidelines. In addition, DC–DC MMC topologies are discussed separately in a contextual overview. Full article

Frequency-selective attenuation is widely needed in integrated analog front-ends, yet conventional on-chip RC low-pass filters occupy unfeasibly large silicon areas for low-frequency cutoffs and inherently introduce cumulative phase lag. Motivated by the nonlinear, frequency-dependent state evolution of memristive devices, this work experimentally demonstrates a highly compact, capacitor-free memristor–resistor network that functions as a variable-cutoff, zero-phase-lag resistive attenuator. An Au/HfO₂/Au memristor (15 µm × 15 µm) is connected in series with a load resistor and characterized over a wide frequency range. By leveraging the finite time constant of internal ionic drift, the attenuation bandwidth is strictly programmable via the device’s initial resistance. Cutoff frequencies of approximately 10 Hz, 1 kHz, and 10 kHz are achieved for initial resistances of 400 k$\Omega \pm$30 k$\Omega$, 300 k$\Omega \pm$30 k$\Omega$, and 200 k$\Omega \pm$30 k$\Omega$, respectively. Remarkably, the nonlinear state-switching mechanism enables a steep post-cutoff attenuation rate approaching −60 dB/dec—equivalent to a cascaded third-order RC network—using only a single nanoscale device. Rather than functioning as a strictly linear time-invariant (LTI) filter, the proposed circuit operates as a state-adaptive edge-processor. Its inherent amplitude-dependent dynamics and total absence of reactive poles make it exceptionally suited for highly specialized, area-constrained applications, including zero-phase closed-loop noise suppression, frequency-to-amplitude conversion, and amplitude-aware event-driven sensory preprocessing. Full article

Pulse thyristors are extensively utilized in pulsed plasma discharge applications. In this study, a pulse switch prototype is built using two parallel valve groups, each consisting of seven series-connected thyristors. Each thyristor is equipped with an anti-parallel protection diode, a static voltage-sharing resistor, and an RCD (resistor-capacitor-diode) dynamic voltage-sharing circuit. The prototype withstands 24 kV, delivers 150 kA peak current, operates at 10 Hz, and can run continuously for 1 s. Thermal analysis is essential under narrow-pulse high-current conditions to avoid failure from localized overheating. By investigating the expansion process of the conduction zone during thyristor turn-on, a single-thyristor turn-on model and a finite-element model of the multi-layer series thyristor module are established to analyze transient temperature distributions. Results show a non-uniform temperature profile across the silicon wafer, with the hottest zone near the gate ring. During repetitive pulses, the silicon temperature fluctuates rapidly, while the copper base heats up gradually. At a spreading speed of 30 m/s, the gate terminal temperature rises about 38 °C—within safe limits for now, but projected to exceed them under future operating conditions. Thus, improved thermal management will be critical in further development. Full article

This paper presents an improved switching strategy developed for the Modified Non-Inverting Step-Down/Up (MNI-SDU) DC–DC converter. Unlike previously studied switching strategies, the proposed approach changes the firing sequence and then the equivalent circuits without increasing the switching frequency. This switching technique alters the equations used to select the converter’s capacitors, enabling a different voltage ripple in the capacitors while maintaining the same capacitance as in the previous operation. The proposed switching technique is introduced with a theoretical explanation, and the feasibility of the proposed method is verified through experimental results on a 570 W prototype. The results indicate that the new operation reduces capacitor capacitance and achieves over 58% voltage ripple reduction for both capacitors, while preserving desired operation, specified capacitances, and voltage regulation. The proposed strategy provides a compact and effective solution for high-performance power converters in battery-regulated and renewable-energy systems. Full article

For next-generation biomedical and biochemical sensor nodes, the analog front-end demands a direct interface with current-output sensors, extreme miniaturization, and nanowatt power consumption to enable energy autonomy. This work directly addresses these needs by presenting a comparative analysis of four minimalist, first-order, current-mode $\Delta \Sigma$ modulator ($\Delta \Sigma$M) architectures. Optimized for ultra-low-voltage operation (supply $\le 0.5$ V), the investigated topologies—including resistive, switched-capacitor, and current-reference-based cores—exploit passive integration and charge-domain feedback, eliminating the need for power-hungry active blocks. Detailed circuit-level simulations confirm that, with ad hoc techniques, it is possible to achieve stable first-order noise shaping in the deep near-threshold region, delivering up to 10-bit resolution while consuming less than 10 nW at a 0.5 V supply voltage achieving a signal bandwidth in the sub-10 hertz range. This study validates that robust $\Delta \Sigma$ conversion is feasible under extreme area and power constraints by leveraging architectural simplicity. The clear performance–complexity trade-offs outlined make these current-mode architectures ideal candidates for monolithic integration within miniaturized, energy-autonomous sensing systems. Full article

The pulsed power switch serves as a critical component in pulsed power systems. The electric radiation generated by switching operations threatens the miniaturization of pulsed power systems, causing significant electromagnetic interference (EMI) to nearby signal circuits. The pseudospark switch’s (PSS) exceptionally fast transient response, a key enabler for sophisticated pulsed power systems, is also a major source of severe EMI. This study investigated the electric field radiation from a high voltage PSS within a capacitor discharge unit (CDU), using a near-field scanning system based on an electro-optic probe. The time-frequency distribution of the radiation was characterized, identifying contributions from three sequential stages: the application of the trigger voltage, the main gap breakdown, and the subsequent oscillating high voltage. During the high-frequency oscillation stage, the distribution of the peak electric field radiation aligns with the predictions of the dipole model, with a maximum value of 43.99 kV/m measured near the PSS. The spectral composition extended to 60 MHz, featuring a primary component at 1.24 MHz and distinct harmonics at 20.14 MHz and 32.33 MHz. Additionally, the impacts of circuit parameters and trigger current on the radiated fields were discussed. These results provided essential guidance for the electromagnetic compatibility (EMC) design of highly-integrated pulsed power systems, facilitating more reliable PSS applications. Full article

This study presents a versatile single-phase multilevel inverter designed to accommodate varying input voltages and output levels. Unlike conventional fixed topologies, the proposed design utilizes a unified structure of 13 switches and three capacitors to realize two distinct configurations: a nine-level circuit employing three series-connected single-voltage clamping sets, and a thirteen-level variant utilizing a hybrid of single- and half-voltage clamping sets. A critical advantage of this architecture is its capability to achieve capacitor self-voltage balancing within a single AC cycle, thereby simplifying the control strategy. Verification through PSIM 9.1 simulations and a TI F280025C-based hardware prototype confirms the circuit’s operational effectiveness. Notably, the thirteen-level configuration demonstrates superior performance, achieving a total harmonic distortion (THD) of 1.25% and a peak efficiency of 97.5%, significantly outperforming the 1.43% THD and 94.5% efficiency of the nine-level counterpart. Full article