A New Switching Configuration for a Bipolar Full-Bridge Boost Converter: Dynamic Analysis and Model Validation

Abstract

This paper proposes a new single-stage bipolar Boost DC/DC converter topology, hereafter referred to as the Full-bridge Boost converter. The proposed architecture enables the generation of a bipolar output voltage with a magnitude equal to or greater than the input voltage, reducing the passive component count. Specifically, a single inductor and a single capacitor are employed, in conjunction with a full-bridge structure and auxiliary switches, to achieve both voltage boosting and polarity inversion within a unified conversion stage. A comprehensive switching configuration is presented, and a mathematical model based on the system switching dynamics is derived. Furthermore, the steady-state behavior is analyzed, yielding an explicit expression for the voltage gain as a function of the control input. In addition, ripple analysis and continuous conduction mode (CCM) boundary conditions are derived to establish design constraints for the converter operation. The characteristic waveforms under both CCM and discontinuous conduction mode (DCM) operation are also analyzed. The validity of the proposed topology and its mathematical representation is verified through MATLAB/Simulink simulations. The detailed switching-level converter is implemented using the Simscape Electrical environment, and the numerical results of the averaged model are compared against the circuit-level simulation through waveform analysis and root mean square error (RMSE) indices to assess modeling accuracy. Finally, implementation feasibility considerations, including semiconductor stress, dead-time requirements, conduction and switching losses, and efficiency analysis, are discussed.

1. Introduction

The generation of electrical power from renewable energy sources (such as wind, solar, hydropower, geothermal energy, and biomass) has steadily increased, gradually replacing fossil fuel-based power generation [1]. However, the electrical energy produced by these sources is typically available at relatively low voltage levels. Consequently, voltage step-up stages are required either to enable long-distance power transmission with minimal energy losses or to directly supply specific applications. In this context, power electronic converters have gained increasing relevance due to their high efficiency in electrical energy conversion and their ease of integration into a wide variety of systems [2]. Among them, the DC/DC Boost converter, characterized by its ability to increase the output voltage relative to the input voltage, has been widely used in applications such as photovoltaic systems [3,4,5], wind energy conversion systems [6,7], electric vehicles [8,9], and other industrial sectors [10,11].

The conventional DC/DC Boost converter provides a unipolar output voltage with the same polarity as the input source. Although its voltage gain can theoretically be increased by adjusting the PWM duty cycle, the output polarity remains fixed. Nevertheless, many practical applications require the generation of bipolar voltage levels, where the output can assume both positive and negative values with respect to a common reference [12,13]. In traditional implementations, bipolar voltage generation is achieved by cascading a DC/DC Boost converter with a full-bridge inverter stage. While effective, this multi-stage approach increases component count, control complexity, and overall system size. To mitigate structural complexity, several Boost-derived topologies have been proposed to integrate voltage step-up and polarity inversion within a single stage.

1.1. State of the Art

To address the need for bipolar voltage generation, numerous Boost-derived converter topologies have been reported. A straightforward approach to obtaining a bipolar output voltage consists of placing a Boost converter between the DC source and an inverter, as shown in Figure 1. However, depending on the power and voltage levels, this configuration may lead to increased volume, weight, and cost, as well as reduced overall efficiency [14]. Although such cascaded structures are typically employed for AC waveform generation, the objective of the present work is not the synthesis of sinusoidal signals but the realization of a single-stage DC/DC converter capable of generating controlled positive and negative voltage levels with step-up capability.

An improvement over the configuration shown in Figure 1 is presented in Figure 2. According to Cáceres and Barbi [14], two Boost converters are combined to generate a DC-biased sinusoidal output. The modulation signals of each converter are phase-shifted by ${180}^{\circ }$, with the load connected differentially between their outputs. Depending on the switching states of the transistors, a bipolar voltage is obtained across the load terminals. The averaged mathematical model describing the dynamics of this DC/AC Boost converter is nonlinear and of fourth order [14,15].

Arunkumar et al. [16] investigated the DC/AC Boost converter shown in Figure 2 by incorporating component nonlinearities into the mathematical model. By accounting for these nonlinear effects, the resulting model more accurately represents the dynamic behavior of the experimental prototype while preserving the fundamental characteristics of the conventional Boost converter.

The Z-source inverter (ZSI), illustrated in Figure 3, was introduced in [17]. This topology employs an X-shaped $LC$ impedance network between the inverter bridge and the power source, along with an $LC$ low-pass filter at the output. Consequently, the load voltage can be bipolar with a magnitude either greater than or less than that of the source, depending on the switching states. Furthermore, the Z-source inverter can operate with both DC and AC inputs to generate either DC or AC outputs.

Ravindranath et al. [18] proposed a modification of the Z-source inverter, referred to as the switched Boost inverter (SBI), as shown in Figure 4. Compared with the ZSI in Figure 3, the switched Boost inverter incorporates additional active switches while reducing the count of passive components, specifically inductors and capacitors. This modification results in a notable reduction in system size, weight, and cost while preserving the operational advantages of the ZSI.

Ray et al. [19] proposed a Boost-derived hybrid converter, as depicted in Figure 5, obtained by replacing the transistor in a conventional DC/DC Boost converter with a network of ideal switches. This configuration enables the simultaneous generation of both AC and DC voltages. However, experimental results indicate that while the DC voltage is effectively boosted, the AC voltage does not experience amplification.

The topology shown in Figure 6 employs the same components as the switched Boost inverter depicted in Figure 4, with the key difference being that the DC source is connected in series with the inductor $L_1$. Consequently, the quasi-switched Boost inverter (qSBI) proposed in [20] achieves continuous input current operation and an enhanced voltage gain.

Nguyen et al. [21] extended the switched Boost inverter by incorporating an additional inductor and three diodes, resulting in the topology known as the switched-inductor Boost inverter (SLBI), shown in Figure 7. This configuration exhibits a higher voltage gain compared to the conventional switched Boost inverter presented in Figure 4.

Half-bridge and full-bridge switched-Boost inverter topologies were proposed in [22], as shown in Figure 8. These converters provide high voltage gain, high efficiency, and a reduced passive component count compared to conventional Z-source inverters (Figure 3). Additionally, they offer continuous input current and the capability to generate a zero-voltage output level.

Nguyen and Tran [23] modified the quasi-switched Boost inverter shown in Figure 6 and proposed a four-switch switched-Boost inverter, illustrated in Figure 9. In this topology, the transistor located between the capacitor and the DC source is replaced by a half-bridge. Consequently, the active switch count is reduced compared to the quasi-switched Boost inverter, and a capacitor is employed to eliminate the DC offset at the output. The reported results demonstrate an increased voltage gain compared to other Boost-derived converters.

The converter proposed in [24], shown in Figure 10, is primarily composed of five switches, a diode, an input inductor, a capacitor, and an output filter. This non-isolated step-up DC–AC converter results from integrating a DC/DC Boost converter with a conventional full-bridge inverter. The reported results indicate a significant reduction in leakage current, thereby improving both reliability and conversion efficiency.

Recently, García-Rodríguez et al. [25] proposed a cascaded topology composed of a DC/DC Boost converter, a full-bridge inverter, and a DC/DC Buck converter, as shown in Figure 11. In this configuration, the Boost converter increases the input voltage, the full-bridge generates a bipolar output, and the Buck converter provides additional filtering and regulation through its $LC$ stage.

The aforementioned topologies are reviewed not for their sinusoidal AC generation capability but because they belong to the class of Boost-derived converters that incorporate voltage step-up and polarity inversion. The state-of-the-art proposed converter shares this architectural principle.

From a topological and modulation perspective, recent single-stage bipolar step-up converters can be broadly classified into differential Boost–inverter converters [14,15,16], impedance-source inverters [17,20,21], hybrid Boost–inverter topologies [18,19,22,23,24], and cascaded Boost–inverter configurations [25]. In these topologies, bipolar voltage generation is commonly achieved through phase-shifted modulation, shoot-through states, switched-inductor boosting mechanisms, or full-bridge inversion stages. In contrast, the proposed converter employs a simplified switching configuration in which voltage boosting and polarity inversion are integrated within a unified DC/DC stage without requiring impedance-source networks or shoot-through operation. Owing to their capability for bipolar voltage generation and voltage boosting, converters of this class may also be relevant in emerging DC distribution and high-voltage DC applications. In this context, fault-tolerant and controllable DC conversion structures for HVDC systems have recently attracted considerable attention [26].

An alternative approach to voltage boosting consists of using multilevel Boost power converters, which generate multiple output voltage levels from several lower-voltage sources. This technique enables a significant reduction in harmonic content and improves system efficiency [27,28,29,30,31,32,33]. However, multilevel converters are not considered in this work. In addition to multilevel structures, isolated Boost-type DC/DC converters have been extensively investigated in the literature. These topologies typically employ high-frequency transformers to provide galvanic isolation and to extend the voltage conversion ratio through the turn ratio [34,35]. In such converters, the voltage boosting mechanism is inherently linked to magnetic energy transfer, the transformer turn ratio, and secondary-side rectification structures. The energy-processing principle is, therefore, magnetically coupled and structurally dependent on isolation stages. In contrast, non-isolated Boost converters achieve voltage step-up exclusively through duty-cycle modulation and direct inductor energy transfer without magnetic coupling. Consequently, the averaged dynamic models, gain-generation mechanisms, and switching-state structures of isolated and non-isolated converters belong to fundamentally different architectural families. For this reason, isolated Boost converters are outside the scope of this work.

1.2. Discussion and Contributions

In this paper, a novel bipolar Boost DC/DC topology is proposed. The proposed Full-bridge Boost converter consists of a DC source, a single inductor, a full-bridge stage, an additional pair of transistors, a capacitor, and a resistive load. Compared with the previously reported topologies shown in Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11, the proposed converter employs a reduced number of passive components relative to those presented in [14,15,16,17,18,19,20,21,22,23,24,25]. Specifically, unlike the conventional Z-source inverter [17] or switched-Boost inverter [18] topologies, the proposed Full-bridge Boost converter does not rely on impedance-source networks, shoot-through states, switched-inductor cells, or capacitor-assisted boosting structures to achieve bipolar voltage generation. Instead, the proposed topology employs a full-bridge switching configuration together with a single inductor and a single capacitor to integrate voltage boosting and polarity inversion within a unified DC/DC stage. As a result, the proposed converter presents a structurally simpler alternative to existing switched-Boost and Z-source-derived converters. By appropriately controlling the switching states of the transistors, a bipolar output voltage is obtained at the full-bridge terminals while the input voltage is simultaneously stepped up. Simulation results are presented to validate the performance and feasibility of the proposed topology.

Although the proposed converter employs a full-bridge switching arrangement that may appear visually similar to the conventional current-fed full-bridge (CFFB) isolated Boost converter shown in Figure 12, both topologies belong to fundamentally different architectural classes.

In the conventional CFFB, the voltage-Boost mechanism is intrinsically dependent on the high-frequency transformer, the turn ratio n, the primary short-circuit interval, and the secondary rectifier stage. Its averaged model explicitly contains the transformer-dependent factor $1/\left(2n\right)$, and the static gain is given by [35],

$$G={\displaystyle \frac{2n}{1-D_c}},$$

which demonstrates that both the dynamic behavior and the voltage conversion ratio are structurally linked to magnetic coupling. Therefore, the transformer is not an auxiliary element but a fundamental component that defines the energy-processing mechanism of the converter.

In contrast, the proposed Full-bridge Boost converter belongs to the family of non-isolated voltage-fed topologies, where energy transfer occurs directly between the inductor and the load through controlled switching states, without transformer coupling, short-circuit intervals, or secondary rectification stages. As a result, the voltage-Boost mechanism is determined not by magnetic coupling or transformer turn ratio but by the switching configuration and the modulation strategy. This leads to a fundamentally different averaged dynamic structure and gain-generation principle, which are formally derived and analyzed in the following sections. The complete proposed circuit topology and switching configuration are formally introduced in Section 2.

Based on the comprehensive review of the state of the art and the technical gaps identified in existing bipolar power conversion solutions, the main contributions of this work are established as follows:

• A new Full-bridge Boost converter topology is established that is capable of generating bipolar voltage using only six switches, one inductor, one capacitor, and a resistive load.
• The formal mathematical representation is developed through the derivation of both switched and averaged models based on Kirchhoff’s theorems to provide a complete theoretical framework for dynamic analysis.
• The operating regions are characterized by defining the boundary conditions for continuous and discontinuous conduction modes to establish deterministic design constraints.
• The steady-state performance is evaluated through the analytical derivation of the current-voltage ripple expressions and the static voltage gain under a constant PWM duty cycle to establish the fundamental operating characteristics of the topology.
• A high-fidelity validation framework is implemented in MATLAB R2023b/Simulink using Simscape Electrical and RMSE metrics to demonstrate the dynamic accuracy of the proposed model across the entire operational range.
• The validation of the mathematical model is achieved through a comprehensive comparison between numerical results obtained from the averaged equations and high-fidelity circuit-level simulations to ensure the consistency of the proposed theory with physical behavior.

To further highlight the advantages of the proposed topology relative to existing Boost-derived converters that integrate voltage boosting and polarity inversion,

Table 1. Comparison of efficiency, voltage stress, and control complexity with related topologies.

Topology	Active	Passive	Typical	Voltage	Control
	Switches	Components	Efficiency	Stress	Complexity
DC/DC Boost–inverter–Buck converter [14]	6	2L + 2C	∼80%	Low	High
DC/AC Boost converter [14,15,16]	4	2L + 2C	∼75−85%	Moderate	High
Z-source inverter [17]	4	3L + 3C	∼90%	Low	Medium
Switched Boost inverter [18]	5	2L + 2C	∼90%	High	Medium
Boost-derived hybrid converter [19]	4	3L + 2C	∼85%	Moderate	Medium
Quasi-switched Boost inverter [20]	5	2L + 1C	79–84%	Low	Medium
Switched-inductor Boost inverter [21]	5	3L + 2C	∼90%	Moderate	Medium
Half-bridge switched-Boost inverter [22]	4	1L + 2C	∼90–95%	Low	Medium
Full-bridge switched-Boost inverter [22]	6	1L + 2C	∼90–95%	Low	Medium
Switched-Boost inverter with four switches [23]	4	2L + 2C	∼90%	Moderate	Medium
Non-isolated step-up DC-AC converter [24]	5	2L + 2C	∼95%	Moderate	Medium
DC/DC Boost–Full-Bridge–Buck Inverter [25]	5	2L + 2C	∼85–90%	Low	High
Proposed Full-bridge Boost Converter	6	1L + 1C	Expected high	High	Medium

provides a comparative overview in terms of the number of active switches, passive components, efficiency, voltage stress, and control complexity. The values reported in Table 1 are qualitative or representative ranges extracted from the corresponding references and are intended to provide a comparative assessment of the structural and operational characteristics of the considered topologies. As can be observed, the proposed Full-bridge Boost converter achieves bipolar voltage boosting using a reduced number of passive components while preserving a single-stage conversion structure.

The remainder of this paper is organized as follows. Section 2 introduces the proposed Full-bridge Boost converter topology and describes its operating principles and switching configurations. Subsequently, the switching-based and averaged mathematical models of the converter are derived, and a steady-state analysis is carried out to determine the static voltage gain. Simulation results and model validation are presented in Section 4, where the averaged model is compared against circuit-level simulations implemented in MATLAB/Simulink. Finally, the main conclusions of the work are summarized in Section 5.

2. The New Full-Bridge Boost Converter System

The proposed Full-bridge Boost converter is a novel DC/DC topology that enables bipolar boosting of the input voltage magnitude. The circuit diagram of the converter is shown in Figure 13. It comprises a DC supply voltage E, a single inductor L, an array of six power transistors ($T_1$ to $T_6$), and an $RC$ network consisting of a capacitor C and a load resistor R connected in parallel.

Through an appropriate switching sequence of transistors $T_1$ to $T_6$, the proposed converter generates a bipolar output voltage v. As demonstrated in Section 2.1, the magnitude of this output can be controlled to be equal to or greater than that of the unipolar source E.

2.1. Switching Configuration

The operation of the proposed Full-bridge Boost converter system is divided into four distinct switching phases, as summarized in

Table 2. Switching configuration: transistor activation for the four operating phases of the proposed Full-bridge Boost converter system.

	Positive Charging	Positive Discharging	Negative Charging	Negative Discharging
$T_1$	ON	ON	ON	OFF
$T_2$	ON	OFF	ON	ON
$T_3$	ON	OFF	ON	ON
$T_4$	ON	ON	ON	OFF
$T_5$	OFF	ON	OFF	ON
$T_6$	OFF	ON	OFF	ON

.

Transistors $T_1$ to $T_4$ constitute a full-bridge (H-bridge) stage responsible for controlling the polarity of the output voltage v. Transistors $T_5$ and $T_6$, in coordination with the H-bridge, regulate the energy charging and discharging cycles of the converter.

Assuming ideal switching devices, the output voltage satisfies $v>0$ during the positive charging and discharging phases. Conversely, during the negative charging and discharging phases, the output voltage satisfies $v<0$.

As detailed in Table 2, the practical implementation requires three independent PWM signals. The first PWM signal drives transistors $T_1$ and $T_4$, the second drives $T_2$ and $T_3$, and the third controls $T_5$ and $T_6$. Considering the positive charging and discharging phases, transistors $T_1$ and $T_4$ remain continuously ON, while transistors $T_2$ and $T_3$ switch complementarily with respect to transistors $T_5$ and $T_6$. Similarly, during the negative charging and discharging phases, transistors $T_2$ and $T_3$ remain continuously ON, whereas transistors $T_1$ and $T_4$ switch complementarily with respect to transistors $T_5$ and $T_6$.

To characterize the switching dynamics of the proposed Full-bridge Boost converter, the equivalent circuit corresponding to each operating phase is analyzed in the following sections.

2.1.1. Positive Charging Phase

Based on the transistor switching states defined in Table 2, the equivalent circuit for the positive charging phase is illustrated in Figure 14.

Applying Kirchhoff’s theorems to the inductor L and capacitor C loops yields the following dynamic model:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{di}{dt}}& =E,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

(1)

2.1.2. Positive Discharging Phase

The equivalent circuit for the positive discharging phase is shown in Figure 15.

During this phase, the energy previously stored in the inductor L is transferred to the $RC$ network. The corresponding dynamics is described by

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{di}{dt}}& =E-v,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =i-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

(2)

It is worth noting that, during the positive discharging phase, the inductor current may reach zero if the Full-bridge Boost converter operates in discontinuous conduction mode (DCM). Under this condition, the inductor remains in a zero-current state, and the capacitor supplies the load according to

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill i& =0,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

Therefore, the inductor current satisfies $i\ge 0$ during the positive operating phases. In the remainder of this work, the proposed Full-bridge Boost converter is assumed to operate in continuous conduction mode (CCM) unless otherwise specified; that is, the inductor current does not reach zero within a switching period.

2.1.3. Negative Charging Phase

For the negative charging phase, where $v<0$ is expected, the inductor stores energy as illustrated in Figure 16.

Since the positive and negative charging phases share the same switching configuration (see Table 2), the model for the negative charging phase is identical to that of the positive charging phase:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{di}{dt}}& =E,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

(3)

2.1.4. Negative Discharging Phase

In the negative discharging phase, the H-bridge reverses the polarity of the voltage applied to the $RC$ network, as shown in Figure 17.

Applying Kirchhoff’s theorems yields

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{di}{dt}}& =E+v,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =-i-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

(4)

Similar to the positive discharging phase, during the negative discharging phase the inductor current may also reach zero under discontinuous conduction mode (DCM) operation. In such a case, the converter enters a zero-current state described by

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill i& =0,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =-{\displaystyle \frac{v}{R}},\hfill \end{array}\end{array}$$

thus ensuring that the inductor current satisfies $i\ge 0$ during the negative operating phases.

2.2. Switching Model

The switching models given by (1)–(4) can be unified into a single switched representation by introducing the dimensionless discrete switching function $u\in \{-1,0,1\}$, which represents the converter switching configuration:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{di}{dt}}& =E-uv,\hfill \\ \hfill C{\displaystyle \frac{dv}{dt}}& =ui-{\displaystyle \frac{v}{R}}.\hfill \end{array}\end{array}$$

(5)

Each operating phase is obtained by assigning to u the value specified in

Table 3. Values of the discrete switching function u for the four operating phases.

	Positive Charging	Positive Discharging	Negative Charging	Negative Discharging
u	0	1	0	$-1$

. Consequently, the unified switched model in (5) reproduces the individual operating modes described by (1)–(4). Moreover, the discrete switching function u determines the active switching state associated with the PWM implementation, as detailed in Section 4.1, and enables the derivation of the averaged model under CCM conditions.

2.3. Averaged Model

Following standard averaging techniques for CCM [36], the switched model (5) can be extended to an averaged representation by allowing the discrete switching function u to take values in the continuous interval $[-1,0)\cup (0,1]$. The dimensionless averaged input is denoted by $\overline{u}$, while the averaged inductor current and capacitor voltage are denoted by $\overline{i}$ and $\overline{v}$, respectively. The resulting averaged model is expressed as

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{d\overline{\mathsf{ı}}}{dt}}& =E-\overline{u}\overline{v},\hfill \\ \hfill C{\displaystyle \frac{d\overline{v}}{dt}}& =\overline{u}\overline{\mathsf{ı}}-{\displaystyle \frac{\overline{v}}{R}}.\hfill \end{array}\end{array}$$

(6)

The averaged model (6) serves as the basis for the steady-state analysis of the proposed “Full-bridge Boost converter system”, which is presented in the following section.

2.4. Steady-State Analysis of the Proposed Full-Bridge Boost Converter System

Under steady-state conditions, the time derivatives of the averaged state variables in (6) are set to zero, yielding the following algebraic relationships:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill 0& =E-{\overline{u}}_{ss}{\overline{v}}_{ss},\hfill \\ \hfill 0& ={\overline{u}}_{ss}{\overline{\mathsf{ı}}}_{ss}-{\displaystyle \frac{{\overline{v}}_{ss}}{R}},\hfill \end{array}\end{array}$$

(7)

where ${\overline{u}}_{ss}$, ${\overline{v}}_{ss}$, and ${\overline{\mathsf{ı}}}_{ss}$ denote the steady-state control input, output voltage, and inductor current, respectively. Solving (7) gives the steady-state current and voltage as functions of ${\overline{u}}_{ss}$:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill {\overline{\mathsf{ı}}}_{ss}& ={\displaystyle \frac{E}{{\overline{u}}_{ss}^{2}R}},\hfill \\ \hfill {\overline{v}}_{ss}& ={\displaystyle \frac{E}{{\overline{u}}_{ss}}}.\hfill \end{array}\end{array}$$

(8)

From (8), the steady-state voltage gain of the Full-bridge Boost converter is obtained as

$$\begin{array}{c}\hfill G\left({\overline{u}}_{ss}\right)={\displaystyle \frac{{\overline{v}}_{ss}}{E}}={\displaystyle \frac{1}{{\overline{u}}_{ss}}}.\end{array}$$

(9)

The gain $G\left({\overline{u}}_{ss}\right)$ for ${\overline{u}}_{ss}\in [-1,0)\cup (0,1]$ is shown in Figure 18, where $G\left(1\right)=1$, $G(-1)=-1$, and ${lim}_{{\overline{u}}_{ss}\to 0^{\pm }}G\left({\overline{u}}_{ss}\right)=\pm \infty$.

2.5. Ripple Analysis and Continuous Conduction Mode Boundary Conditions

The inductor current and output voltage ripples, along with the continuous conduction mode (CCM) boundary condition, constitute fundamental design constraints for the proposed converter. These quantities are derived from the steady-state waveforms depicted in Figure 19, where $i_1$ and $i_2$ denote the minimum and maximum inductor currents, respectively, while $v_1$ and $v_2$ represent the minimum and maximum output voltages within a switching period. The corresponding average values of the inductor current and output voltage are denoted by $\overline{i}$ and $\overline{v}$, respectively.

Assuming linear current and voltage variations within each switching subinterval, the positive charging phase dynamics given in (1) leads to:

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill L{\displaystyle \frac{\Delta i}{t_1}}& =E,\hfill \\ \hfill -C{\displaystyle \frac{\Delta v}{t_1}}& =-{\displaystyle \frac{\overline{v}}{R}},\hfill \end{array}\end{array}$$

(10)

where $\Delta i=i_2-i_1$ and $\Delta v=v_2-v_1$ represent the peak-to-peak inductor current and output voltage ripples, respectively. Similarly, from the positive discharging phase in (2),

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill -L{\displaystyle \frac{\Delta i}{t_2}}& =E-\overline{v}\hfill \\ \hfill C{\displaystyle \frac{\Delta v}{t_2}}& =\overline{i}-{\displaystyle \frac{\overline{v}}{R}}.\hfill \end{array}\end{array}$$

(11)

Using the switching frequency definition $f_{sw}=1/(t_1+t_2)$, the ripple magnitudes are obtained as

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill \Delta i& ={\displaystyle \frac{E}{L}}{\displaystyle \frac{(1-\overline{u})}{f_{sw}}},\hfill \\ \hfill \Delta v& ={\displaystyle \frac{E}{RC}}{\displaystyle \frac{\left(1-\overline{u}\right)}{f_{sw}\overline{u}}}.\hfill \end{array}\end{array}$$

(12)

Equation (12) explicitly reveals the inverse proportionality of the ripples to the switching frequency and passive components, and their nonlinear dependence on the duty cycle. The inductor current and output voltage ripples computed from the parameter values given in

$$\begin{array}{c}E=32 \mathrm{V},\hspace{1em}L=4.97 \mathrm{mH},\hspace{1em}C=114.7 \mathrm{\mu }\mathrm{F},\hspace{1em}R=48 \Omega ,\end{array}$$

(13)

are $\Delta i=71.54 \mathrm{mA}$ and $\Delta v=129.16 \mathrm{mV}$, respectively.

On the other hand, the critical inductance $L_c$ required to guarantee CCM operation can be derived from the boundary condition $i_1=0$, as illustrated in Figure 19. Additionally, the minimum capacitance value $C_c$ can be obtained from the condition $\Delta v=2\overline{v}$ in order to establish a capacitive design constraint. Under these conditions, a bound design approximation is obtained by imposing $\Delta i=2\overline{i}$ and $\Delta v=2\overline{v}$. Substituting these relationships into (12) yields the following design criteria

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill 2\overline{\mathsf{ı}}& =\Delta i={\displaystyle \frac{E}{L_c}}{\displaystyle \frac{\left(1-\overline{u}\right)}{f_{sw}}},\hfill \\ \hfill 2\overline{v}& =\Delta v={\displaystyle \frac{E}{R{C}_c}}{\displaystyle \frac{\left(1-\overline{u}\right)}{f_{sw}\overline{u}}},\hfill \end{array}\end{array}$$

(14)

therefore, by substituting the steady-state relationships from (8), the critical inductance and capacitance are determined as follows:

$$\begin{array}{c}\hfill \begin{array}{c}\hfill L_c={\displaystyle \frac{R}{2}}{\displaystyle \frac{\overline{u}\left(1-\overline{u}\right)}{f_{sw}}},\\ \hfill C_c={\displaystyle \frac{1}{2R}}{\displaystyle \frac{\left(1-\overline{u}\right)}{f_{sw}}}.\end{array}\end{array}$$

(15)

For the design parameters (13) $R=48 \Omega$, $\overline{u}=0.5$, and $f_{sw}=45$ kHz, the critical values are calculated as $L_c=133.33$ μH and $C_c=115.74$ nF, respectively. Given that the selected components satisfy $L=4.97 \mathrm{mH}\gg L_c$ and $C=114.7$ $\mathrm{\mu }\mathrm{F}$$\gg C_c$, the operation of the Full-bridge Boost converter is guaranteed to operate in CCM.

3. Design Considerations and Constraints

In addition to the switching and averaged models presented above, several aspects related to the implementation feasibility of the proposed Full-bridge Boost converter must be analyzed. These include the electrical stresses imposed on the semiconductor devices, dead-time requirements, conduction and switching losses, and the overall converter efficiency.

3.1. Semiconductor Stress

This analysis is essential for assessing the practical feasibility of the topology, facilitating the selection of power devices with appropriate voltage and current ratings.

3.1.1. Voltage Stress

Based on the switching configurations summarized in Table 2 and the equivalent circuits depicted in Figure 14, Figure 15, Figure 16 and Figure 17, it is evident that during their blocking intervals, the transistors are subjected to voltage stresses associated with the output voltage across the $RC$ network. Therefore, the maximum blocking voltage across each transistor satisfies

$$\begin{array}{c}\hfill |V_{T_k}^{max}|=\left\{\begin{array}{cc}|\overline{v}+{\displaystyle \frac{1}{2}}\Delta v|-E\hfill & k=1,2,3,4,\hfill \\ |\overline{v}+{\displaystyle \frac{1}{2}}\Delta v|\hfill & k=5,6,\hfill \end{array}\right.\end{array}$$

(16)

where $\Delta v$ is the small output voltage ripple. Using the steady-state relation obtained in (8), the output voltage magnitude is

$$|{\overline{v}}_{ss}|=\left|{\displaystyle \frac{E}{{\overline{u}}_{ss}}}\right|.$$

(17)

It follows that the voltage stress increases as $|{\overline{u}}_{ss}|$ decreases. In particular,

$$\underset{{\overline{u}}_{ss}\to 0}{lim}|{\overline{v}}_{ss}|=\infty .$$

(18)

which highlights the need to restrict the operating range of the modulation variable in practical implementations. In practice, this condition is limited by semiconductor ratings, parasitic effects, and non-ideal converter dynamics.

3.1.2. Current Stress

Transistors $T_1$–$T_6$ participate directly in the charging and discharging of the inductor. Consequently, their current stress is primarily determined by the inductor current. Assuming continuous conduction mode (CCM) operation, the maximum current can be approximated as

$$I_{T_k}^{max}=\overline{\mathsf{ı}}+{\displaystyle \frac{1}{2}}\Delta i, k=1,\dots ,6,$$

(19)

where $\Delta i$ is the small inductor current ripple. Both the analysis of the output voltage and the inductor current ripples are detailed in Section 4. Considering (8), the steady-state inductor current is given by

$${\overline{\mathsf{ı}}}_{ss}={\displaystyle \frac{E}{{\overline{u}}_{ss}^{2}R}}.$$

Therefore, the current stress of the transistors depends on the selected operating point through ${\overline{u}}_{ss}$ and the load resistance R. Similarly to the voltage stress, the current stress increases as $|{\overline{u}}_{ss}|$ decreases, and

$$\underset{{\overline{u}}_{ss}\to 0}{lim}{\overline{\mathsf{ı}}}_{ss}=\infty .$$

(20)

This behavior further supports the requirement to bound the modulation variable in order to avoid excessive semiconductor stress.

3.2. Dead-Time Requirement

Since the proposed topology incorporates complementary switching sequences, a dead-time interval must be introduced during switching transitions to prevent shoot-through conditions. As detailed in Table 2, the gating signals for $T_1$ and $T_4$ are complementary to those of $T_5$ and $T_6$ during the positive phases; conversely, the signals for $T_2$ and $T_3$ are complementary to $T_5$ and $T_6$ during the negative phases. The required dead-time duration depends on the turn-off delay and fall-time characteristics of the selected semiconductor technology. An insufficient dead time may induce shoot-through currents across the DC source, thereby increasing switching losses and potentially compromising device reliability.

3.3. Loss Analysis

To evaluate the practical feasibility of the proposed Full-bridge Boost converter, the primary non-idealities of both passive components and semiconductor devices are incorporated into the averaged model. Specifically, the equivalent series resistances (ESRs) of the inductor and capacitor, along with the conduction and switching losses of the transistors, are considered to provide a more accurate representation of the system dynamics and efficiency.

3.3.1. Conduction Losses

Under continuous conduction mode (CCM) and considering the triangular ripple approximation $\Delta i$, the RMS current is given by

$$I_{RMS}^2={\overline{\mathsf{ı}}}^{ 2}+{\displaystyle \frac{\Delta i^2}{12}}.$$

(21)

From the switching sequence summarized in Table 2, the RMS current through each transistor is

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill I_{T_1,RMS}^2& =I_{T_4,RMS}^2=I_{RMS}^2,\hfill \\ \hfill I_{T_2,RMS}^2& =I_{T_3,RMS}^2=(1-\overline{u})I_{RMS}^2,\hfill \\ \hfill I_{T_5,RMS}^2& =I_{T_6,RMS}^2=\overline{u}{I}_{RMS}^2.\hfill \end{array}\end{array}$$

(22)

Due to the switching operation of the converter, the transistor onducts during different fractions of the switching period. Using the RMS current expressions obtained above, the conduction loss of each transistor can be approximated as

$$P_{\sigma ,T_k}=I_{T_k,RMS}^2{R}_{DS},\hspace{1em}k=1,2,3,4,5,6,$$

(23)

where $R_{DS}$ is the drain–source on-resistance of the transistors. By considering the RMS current through each transistor (22), the total conduction loss of the semiconductor devices can be expressed as

$$P_{\sigma }={\displaystyle \sum _{k=1}^6}{P}_{\sigma ,T_k}=4I_{RMS}^2{R}_{DS}.$$

(24)

Using the steady-state conditions (8), the total conduction loss results in

$$P_{\sigma }=4R_{DS}\left({\displaystyle \frac{E^2}{{\overline{u}}^4{R}^2}}+{\displaystyle \frac{\Delta i^2}{12}}\right).$$

(25)

The resistive losses of the inductor and capacitor are given by

$$P_{r_L}=\left({\displaystyle \frac{E^2}{{\overline{u}}^4{R}^2}}+{\displaystyle \frac{\Delta i^2}{12}}\right)r_L,$$

(26)

$$P_{r_C}={\displaystyle \frac{\Delta i^2}{12}}{r}_C,$$

(27)

where $r_L$ and $r_C$ denote the equivalent series resistances of the inductor and capacitor, respectively.

3.3.2. Switching Losses

In addition to conduction losses, the switching transitions of the semiconductor devices produce additional power dissipation due to the overlap between the drain–source voltage and the drain current during turn-on and turn-off events. Assuming the commonly used linear approximation for the voltage and current transitions, the switching energy dissipated by each transistor during a commutation period can be approximated as

$$E_{sw,T_k}\approx {\displaystyle \frac{1}{2}}\overline{v}\overline{i}(t_r+t_f), k=1,2,3,4,5,6,$$

(28)

where $t_r$ and $t_f$ denote the rise and fall times of the transistor, respectively. According to the switching sequence summarized in Table 2, four transistors commutate during each switching period of the Full-bridge Boost converter. Therefore, the total switching loss of the converter can be expressed as

$$P_{sw}=4E_{sw}{f}_{sw},$$

(29)

where $f_{sw}$ denotes the switching frequency. Substituting the switching energy expression yields

$$P_{sw}=2\overline{v}\overline{i}(t_r+t_f)f_{sw},$$

(30)

This expression shows that the switching losses increase proportionally with the output voltage, the average inductor current, the switching frequency, and the intrinsic transition times of the semiconductor devices.

3.3.3. Total Losses and Efficiency

The total power dissipation in the converter is, therefore,

$$P_{tot}=P_{r_L}+P_{r_C}+P_{\sigma }+P_{sw}.$$

(31)

Finally, the efficiency of the converter can be estimated as

$$\eta ={\displaystyle \frac{P_{out}}{P_{out}+P_{tot}}}.$$

(32)

The output power of the converter in steady state is

$$P_{out}={\displaystyle \frac{{\overline{v}}^2}{R}}.$$

(33)

Using the steady-state relation (8), the efficiency equation leads to

$$\eta ={\displaystyle \frac{{\displaystyle \frac{E^2}{{\overline{u}}^{2}R}}}{{\displaystyle \frac{E^2}{{\overline{u}}^{2}R}}+\left({\displaystyle \frac{E^2}{{\overline{u}}^{4}R}}+\frac{\Delta i^2}{12}\right)r_L+\frac{\Delta i^2}{12}{r}_C+4R_{DS}\left(\frac{E^2}{{\overline{u}}^4{R}^2}+\frac{\Delta i^2}{12}\right)+2\frac{E^2}{{\overline{u}}^{3}R}(t_r+t_f)f_{sw}}}.$$

(34)

This expression highlights the influence of the operating point $\overline{u}$ and the parasitic parameters on the overall efficiency of the Full-bridge Boost converter. In particular, high switching frequencies and small values of $|\overline{u}|$ increase semiconductor stresses and switching losses, which may reduce the achievable efficiency.

The presented analysis establishes the basis for a safe practical implementation of the proposed converter. Accordingly,

Table 4. Principal implementation and safe-operation considerations for the proposed Full-bridge Boost converter.

Parameter	Description	Implementation Consideration
$|V_{T_k}^{max}|=|\overline{v}+{\displaystyle \frac{1}{2}}\Delta v|$	Maximum transistor voltage stress	Must remain below the selected semiconductor blocking voltage rating
$I_{T_k}^{max}=\overline{\mathsf{ı}}+{\displaystyle \frac{1}{2}}\Delta i$	Maximum transistor current stress	Must remain below the selected semiconductor current rating
$\overline{u}$	Modulation operating range	Small values of $|\overline{u}|$ increase gain and semiconductor stress
$f_{sw}$	Switching frequency	High values increase switching losses and thermal stress
$t_d$	Dead-time interval	Prevents shoot-through during switching transitions
$R_{DS}$	On-state transistor resistance	Directly affects conduction losses
$t_r,t_f$	Rise and fall times	Influence switching losses
$r_L$	Inductor ESR	Produces additional conduction losses
$r_C$	Capacitor ESR	Increases voltage ripple and power dissipation
$\Delta i={\displaystyle \frac{E}{L}}{\displaystyle \frac{(1-\overline{u})}{f_{sw}}}$	Inductor current ripple	Affects RMS current and semiconductor stress
$\Delta v={\displaystyle \frac{E}{RC}}{\displaystyle \frac{\left(1-\overline{u}\right)}{f_{sw}\overline{u}}}$	Output voltage ripple	Affects voltage quality and capacitor stress
$L_c={\displaystyle \frac{R}{2}}{\displaystyle \frac{\overline{u}(1-\overline{u})}{f_{sw}}}$	Critical inductance	Minimum inductance value for guaranteed CCM operation

summarizes the principal electrical stresses, operating constraints, and implementation-related parameters in order to facilitate hardware implementation considerations.

4. Results

In this section, the signal analysis and validation of the averaged model of the proposed Full-bridge Boost converter system are presented. The validation is carried out by means of circuit-level simulations and numerical simulations of the switching and averaged models implemented in MATLAB/Simulink.

The MATLAB/Simulink block diagram used to obtain the circuit simulation results is shown in Figure 20. It consists of the following main blocks:

• Switching configuration: In this block, the averaged control input $\overline{u}$ is defined, and the corresponding switching signals for transistors $T_1$ to $T_6$ are generated. The switching logic follows the configurations listed in Table 2. In addition, Table 3 is used to determine the discrete input u from the PWM signals, which are generated by the PWM Generator block of the Simscape Electrical toolbox with a switching frequency $f_{sw}=45$ kHz.
• Measurements: This block acquires and displays the relevant signals from the Switching configuration and Full-bridge Boost converter subsystems.
• Full-bridge Boost converter: In this block, the proposed Full-bridge Boost converter is implemented using the Simscape Toolbox. Discrete simulation is selected in the powergui settings with a sampling time of 22.2 ns.

The numerical simulation of the ideal averaged model is performed by implementing equations (6) in MATLAB/Simulink. Both the circuit-level simulation and the averaged model simulation employ the Euler numerical integration method with a fixed step size of 22.2 ns.

4.1. Waveforms and Switching Model Validation for the CCM Operation

This subsection analyzes the typical voltage and current waveforms of the proposed Full-bridge Boost converter system. The converter is assumed to operate in continuous conduction mode (CCM) by selecting the parameter values given in (13), such that neither the inductor current nor the output voltage reaches zero.

Under CCM operation, two main waveform patterns arise for the output voltage v and the inductor current i, depending on the sign of the averaged input $\overline{u}$. When $\overline{u}>0$, the converter operates in the positive charging and positive discharging phases. In this case, transistors $T_1$ and $T_4$ remain continuously on, while transistors $T_2$ and $T_3$ switch with a duty cycle of $1-\overline{u}$. Simultaneously, transistors $T_5$ and $T_6$ switch with a duty cycle of $\overline{u}$. Conversely, when $\overline{u}<0$, the negative charging and negative discharging phases occur. In this operating mode, transistors $T_2$ and $T_3$ remain continuously on, transistors $T_1$ and $T_4$ switch with a duty cycle of $1+\overline{u}$, and transistors $T_5$ and $T_6$ switch with a duty cycle of $-\overline{u}$.

The waveforms corresponding to the positive charging and discharging phases for $\overline{u}=0.5$ are shown in Figure 21a. Similarly, the waveforms for the negative charging and discharging phases with $\overline{u}=-0.5$ are presented in Figure 21b.

The obtained waveforms confirm that for $\overline{u}>0$, both the output voltage and the inductor current satisfy $v>0$ and $i>0$, whereas for $\overline{u}<0$, the output voltage becomes negative ($v<0$) while the inductor current remains positive. Moreover, Figure 21a,b show that the switching model (5) accurately reproduces the waveform behavior obtained from the circuit-level simulation.

4.2. Waveforms and Switching Model Validation for the DCM Operation

The discontinuous conduction mode (DCM) constitutes an important operating condition in power converters. Therefore, this subsection analyzes the characteristic waveforms of the proposed Full-bridge Boost converter under DCM operation. To induce DCM behavior, the design parameters are selected as

$$\begin{array}{c}E=32 \mathrm{V},\hspace{1em}L=50 \mu \mathrm{H},\hspace{1em}C=50 \mathrm{nF},\hspace{1em}R=48 \Omega ,\end{array}$$

(35)

where $L<L_c$, as established in Section 2.5. Additionally, the reduced capacitance value increases the output voltage ripple. The behavior of the Full-bridge Boost converter under DCM operation for both positive and negative phases is illustrated in Figure 22.

As expected under DCM operation, the inductor current reaches zero during a portion of the switching period in both the positive and negative discharging phases. Moreover, the reduced capacitance produces a significant increase in the output voltage ripple. Furthermore, Figure 22 shows that the switching model (5) reproduces the principal waveform characteristics observed in the circuit-level simulation under DCM operation.

4.3. Averaged Model Validation

In this subsection, the dynamic behavior of the Full-bridge Boost converter obtained from circuit-level simulations is compared against the numerical solution of the averaged model (6). To achieve steady-state output voltages $v=2E$, $v=E$, $v=-E$, and $v=-2E$, a gain function $G\left(\overline{u}\right)$ ranging from $-2$ to 2 is implemented, as illustrated in Figure 23. This is presented alongside the corresponding waveform of the averaged input $\overline{u}$ to demonstrate the wide-range bipolar operation of the topology.

Figure 24 presents a comparative analysis between the averaged model (6) and the Full-bridge Boost converter implementation using circuit-level simulation. The numerical implementation was carried out using the parameter values defined in (13), for which the converter operates under CCM conditions. The results demonstrate that both the voltage and current trajectories of the averaged model closely track the responses of the switching circuit simulation. Therefore, the averaged model provides a high-fidelity representation of the system dynamics across the entire bipolar range, validating its use for subsequent control design.

An appropriate quantitative index to evaluate the agreement between the averaged model dynamics and the circuit-level simulation is the root mean square error (RMSE), defined as

$$\begin{array}{c}\hfill RMS{E}_i=\sqrt{{\displaystyle \frac{1}{n}}\sum _{k=1}^n{\left(\overline{i}\left(k\right)-i_c\left(k\right)\right)}^2},\\ \hfill RMS{E}_v=\sqrt{{\displaystyle \frac{1}{n}}\sum _{k=1}^n{\left(\overline{v}\left(k\right)-v_c\left(k\right)\right)}^2},\end{array}$$

where n is the total number of data samples and k denotes the discrete-time index. The time evolution of $RMS{E}_i$ and $RMS{E}_v$ is shown in Figure 25.

The calculated RMSE values at the end of the simulation are $RMS{E}_i=0.27 \mathrm{A}$ and $RMS{E}_v=2.66 \mathrm{V}$. These metrics indicate that the averaged model of the Full-bridge Boost converter captures the principal dynamic behavior observed in the circuit-level simulation. Notably, the RMSE values are more pronounced during transient intervals and decrease as the system approaches steady-state operation. This behavior is consistent with the fundamental assumptions of the averaging technique, since the high-frequency switching components are inherently filtered in the averaged representation.

5. Conclusions

The “Full-bridge Boost converter” presented in this work demonstrates a notable improvement in structural simplicity when compared with existing bipolar Boost-derived topologies, while retaining the capability to generate a boosted bipolar output voltage. The mathematical model derived for the proposed converter accurately describes its dynamic behavior, making it suitable for analysis as well as for the design of switching and control strategies. Furthermore, ripple analysis and continuous conduction mode (CCM) boundary conditions were derived to establish design constraints for the converter operation, and the characteristic waveforms under both CCM and discontinuous conduction mode (DCM) were analyzed.

Simulation results validate the proposed topology and confirm its ability to achieve bipolar voltage gain, together with the characteristic voltage and current waveforms expected in power electronic converters. Moreover, the averaged model provides a convenient framework for the systematic design of control strategies aimed at voltage regulation and trajectory tracking of the bipolar output. The comparison between the averaged model and the circuit-level simulation, supported through waveform analysis and RMSE indices, demonstrates that the averaged representation captures the principal dynamic behavior of the converter.

In addition, implementation feasibility considerations, including semiconductor stress, dead-time requirements, conduction and switching losses, and efficiency analysis, were discussed in order to provide a preliminary assessment of the practical operation of the proposed topology.

Overall, the proposed Full-bridge Boost converter constitutes a solid and flexible solution for applications requiring controlled positive and negative voltage generation, such as motor drives, robotics, and other power electronic systems.