Hardware-Based Reduction of Submodule Capacitor Voltage Ripple in Modular MultiLevel Converters: A Critical Review

Abstract

This paper reviews circuit topologies in the literature that aim to suppress submodule (SM) capacitor-voltage ripple of modular multilevel converters (MMCs), since this low-frequency ripple largely determines the required SM capacitance and thus the overall converter volume, cost, and reliability. The circuit topologies covered in this review include high-frequency (HF) magnetic or switched power channels, transformerless active channel or bridging cells with mid-cell connections, hybrid-MMC and DC-bus management options, SM-level active power decoupling (APD) and active power filters (APF), and structural modifications. Physical power-channel topologies (HF magnetic or switched auxiliary paths) suppress the $2\omega$ capacitor-voltage ripple by transferring the associated low-frequency ripple power to an auxiliary high-frequency path. Hybrid-MMC and direct-current (DC) bus management reduce the required capacitance with only a modest increase in hardware requirements. SM-level APD and APF cells transfer the ripple power into auxiliary storage. Structural and topological arrangements modify the converter architecture itself, leading to architectural simplification, passive attenuation, and a reduced need for measurement or balancing. The reviewed topologies are then compared in terms of ripple reduction, hardware complexity, additional components, cost, and control complexity, and the resulting evidence is synthesised into application-driven design trade-offs and selection guidelines. In addition, DC–DC MMC topologies are discussed separately in a contextual overview.

1. Introduction

Figure 1 summarizes three representative approaches to direct-current–to–alternating-current (DC–AC) conversion in power electronics: (a) rectification- and commutation-based, thyristor line-commutated converters (LCC); (b) two-level pulse-width-modulated voltage-source converters (2-level PWM-VSC); and (c) three-phase modular multilevel converters (MMCs) composed of phase arms and submodules. This review focuses on hardware-based topology modifications aimed at suppressing submodule capacitor-voltage ripple (CVR) in the MMC architecture shown in Figure 1c, whereas Figure 1a,b are included as a reference framework to contextualize the industrial positioning and evolutionary background of MMC technology. Although MMC is widely regarded as a mature technology and CVR has been investigated for decades, CVR remains a practically relevant constraint because it governs submodule-capacitor sizing and tends to become more pronounced as the output fundamental frequency decreases, particularly in wide-speed-range applications such as medium-voltage motor drives [1,2]. A key design issue in MMC-based drives is the submodule (SM) capacitor-voltage ripple and the associated $2\omega$ circulating-current components, as they directly affect capacitor sizing, semiconductor and reactance losses, torque ripple, common-mode voltage (CMV), and electromagnetic interference (EMI) [3,4,5,6]. Consequently, CVR reduction warrants renewed attention with respect to industrial adoption and power-density targets, even for mature MMC platforms [7].

The CVR caused by the $2\omega$ component of the power can be mitigated by an energy buffer in the SM capacitors [4,5,8,9]. At low speeds (near 0 Hz), active power transfer decreases while internal circulation and the relative effect of reactive components increase; this means higher SM capacitor voltage ripple $(\Delta V_c)$ and increased circulation current $\left(i_{cc}\right)$ for the same torque [4,9,10]. The optimal design of the MMC has to simultaneously consider: (i) capacitor size and permissible ripple, (ii) arm current suppression, (iii) modulation and balancing strategies [5,8,10,11,12,13,14,15,16,17,18,19,20,21,22,23].

Previous work on control-based mitigation of CVR and CC can be broadly divided into balancing, circulating-current suppression, and modulation-based strategies. Balancing-oriented schemes include fast sorting-based balancing [12], predictive derivative methods [8], repetitive suppression [11], and model predictive control (MPC) approaches [6,10]. Circulating-current suppression within a dual-frequency rotating reference frame has been reported in [4]. Modulation-based studies analyse the effects of phase-shifted carrier (PSC) and phase-disposition (PD) pulse-width modulation (PWM) and its variants on CVR and CC; in particular, the linear modulation range and zero-sequence injection options have been revisited for CVR–CMV joint optimisation with the objective of minimising capacitor-voltage ripple and common-mode voltage [5,20,21]. However, these purely control-based methods act only on the existing MMC structure and therefore only redistribute the low-frequency (LF) ripple power among the arms, submodules, and DC side, without introducing any additional energy-storage path or modifying the source term in the arm power balance [3,9,10,13,21]. For this reason, modification of the basic MMC topology has received increasing attention in the power electronics research community. The main hardware-based proposals for DC–AC MMCs include auxiliary high-frequency (HF) magnetic or switched circuits that provide an additional power path for the ripple power (here referred to as auxiliary power channels), active channel or bridging cells and middle-cell configurations that couple the upper and lower arms, hybrid MMC arrangements (e.g., half-bridge plus full-bridge, HB + FB) and DC-bus management schemes (series DC switch, variable DC-bus), submodule- or phase-level active power decoupling (APD) and active power filter (APF) cells, and structural or topological variants that modify the arm and submodule connections. Auxiliary power-channel circuits and APD/APF cells create an additional energy-storage path for the LF ripple power, active channel structures, hybrid MMC arrangements, and DC-bus management schemes modify how this ripple power is shared between the arms and the DC bus through structural changes, while structural and topological variants aim to weaken the ripple source itself through architectural changes.

Beyond the DC–AC operating context considered in this review, MMC-based converter structures have also been widely investigated for DC–DC conversion in HVDC, DC-grid, and multi-level DC-interface applications. In such systems, capacitor-voltage behaviour is not always governed by the same low-frequency second-harmonic arm-energy oscillation that dominates conventional DC–AC MMC operation; instead, voltage deviation is often shaped by energy-drift suppression, balancing and equalisation actions, switching patterns, and topology-specific internal energy circulation. For this reason, the main comparative framework of this review is intentionally centred on hardware-based low-frequency CVR mitigation in DC–AC MMCs, while DC–DC MMC topologies are discussed separately in a contextual overview section.

To provide an industrial context for the reviewed literature,

Table 1. Market overview of commercial converter platforms across industrial applications.

Application	Topology	Manufacturer	Product Model	Rating	Voltage	Semiconductor
HVDC	LCC-HVDC	Siemens Energy, Erlangen, Germany	UHVDC link (Yunnan–Guangdong example) [24,25]	5000 MW	$\pm 800$ kVdc	Thyristor
HVDC	LCC-HVDC	ABB, Zurich, Switzerland	UHVDC link (Xiangjiaba–Shanghai example) [26,27]	6400 MW	$\pm 800$ kVdc	Thyristor
HVDC	LCC-HVDC	Hitachi Energy, Zurich, Switzerland	UHVDC link (North-East Agra example) [28]	8000 MW	$\pm 800$ kVdc	Thyristor
HVDC	VSC-HVDC (2-level PWM-VSC)	ABB, Ludvika, Sweden	HVDC Light (Hellsjön test installation) [29,30]	3 MW	$\pm 10$ kVdc	IGBT
HVDC	VSC-HVDC (2-level PWM-VSC)	ABB, Ludvika, Sweden	HVDC Light (Gotland example) [31]	50 MW	80 kVdc	IGBT
HVDC	VSC-HVDC (MMC)	Siemens Energy, Erlangen, Germany	HVDC PLUS (BorWin2 example) [32,33]	800 MW	$\pm 300$ kVdc	IGBT
HVDC	VSC-HVDC (MMC)	Hitachi Energy, Zurich, Switzerland	HVDC Light (NordLink example) [34]	1400 MW	$\pm 525$ kVdc	IGBT
HVDC	VSC-HVDC (MMC)	Mitsubishi Electric, Warrendale, PA, USA	HVDC-Diamond (platform capability) [35,36]	>1000 MW	up to $\pm 500$ kVdc	IGBT
FACTS	STATCOM (VSC, 2-level)	Ingeteam, Zamudio, Spain	INGEGRID LV800 [37]	$\pm 4$–$\pm 9$ MVAr	600 Vac	IGBT
FACTS	STATCOM (VSC/AFE, 2-level)	Nidec ASI, Milan, Italy	Active Front End (AFE) [38]	up to 2.08/6.90 MVA	0.4/0.69 kVac	IGBT
FACTS	STATCOM (VSC)	Siemens Energy, Erlangen, Germany	SVC PLUS (Kriftel example) [39]	$\pm 300$ MVAr	380 kVac	IGBT
FACTS	STATCOM (VSC)	Hitachi Energy, Zurich, Switzerland	SVC Light (Emirates Steel example) [40]	0–164 MVAr	33 kVac	IGBT
FACTS	STATCOM (VSC)	Mitsubishi Electric (MEPPI), Warrendale, PA, USA.	STATCOM (Colington substation example) [41,42]	$\pm 125$ MVAr	115 kVac	IGBT
Drive	Two-level PWM-VSI (VFD)	Ingeteam, Zamudio, Spain	INGEDRIVE LV200 [43]	0.335–1.380 MW	380–690 Vac	IGBT
Drive	LCC-CSC (LCI)	Siemens, Nuernberg, Germany	SINAMICS GL150 [44]	2.8–85 MVA	2.3–11 kV	Thyristor
Drive	LCC-CSC (LCI)	ABB, Ludvika, Sweden	MEGADRIVE-LCI [45]	2–150 MW	2–10 kV	Thyristor
Drive	LCC-CSC (LCI)	GE Vernova (lineage), Cambridge, MA, USA	SD 7000 [46]	3–100 MW	1.5–15 kV	Thyristor
Drive	Multilevel VSI	Hitachi (Hi-Rel), Sanand, Gujarat, India	HIVECTOL HVI-E [47,48]	up to 19.0 MVA	3.3–11 kV	IGBT
Drive	Multilevel VSI	TMEIC, Tokyo, Japan	TMdrive-MVG2 [49,50]	up to 19.5 MVA	3–11 kV	IGBT
Drive	MMC (M2LC cell-based VSI)	Siemens, Nuernberg, Germany	SINAMICS SM120 CM [51]	4–13.3 MVA	3.3–7.2 kV	IGBT
Drive	MMC (M2LC)	Benshaw, Pittsburgh, PA, USA	M2L Series [52]	0.224–8.952 MW †	up to 7.2 kV	IGBT

^† Benshaw documentation reports 300–12,000 HP; using 1 HP = 0.746 kW and power factor $\approx 1$, MW is approximated.

offers a market-oriented snapshot of representative commercial converter platforms across grid and industrial applications. Specifically, it highlights the main deployed families in high-voltage direct current (HVDC) transmission (line-commutated converter HVDC (LCC-HVDC), 2-level voltage-source converter (VSC) HVDC, and modular multilevel converter (MMC)-based VSC-HVDC), flexible AC transmission systems (FACTS) and static synchronous compensator (STATCOM) applications (2-level VSC and MMC-based STATCOM), and medium-voltage (MV) drive systems (2-level pulse-width-modulated voltage-source inverter (PWM-VSI), line-commutated converter current-source converter (LCC-CSC) drives, also referred to as load-commutated inverters (LCI), multilevel voltage-source inverter (VSI) drives, and MMC/modular multilevel cascaded converter (MMC/M2LC)-based drives), together with typical rating and voltage ranges and the corresponding semiconductor technologies (thyristor and insulated-gate bipolar transistor (IGBT)). This baseline places the reviewed CVR-reduction topologies within realistic industrial operating envelopes by summarizing typical power and voltage scales, application contexts, and prevailing semiconductor technologies. These system-level attributes can, at a first-order level, shape the practicality of integrating additional power channels or buffering elements in terms of ratings, isolation, and loss and thermal budgets, thereby supporting a more grounded discussion of feasibility and integration considerations.

This paper brings together the different hardware-based contributions that focus on CVR interaction. The remainder of this paper is organised as follows. Section 2 summarises the physical origin of low-frequency power ripple in MMC arms. Section 3 provides a contextual overview of DC–DC MMC topologies with emphasis on capacitor-voltage behaviour and management. Section 4 introduces a systematic classification of hardware-based DC-AC MMC topologies into five groups, denoted A–E: (A) physical power channels, (B) active channel cells with mid-cell connections, (C) hybrid MMC and dc-bus management, (D) SM-level active power decoupling (APD) and phase-level active power filters (APF), and (E) structural or topological changes to the SM architecture. Section 5 synthesises the cross-group comparison and distils the main design trade-offs beyond ripple reduction—including scalability with large N, low-speed or near-zero-frequency operation, EMI/CMV implications, maintainability, modularity, fault tolerance, and cost and industrial feasibility—to formulate application-driven selection guidelines. Section 6 concludes the paper by summarising the main findings and outlining design implications and research directions for hardware-based CVR mitigation in practical MMC platforms.

2. Review of Power Ripple in MMCs

In a balanced three-phase MMC delivering approximately constant DC power (neglecting losses), the sum of the instantaneous powers of the three phases is (approximately) constant, whereas the instantaneous power of each individual phase contains a second-harmonic (2$\omega$) component. These 2$\omega$ oscillations cancel in the three-phase sum, but they cause low-frequency energy pulsations in each arm and in the SM capacitors. For a two-level converter, this ripple component is reflected in the DC bus of the SM resulting in a low-frequency $\left(2\omega \right)$ fluctuation; the fluctuation amplitude strongly depends on the load power, the fundamental frequency, the modulation index, the number of SMs, and the capacitance value [3]. The low speed, high torque region is particularly critical: as the fundamental frequency decreases, the period of the oscillation at $\left(2\omega \right)$ increases and the energy that the capacitors must store increases; this amplifies the voltage fluctuation for a fixed capacitance. Also, unwanted 2nd harmonic circulating currents are generated: although limited by arm reactances, they increase copper losses and thermal stress on semiconductors [4,9,10]. Modulation strategies such as PSC/PD PWM and zero-sequence harmonic injection affect the $i_{cc}$ spectrum and CVR by altering the branch voltage waveform and zero-sequence content; however, such control-based methods do not eliminate the source, but merely redistribute the ripple power or reduce the SM capacitance required to satisfy a given voltage-ripple specification [3,4,5,21].

Two main hardware-based approaches for SM ripple suppresion have been reported in the literature. The first method is based on shifting the power ripple to other components of the MMC circuit. The LF ripple power is transferred to an auxiliary storage or a physical channel. SM-based APD topologies direct the ripple power to an auxiliary capacitor [53]; HF magnetically coupled ‘ripple-power decoupling’ channels established between arm pairs circulate the $2\omega$ component via an isolated path at high frequency [17]. Arm-link structures based on dual active bridge (DAB) and dual half bridge (DHB) placed in the arm also apply the same principle [54].

The second method is based on reducing the source of the ripple. The selection of operating parameters (using a higher modulation index m and injecting a controlled second-harmonic circulating current) with hybrid topologies (HB + FB blends, mid-cell, etc.) improves the arm power profile and limits $2\omega$ circulation, thus reducing SM capacitor-voltage fluctuations [1,14,20].

Increasing the number of SMs is one straightforward way to reduce CVR, because it decreases the voltage step in each SM, but it also increases the number of semiconductors, gate drivers, and the overall system complexity [3]. In practice, mitigating CVR and circulating currents requires making joint decisions on several interacting design parameters, including SM count, arm inductance, CMV-management schemes, and auxiliary hardware that processes low-frequency energy; these parameters must be chosen together so that the converter simultaneously meets the required CVR level, CMV/EMI limits, and acceptable hardware cost and complexity [1,10,14,15,17,53,54,55,56]. While this review is primarily concerned with DC–AC MMC operation, capacitor-voltage behaviour in DC–DC MMC topologies is shaped by different operating mechanisms and balancing requirements; these are therefore discussed separately in the following contextual overview section.

3. DC–DC MMC Topologies: Contextual Overview

The primary focus of this review is the reduction of SM capacitor-voltage ripple in DC–AC MMCs, particularly the ripple–power interaction that becomes pronounced at low speeds and low output frequencies, using hardware-based methods. However, for HVDC and DC-grid interfaces and applications requiring power transfer between different DC voltage levels, DC-DC MMC topologies, where the MMC structure is employed for DC–DC conversion, also represent an important parallel research line. These studies commonly address issues such as arm and submodule energy drift under DC operation, sustained capacitor-voltage sharing, and, in some cases, mitigation of output ripple and filtering requirements.

This section, from a hardware perspective, compiles and summarises representative DC-MMC topologies relevant to capacitor-voltage management and ripple-related performance, using a single overview table. The dominant components of capacitor-voltage ripple in MMC systems depend on the operating mode. In DC–AC operation, the sinusoidal output voltage and current, together with the associated arm-energy exchange, typically introduce a prominent second-harmonic ($2\omega$) component in the SM capacitor voltage. At low frequency and low speed, the longer energy-oscillation period can make the capacitor charge–discharge swing more pronounced, leading to increased ripple. By contrast, in DC-DC MMC operation, a fixed AC reference and the corresponding $2\omega$ dominance are not generally applicable. Instead, capacitor-voltage behaviour is often shaped by balancing and equalisation actions introduced to prevent energy drift, the switching pattern, and topology-specific internal energy circulation. Consequently, the metrics reported in DC-MMC studies, for example inter-cell voltage deviation, equalisation dynamics, and output or DC-link ripple, are not always directly comparable to the low-frequency SM ripple metrics used for DC–AC MMCs. For this reason, the DC-DC MMC studies discussed here are not directly included in the A–E classification.

Isolated, HF magnetic-path concepts are commonly used to stabilise capacitor-voltage sharing while interconnecting two DC voltage levels through a transformer-like architecture. In [57], capacitor-voltage management is pursued via a self-balancing mechanism based on diode–inductor clamping circuits, within a DC-transformer configuration in which two diode-clamped MMCs are linked through a medium-frequency transformer; the emphasis is on simplifying the balancing mechanism and reducing sensing and controller burden. In [58], isolation transformer-based flyback energy-equalisation modules are inserted between upper–lower SM pairs, effectively moving the equalisation action into a dedicated physical channel. This improves voltage-sharing robustness during DC operation, but increases hardware and integration cost due to additional magnetics and isolation.

Hybrid and reconfiguration-based energy equalisation approaches enable controlled energy transfer between arms by introducing additional operating modes or extra HV switching elements. In [59], energy drift is suppressed using a two-stage structure and periodic arm-interchange (swapping) operation; while this provides strong freedom for balancing, system complexity increases markedly due to the two-stage architecture and multiple operating modes. In [60], a more minimal hardware addition is adopted by inserting a single bidirectional HV valve into a conventional HB-SM MMC and performing energy equalisation by paralleling the arms at specific intervals (see Figure 2); the objective of keeping capacitor voltages within a bounded ripple window is emphasised, but current stresses during equalisation and HV-valve sizing become critical design considerations.

In transformerless DC–DC MMCs, balancing actions can introduce ripple components that would otherwise be mitigated using bulky passive LC filters. In [61], a middle-cell addition is proposed so that balancing-related alternating components are managed within the phase arms, while active compensation of unwanted components at the output DC side is targeted. In this line of work, ripple reduction is commonly reported as a system-level outcome enabled by active shaping and compensation, rather than being framed exclusively as direct SM capacitor-ripple suppression.

Without isolation, ripple or balance improvement can also be pursued through structural revisions at the SM or arm level, or through magnetic cancellation mechanisms. In [62], as shown in Figure 3, the SM structure is revised to form power and auxiliary balancing branches sharing the same capacitor, enabling DC-control-based regulation while reducing capacitor-voltage fluctuation over a wide output range. In [63], DC-link capacitor ripple is reduced by cancelling current ripple using H-bridge-based modular blocks and mutually coupled inductors; while the approach is strong in terms of scalability (module stacking), reported outcomes often emphasise DC-link and current ripple behaviour, so a direct one-to-one comparison with SM-level ripple is not always straightforward.

Table 2. Comparison of DC-DC MMC.

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
Diode-clamped DC transformer (MFT + clamp) [57]	66.7% (s)/90.0% (e)	High	Diode+inductor clamping network + MFT; self-balancing path	High	Medium	“DC transformer” line; main emphasis on self-balancing and reduced sensing burden.
Flyback-EEM energy equalisation (isolation transformer) [58]	82.8% (est.) (s)/ N/A (e)	Very High	Flyback EEM modules with isolation transformer (energy equalisation path)	Very High	Medium	Simplified control with 50% duty EEM; added cost/volume due to isolation and magnetic integration.
Arm interchange (two-stage) [59]	60% (est.) (s)/ 50% (est.) (e)	Medium-High	Two-stage structure + arm-interchange operation	Medium-High	Medium-High	Suppresses energy drift; operating modes and coordination are critical.
Single bidirectional HV valve [60]	93.7% (est.) (s)/ 26.7% (est.) (e)	Medium–High	Single bidirectional HV valve + periodic paralleling	Medium–High	Medium–High	Emphasises soft-switching; current stresses during equalisation instants.
Middle cells (active filtering) [61]	64.1% (est.) (s)/N/A (e)	Medium	Middle-cell added + APF-like control	Medium	Medium	Reduces bulky LC filter; alternative component/energy management for balancing.
4-terminal SM (power + aux balance branch) [62]	61.8% (est.) (s)/ 60.1% (e)	High	In-SM power branch + auxiliary balancing branch	Medium–High	Medium	DC control; wide $V_{\mathrm{out}}$ range; balancing branch + small inductors.
H-bridge + mutually coupled inductors [63]	93.3% (est.) (s)/ 66.7% (est.) (e)	Medium–High	H-bridge + mutually coupled inductors	Medium	Medium	DC-link ripple emphasis; level scalability via stacking modules.

provides a comparative overview of hardware-based approaches in the DC–DC MMC literature, summarising the reported ripple-reduction performance and the associated hardware and control requirements. The methods are presented side by side using common criteria, including ripple reduction, hardware and control complexity, additional components and cost, and brief explanatory notes. This presentation helps make the main trade-offs between reported ripple performance and practical applicability more transparent, while preserving the contextual differences across the reviewed studies.

4. Hardware-Based Reduction of SM Capacitor Ripple in DC-AC MMCs: Classification and Impact–Cost Assessment

In this section, the proposed A–E classification is applied to DC–AC MMCs (motor-drive and grid-interface operation), where the dominant low-frequency SM capacitor-voltage ripple is primarily linked to the arm-energy oscillation at the fundamental and its second harmonic components. The methods are grouped according to the physical mechanism by which the ripple power is processed and the additional hardware pathway introduced to redistribute, buffer, or decouple that energy. Group A covers approaches that create explicit physical power channels, typically via high-frequency magnetic links, to transfer ripple power between arms or phases. Group B includes transformerless and topology-level auxiliary channels (e.g., middle-cell or active bridging structures) that shape the internal energy exchange without galvanic isolation. Group C comprises hybrid and reconfigurable MMC variants that exploit additional switching states or mixed submodule types to manage arm-energy imbalance under low-speed conditions. Group D collects methods that employ dedicated energy-storage interfaces to buffer ripple energy, while Group E captures architectural and design-oriented solutions (e.g., structural modifications and selection guidelines) that mitigate ripple through system-level reallocation of stored energy and practical design trade-offs. In the following subsections, these groups are compared not only in terms of ripple mitigation effectiveness, but also with respect to incremental hardware burden, control complexity, and impact–cost considerations.

4.1. Group A: Physical Power Channels (HF Magnetic Path)

The addition of physical power components typically results in significant suppression of the ripple while maintaining stability at low speeds [17,54,64]. The trade-off is increased hardware complexity and cost due to the need for high-frequency transformers and additional power bridges, as well as the need for EMI-aware layout in the design. The approach has been implemented in several variants such as DAB- or three-port-based links, inter-phase high-frequency power-sharing channels, and wireless high-frequency magnetic coupling [17,54,65,66].

Topologies that transmit low-frequency ripple power at $\omega$ or $2\omega$ via high-frequency magnetic couplings operate on the same principle: the SMs of neighbouring arms at the same level are laterally connected via HF transformer-based DHB/DAB intermediate converters, and ripple power is compensated instantaneously between phases. In [17], DHB converter based ripple-power decoupling channels established between the three phases simultaneously separate the Differential-Mode (DM) and Common-Mode (CM) components as illustrated in Figure 4. Thus, the SM capacitor voltage ripple is substantially reduced while maintaining full torque at low speed.

In [67], the MMC-PET hybrid, the $2\omega$ circulating current injection on the MMC side suppresses CVR, while the DAB phase shift transfers the fundamental ripple power to the HF link; the architecture is summarised in Figure 5—‘Upper-lower arm coupled MMC–PET’.

In [54], an intra-arm variant is implemented in Arm-Link Enhanced (ALE) MMC as shown in Figure 6. The upper and lower arm SMs are connected via a DAB. Since the DAB current depends solely on the arm modulation, SM voltage measurement and sequencing are not required, the capacitor is reduced, and the DAB operates continuously in Zero-Voltage Switching (ZVS).

Similar to ALE-MMC [54], an isolated DHB-based link [68] is inserted between each pair of SMs in the upper and lower arm, as indicated in Figure 7. The fundamental component of the power is transferred to the opposite arm with phase-shifted control, reducing current stress and $C_{SM}$ without requiring HF common-mode injection. Briefly [17], the DM and CM components are jointly separated using the inter-phase DHB chain as shown in Figure 4; [54] uses DAB between the upper and lower arms of the same phase to enable intra-arm power transfer without SM voltage measurement (Figure 6); reference [68] proposes a DHB power link between the upper and lower arm pair, specifically carrying the fundamental $\left(\omega \right)$ DM component, as shown in Figure 7; reference [65] brings the three phases together in a three-port connection and uses the principle that the sum of the instantaneous powers is 0 to naturally cancel the components at $\omega$ and $2\omega$ within the link (Figure 8).

The three-port connection at the phase level is addressed in [65]: single-phase three-winding transformers at the same level are connected laterally (Figure 8), ensuring that the sum of the active powers are zero within the link, cancelling the components at $\omega$ and $2\omega$ internally.

Low frequency components can also be suppressed by directing the ripple current through isolated HF channels to the target arm or phase. For example, a DHB chain placed between the phases simultaneously separates differential and common-mode components [17]. In ALE-MMC, the opposing ripple SMs in the upper and lower branches of the same phase are connected via DAB; since the DAB current depends only on the branch modulation, it does not require SM voltage measurement and provides a wide ZVS range [54]. The fundamental $\left(1\omega \right)$ component is transferred to the opposite arm via the DHB power channel inserted between each upper–lower SM pair; this reduces current stress and the required SM capacitance without the need for HF common-mode injection [68]. In open-end stator winding machine drives, in the Dual-MMC configuration, HF connections are not within a single MMC but between the mutual SMs of two separate MMCs; power ripple sharing occurs between converters [69]. The reported front-to-front DHB configuration for six-phase drives indicates a fluctuation reduction of approximately 42–84% in the $50\to 1$ Hz range [70].

A different option is to export the fluctuating arm power to an external energy storage system, as in the MMC-integrated battery topology proposed in [71]. In this approach, a dedicated battery pack belonging to a modular BESS is connected to the upper and lower arms of each phase leg through an isolated three-port DC–DC converter. By actively exchanging power between the two arms and the battery, the arm powers are balanced, the fundamental circulating current is cancelled, and the three-port converter processes the fundamental power oscillation as a controlled power channel. As a result, the required arm capacitance $C_{\mathrm{SM}}$ can be reduced even at low speeds while maintaining a narrow SM-CVR; the average power-flow duty ratio D and the oscillation phase shift $\mathrm{\Phi }$ are controlled independently.

Coupling SMs of the same level with a lateral HF connection is also an effective strategy. In the switched-capacitor HF-link (SC-HFL) MMC, this lateral link is realised by a switched-capacitor HF network across the three phases, implementing natural ripple-power decoupling without additional closed-loop control [72].

Resonant magnetic link-based approaches switch the ripple power within the link without requiring large LF storage. In the resonant push-pull converter – high-frequency Link (RP2C-HFL), the HF link behaves like a low-impedance, constant-ratio source; thanks to three-phase symmetry, fluctuating power is automatically eliminated and the $2\omega$ circulation disappears [73]. At the phase level, the three-port half-bridge (THB) + three-winding HFT connection implements the flux cancellation principle $(pa+pb+pc\approx 0)$ in hardware, enabling $1\omega /2\omega$ components to circulate within the link instead of SM capacitors [65]. Sliding-mode-based input-impedance shaping draws the remaining LF ripple into the HFT path and balances the operating point, targeting a narrow, weak-speed-dependent SM-CVR (Figure 9 shows only the new MMC topology; the control action is detailed in [74]). In the wireless counterpart, the THB ports of the three neighbouring SMs in each arm are magnetically coupled to the wireless three-winding HFT; using the same flux cancellation principle, the LF DM/CM components are damped within the HF link without loading the SM capacitors, reducing the need for large LF capacitors [66].

In the battery energy storage system approach (MMC-BESS) [71], each battery pack is interfaced to a pair of SMs (upper–lower) via an isolated three-port DC-DC, enabling ripple suppression and module-level SoH (State of Health)/SoC (State of Charge) management. At the system level, three-port interfaces can also realise a common low-voltage DC bus for energy sharing across modules, as exemplified by bidirectional three-port converter (BTPC) designs in [64].

For comparison, Refs. [17,54,65,68,71,73] mostly redistribute only ripple power within a single MMC using local HF channels; they do not provide a system-wide common energy pool and do not enable centralised control of power flow separated by duty ratio and phase shift (D–$\varphi$). Therefore, local HF-channel topologies do not provide a high-level, centralised power distribution infrastructure; instead, power flow is largely a local and passive redistribution with only limited adjustments.

Table 3. Technical Parameters, Operating Conditions, and Link Specifications of Active Decoupling Units.

Topological Structure	Scale	Power/Voltage	Operating Current	Switch. Freq.	Capacitance	Link Specifications
MMC + Ripple-Power Decoupling channels [17]	Sim	20 MW/25 kV	500 A (Rated arm current)	2 kHz (MMC)	3 mF	1:1 Unity/Leakage Ind.
	Exp	6 kW/600 V	16.7 A (Rated AC)	10 kHz (DHB)	1.5 mF	1:1 Unity/1.2 T Core Transformer
ALE-MMC: Transfer ripple power via arm-link using DAB [54]	Sim	25 kVA/500 V	25 A (Output)	10 kHz (MMC)/50 kHz (DAB)	220 $\mathsf{\mu }$F	1:1 DAB/$L_s=6.8\mathsf{\mu }$H
	Exp	1.1 kW/70 V	17 A (Output)	10 kHz (MMC)/100 kHz (DAB)	270 $\mathsf{\mu }$F	Si MOSFETs/DAB $f_s=100$ kHz
Power balancing between SM ports via LVDC common bus using BTPC [64]	Sim	40 kW/10 kV	10 A (Rated arm current)	20 kHz (BTPC)	3 mF	Interleaved BTPC/1:1 HF Transformer
	Exp	0.4 kW/50 V	4 A (Battery)	20 kHz (BTPC)	220 $\mathsf{\mu }$F	1:1 Transformer/40 $\mathsf{\mu }$H L
Three-port power channels (HF sharing among phases) [65]	Sim	1.08 MVA/8 kV	150 A (Rated arm)	1 kHz (3-port HF link)	2 mF	1:1:1 Three-winding Isolation Transformer
	Exp	4.87 kVA/600 V	7.4 A (Rated stator)	2 kHz (3-port HF link)	500 $\mathsf{\mu }$F	1:1:1 Three-port Transformer Link
Wireless magnetic power decoupling (THB + 3-winding HFT) [66]	Sim	2.4 MW/2.5 kV	362 A (Est. RMS Load)	5 kHz (THB)	15 $\mathsf{\mu }$F	1:1:1 (Wireless HFT)
	Exp	1.2 kW/260 V	4.6 A (Est. RMS Load)	15 kHz (THB)	15 $\mathsf{\mu }$F	1:1:1/30 $\mathsf{\mu }$H (Leak.)
MMC-PET: ripple transfer via upper–lower arm coupling + 2f circulating current + DAB phase shift [67]	Sim	1.5 MW/2 kV	86.6 A (Est. AC RMS)	1 kHz (MMC)/5 kHz (DAB)	600 $\mathsf{\mu }$F	2.67:1/0.5 mH (DAB Lk)
	Exp	N/R	N/R	N/R	N/R	N/R
Intra-arm power channels (between upper–lower, with isolation transformer) [68]	Sim	3 kW/600 V	∼6 A (AC RMS, est.)	1 kHz (DHB)	500 $\mathsf{\mu }$F	DHB + 1:1 Isolated Transf.
	Exp	3 kW/300 V	∼6 A (AC RMS, est.)	1 kHz (DHB)	500 $\mathsf{\mu }$F	0.4 mH Leakage Ind. (0.2 + 0.2)
Dual-MMC + HF magnetic links (open-end) [69]	Sim	10 MW/12.5 kV	655 A (Rated)	2 kHz (MMC)/10 kHz (DHB)	1 mF	1:1 Transf./Lleak (DHB)
	Exp	4 kW/300 V	9.5 A (Rated)	2 kHz (MMC)/10 kHz (DHB)	1.1 mF	1:1 Transf./100 $\mathsf{\mu }$H Aux. L, 1.2 T Core
Isolated energy balancing modules (DHB-based) [70]	Sim	20 MW/25 kV	655 A (Rated)	2 kHz (MMC)/10 kHz (DHB)	2 mF	Isolated DHB Modules (Energy-Balancing)
	Exp	4 kW/300 V	10 A (Rated)	2 kHz(MMC)/10 kHz (DHB)	1.1 mF	Isolated DC-DC (DHB), 1:1 Transf.
MMC-BESS (battery-SM integration via isolated 3-port DC-DC) [71]	Sim	125 kW/1.25 kV	346 A (Est. Line RMS)	5 kHz (isolated 3-port conv.)	3 mF	1:1:1/60 $\mathsf{\mu }$H (Leak.)
	Exp	∼0.3 kW/30 V	∼6 A (Arm RMS)	5 kHz (isolated 3-port conv.)	3 mF	1:1:0.6/42 $\mathsf{\mu }$H (Leak.)
HF-link SC-MMC (natural ripple-power decoupling) [72]	Sim	1.2 MW/12 kV	– (not explicitly given)	2 kHz (MMC)/ 5 kHz (SC-HFL)	10 $\mathsf{\mu }$F	4:4:4:1/9 $\mathsf{\mu }$H Trans.
	Exp	1.2 kW/240 V	5.6 A (AC current)	2 kHz (MMC)/20 kHz (SC-HFL)	9.4 $\mathsf{\mu }$F	2:2:2:1/4.3 $\mathsf{\mu }$H Trans.
Triple-Port SST (MMC + RP2C-HFL; free-coupling) [73]	Sim	8 MW/12 kV	500 A (Est. DC @ MVDC)	1 kHz (MMC)/20 kHz (RP2C)	120 $\mathsf{\mu }$F	4:1:1/6.53 $\mathsf{\mu }$H/9.69 $\mathsf{\mu }$F
	Exp	2.4 kW/200 V	12 A (Est. DC @ MVDC)	2 kHz (MMC)/20 kHz (RP2C)	18.8 $\mathsf{\mu }$F	2:1:1/9.01 $\mathsf{\mu }$H/6.80 $\mathsf{\mu }$F
Capacitor-less MMC: HFT-based PDC + Sliding Mode Control [74]	Sim	1 MW/2.5 kV	419 A (Est. RMS Load)	15 kHz (THB)	15 $\mathsf{\mu }$F	1:1:1 (HFT)
	Exp	1.3 kW/260 V	4.8 A (Est. RMS Load)	15 kHz (THB)	15 $\mathsf{\mu }$F	1:1:1/100 $\mathsf{\mu }$H (Leak.)

comprehensively compares the practical applicability of active power decoupling/balancing units for reducing low-frequency submodule capacitor-voltage ripple (CVR) in MMCs, considering scale (simulation/experiment), power–voltage level, current stress, switching frequency, capacitance requirement, and link-design axes reported in the literature. In this context, proposed topologies for high-power MV drive scales (e.g., MW–kV range) are presented alongside applications validated through experimental prototypes at the kW level, highlighting the transition between conceptual suitability and hardware feasibility. The data show that most active decoupling channels exhibit two distinct switching layers: the MMC’s PWM carrier (typically in the kHz range) and a corresponding higher (or separate) switching frequency defined for the isolated DC–DC power channel (e.g., DHB/DAB, three-port converters, or SC-HFL networks). This separation enables low-frequency ripple power to be routed through an alternate path outside the main energy-transfer route, while also making link design (leakage inductance, conversion ratio, and magnetic-core stress) a determining engineering variable. Indeed, Table 3 indicates that link characteristics are commonly reported via a 1:1 conversion ratio, specified leakage/auxiliary inductances, and, in some studies, multi-winding isolation transformers. The capacitance column further highlights a wide design range from mF to $\mathsf{\mu }$F depending on the system scale and the power-decoupling architecture: while some solutions enable capacitorless/low-capacitor operation using smaller film capacitors, others indicate that a certain capacitance remains critical for buffering ripple power.

These technical parameters are more meaningful when read in conjunction with the magnitudes of CVR suppression delivered by the corresponding methods. Accordingly, the relevant performance outputs for Group A are summarised in

Table 4. Comparison of Group A approaches (HF magnetic physical power channels).

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
MMC + Ripple-Power Decoupling channels [17]	94.4% (s)/75% (e) at 5 Hz	High	Additional energy channels/HF components	Medium–High	Medium–High	Directs ripple power between arms; strong at low speed.
ALE-MMC: Transfer ripple power via arm-link using DAB [54]	>99% (s) at 0 Hz/90–95% (e) at 10 Hz	High	DAB(s), HF transformers, arm-link components	High	Medium	Eliminates SM voltage measurements; operation from zero to high frequency in LV drives.
Power balancing between SM ports via LVDC common bus using BTPC [64]	90% (s)/85% (e) at 50 Hz	High	Interleaved buck-boost (2 branches) + DAB + HF transformer	High	Medium–High	Not drive-focused; second-life BESS integration; maintains stability under mismatched battery power; no inter-module communication required.
Three-port power channels (HF sharing among phases) [65]	90.5% (s)/92.3% (e) at 20 Hz	High	3-port channels/HF components	Medium–High	Medium	Uses the principle that the three-phase total power equals zero; significantly reduces SM voltage ripples at low speed.
Wireless magnetic power decoupling (THB + wireless 3-winding HFT) [66]	99.75% cap. red. (s)/84.4% ripple red. (e) at 60 Hz	High	THB port + wireless HFT + small HF capacitors	High	Medium	Does not require LF SM capacitors; uses small HF film capacitors; inter-phase magnetic cancellation.
MMC-PET: ripple transfer via upper–lower arm coupling + 2f circulating current + DAB phase shift [67]	95.7% (s) at 50 Hz/N/A (e)	High	MMC-PET + DAB isolation stage + coupling link	High	High	Effective under faults; $I_{sec}$ $\pm 90$ A limit; LVDC ripple $\pm 5$ → $\pm 1$ V.
Intra-arm power channels (between upper–lower, with isolation transformer) [68]	95% (s) at 10 Hz/∼80% (e) at 5 Hz	High	Power channel + isolation transformer	High	Medium	Fundamental component damping within the arm; targeted at MV drives; 2nd-order harmonics may remain in experiments.
Dual-MMC + HF magnetic links (open-end) [69]	90% (s)/66% (e) at 5 Hz	High	HF transformers + DHB	High	Medium–High	Requires open-end stator machine; bidirectional energy exchange between adjacent arms; eliminates ripple independent of frequency.
Isolated energy balancing modules (DHB-based) [70]	92.4% (s)/84% (e) at 1 Hz	Very High	Isolated DC-DC + HF transformers	High	Medium–High	Specifically designed for symmetrical 6-phase machines; achieves ripple-power decoupling between adjacent sub-modules.
MMC-BESS (battery–SM integration via isolated 3-port DC-DC) [71]	74–86% (s)/∼89% (e) at 50 Hz	High	3-port DC-DC + battery	Medium–High	Medium–High	Upper–lower arm power is balanced via 3-port converters; eliminates fundamental ripple and 2nd-harmonic circulation.
HF-link SC-MMC (natural ripple-power decoupling) [72]	81.6% (s)/98.9% (e) at 50 Hz	High	HF link + switched capacitor network	Medium–High	Medium	Natural ripple-power decoupling and self-equalization without closed-loop control; uses 20 kHz HF-link in experiments.
Triple-Port SST (MMC + RP2C-HFL; free-coupling) [73]	88.5% (s)/>95.1% (e) at 50 Hz	High	RP2C-HFL units (multi-port)	Medium–High	Medium	Natural suppression of SM ripple/imbalance; no 2nd-harmonic circulation.
Capacitor-less MMC: HFT-based PDC + Sliding Mode (PDC: Power-Decoupling Converter) [74]	88% (s)/85% (e) at 50 Hz	High	3-winding HF transformer + three-port bridge	High	Medium–High	Frequency-independent rejection; inter-phase flux cancellation.

as ripple-reduction percentages at the studied output frequency ($f_{\mathrm{out}}$), alongside the associated hardware complexity, component set, additional cost, control complexity, and salient implementation notes. The results in Table 4 indicate that, experimentally, suppression of approximately 66–95% can be achieved under low-speed/low-frequency conditions (1–10 Hz), whereas around 50–60 Hz most approaches report 74–90%+ suppression; with appropriate design and scaling, some HF-link-based channels can reach the order of 98–99% experimentally. In this review, the reported ripple-reduction percentages are obtained by comparing the $\pm \%$ ripple level of the SM capacitor voltage in the conventional MMC against the $\pm \%$ ripple level achieved after applying the proposed method at the same operating point. Here, the $\pm \%$ ripple level refers to the peak-to-peak capacitor-voltage ripple normalised to the nominal SM capacitor voltage $V_{c,\mathrm{avg}}$. Typically, $V_{c,\mathrm{avg}}\approx V_{dc}/N$ for an arm with N submodules. Accordingly, reported ripple levels are presented in a scale-independent form, enabling a consistent comparison across studies operating at different DC-link voltages and prototype ratings.

$${\displaystyle \frac{\Delta V_{C,\%}^{\mathrm{conv}}-\Delta V_{C,\%}^{\mathrm{prop}}}{\Delta V_{C,\%}^{\mathrm{conv}}}}\times 100$$

(1)

The reported values are typically expressed as the conv→prop improvement defined in Equation (1), whereby the reduction in ripple magnitude associated with transitioning from the conventional to the proposed configuration is quantified in a consistent manner. The same definition has been adopted for the ripple-reduction figures reported in the tables for the other groups, where ripple levels are available. Furthermore, in studies where the outcome is reported indirectly (e.g., via capacitance reduction rather than $V_{pp}$ or % ripple), cases are observed in which an experimental ripple reduction of ∼$84\%$ is reported alongside a capacitance reduction reaching up to 99.7%, indicating that different metrics can reflect the same physical goal (CVR reduction) from different perspectives.

4.2. Group B: Active Channel (Transformerless, Mid-Cell, etc.)

A second group of methods for reducing SM capacitor ripple aims at bringing the common-mode voltage (CMV) close to zero by redistributing arm power via the middle cell. This preserves the achievable torque at low frequency and down to 0 Hz. Also, reduction of CMV significantly decreases bearing current and EMI risk. This group necessitates additional semiconductor elements in the architecture, protection, and high-level control coordination.

Group B methods reduce voltage fluctuations across SM capacitors by redistributing low-frequency power fluctuations (at frequencies $\omega$ and $2\omega )$ between arms and phases using transformerless active bridges. In cross/midpoint/star-based configurations, bridging the upper–lower arms or phase midpoints with transformerless active channels is fundamental. Active cross-connected MMC, as shown in Figure 10, eliminates the upper–lower arm power imbalance within a phase by circulating a HF square-wave current through the active cross-arm formed by series-connected HB-SMs [55].

Similarly, Star-Channel (StCh-MMC) (in Figure 11) enables inter-phase power sharing through star-channel branches and does not require CMV injection [15].

The middle-cell approach (MC, see Figure 12) [75] establishes an additional power exchange path between the upper arm, lower arm, and AC terminals via a three-terminal intermediate cell. The modified middle-cell structure in [76] specifically reduces the $2\omega$ component via a load-connected middle circuit. In the transformerless HF power-channel topology with a centre cell [77] the load is connected through the centre circuit; even while balancing arm powers with high-frequency switching-based power flow, the number of components is reduced compared to other centre-cell derivatives. The distinguishing feature of this subset is that the “direct” (non-isolated) bridges established at the phase level reduce both ripple and CMV in most structures.

Instead of using phase- or arm-level bridges, SM-level topologies rely on switching channels established between the upper and lower SM pairs at the same level. With the bidirectional-switching channel (BSC) [78], the SM capacitor is connected alternately to one of two branches. Because the half-cycles of the oppositely signalled branch currents are distributed to the same capacitor, the fundamental-frequency ripple is reduced. The reversed-PWM (rPWM) channel together with a clamp capacitor $C_{\mathrm{clamp}}$ [79] directly damps the oppositely phased capacitor ripples in the channel; the reported results show an ≈78% ripple reduction and a decrease of the total capacitance requirement to ≈12% of its original value. In this subgroup, no energy is exchanged with external magnetic components; capacitor energy is balanced locally via charge sharing and reconnection.

Arm-level midpoint schemes [15,55,75,76,77] redirect the low-frequency (LF) power imbalance via active bridging at the arm level, thereby reducing SM capacitor-voltage ripple and often the common-mode voltage (CMV), whereas SM-level switching-channel schemes [78,79] attenuate the fundamental-frequency ($\omega$) ripple component by enabling local charge transfer between the corresponding upper- and lower-arm SM capacitors, with further improvement when a clamp capacitor $C_{\mathrm{clamp}}$ is added. Neither approach requires an isolated high-frequency transformer (HFT), resulting in simpler hardware. However, control and protection requirements demand careful attention. The differences and their practical implications are summarised in

Table 5. Comparison of Group B approaches (transformerless active channel).

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
AC-MMC: Physical power transfer between upper–lower arms via an active cross-linked arm (HB-SM string) [55]	75% (s)/90% (e) at 5 Hz	High	HB-SM string for the cross-link arm; additional sensors	Medium–High	High	No CMV; operation across the full speed range; validated by a 4.16 kV–1 MW model and experimental prototype.
Star-Channel MMC (CMV-free) [15]	91% (s)/93% (e) at 6 Hz	Medium	Star-channel arms (typically FB-SMs)	Medium	Medium	Zero/low fundamental-frequency operation without injecting CMV.
Power exchange via a three-terminal middle cell (transformerless channel) [75]	49.0% (s)/49.0% (e) at 20 Hz	Medium–High	Middle cell + additional capacitors and switches	Medium	Medium–High	Cancels CMV injection with reverse voltage; stable at zero/low frequency.
Modified Middleware Submodule MMC (diode-assisted middle SM; HF modulation) [76]	82.9% (s)/82.9% (e) at 5 Hz	Low–Medium	SM regulated with a diode at the middle position; no external power channel	Low	Medium (PI + PSPWM; middle SMs operate at HF)	Counter-phase to $2\omega$ ripple; no added CMV; simulation + HIL; SM $V_c\approx \pm 10{\mathrm{V}}_{pk}(\sim 20{\mathrm{V}}_{pp})$ at 5 Hz.
Transformerless HF power channel with a middle cell [77]	60% (s)/60% (e) at 3 Hz	Medium–High	Middle cell with 2 IGBTs + 2 capacitors	Medium	Medium	Eliminates CMV; component count lower than classical middle-cell approaches.
Bidirectional switching channel: shared use of capacitors between upper–lower arms (threshold-based) [78]	88.6% (s)/49.3% (e) at 5 Hz	Medium–High	Bidirectional channel switches; repositioned SM capacitors	Medium	Medium	Suppresses SM capacitor ripple at low speed without creating CMV; focused on pumped-storage drives.
Reverse-PWM switching channel + clamp capacitor (between upper–lower SMs) [79]	53.4% (s)/– (e) at 50 Hz	Medium	Switching channel + clamp capacitor	Medium	Medium	Equivalent capacitance can be reduced to ∼$12\%$ (simulation).

, noting ripple reduction, hardware, control complexity, and additional cost.

4.3. Group C: Hybrid-MMC (DC-Bus Series Switch, HB + FB and DC-Link Management)

Group C aims to reduce SM capacitor-voltage ripple by reshaping the submodule energy profile in hybrid MMC topologies using a mix of HB + FB submodules, DC-series switches, or variable DC-bus configurations; some variants also reduce CMV. These schemes can achieve significant CVR reduction without substantial additional hardware and can lower the required capacitance by exploiting the additional degrees of freedom introduced by the hybrid cells (such as extra switching states and insertion possibilities) to shape internal energy exchange and attenuate the dominant low-frequency energy oscillation. However, the available timing margins and feasible operating windows can be relatively narrow and more sensitive to modulation errors and parameter variations; as a result, DC-fault behaviour and protection coordination become more complex and typically require explicit definition of fault-detection criteria, blocking and restart sequences, energy dissipation paths, and semiconductor ratings.

One approach to reducing CVR at low frequencies is to shape the DC-link voltage so that the average (DC) component of the arm voltages is reduced; this, in turn, attenuates the dominant arm-energy oscillation at the fundamental frequency $\omega$ under low-speed operation. In [1], a series switch is placed between the DC source and the MMC; high-frequency on-off operation or the switch lowers the average DC level ‘seen’ by the converter, and the SM energy oscillation is significantly reduced (see Figure 13—‘Traditional MMC with DC-link series switch’). Furthermore, ref. [80] deliberately lowers the average capacitor voltage of the SM in the series switch hybrid MMC, thereby increasing the relative CVR tolerance for the same absolute ripple.

Reference [81] combines this approach with lateral HF coupling: while the series switch reduces the average arm voltage, the added HFT/HFL interconnection provides a high-frequency magnetic link so that a large portion of the SM fluctuation current is diverted into the coupling path (where the three-phase components cancel by superposition) rather than flowing into the SM capacitors. The arm-interchange approach in [82] converts the DC-bus to a square wave at a specific interchange frequency using an integrated gate-commutated thyristor (IGCT)-based H-bridge at the front; energy exchange between arms is performed using the negative, zero, and positive states of the FB-SM-MMC at the rear, keeping CVR balanced down to 0 Hz. In [83], the input 12/24-pulse rectifier is reconfigured as a function of speed; thus, the observed average DC level scales with operation and CVR decreases without injecting circulating current.

The second approach is to reshape the energy profile with hybrid phase-leg architectures using modulation and the negative-voltage capability provided by the hybrid submodules. In [84], a mix of HB-SMs and FB-SMs increases the modulation index with third harmonic voltage injection and suppresses the power ripple at $2\omega$ with second-harmonic circulating-current injection (SCCI); the total capacitance decreases to ≈50% of the value required without the hybrid phase-leg. A typical layout of the mixed HB + FB arrangement is shown in Figure 14. In [85], the $V_c$ state of selected FB-SMs and selection and sorting algorithms limit the SM energy oscillation. The authors of [86] have analytically derived the $CVR-m$ relationship under overmodulation conditions and provided the optimal m.

Reference [87] creates an asymmetric hybrid phase-leg using FB wave-shaping cell (WSC) + direction switch (DS) in two phases and HB-WSC in the third phase; thanks to the half-period time-sharing of the DSs and the branch voltage wave-shaping of the WSCs, the low-frequency component of the branch power is redistributed and the peak-to-peak value $(\Delta E)$ of the SM energy oscillation is reduced. As a result, the required total capacitance and arm inductance can be reduced; DC fault blocking capability is maintained thanks to the presence of the FB path. Furthermore, ‘Hybrid MMC using FB-SMs on the AC side’, as indicated in Figure 15, represents the approach that reduces CVR by redistributing the arm power spectrum at high frequency with FB-SMs added on the AC side that inject high-frequency power [88].

A third approach is to attenuate ripple at its source through storage/PET integration. In the MMC-integrated composite energy storage (ICES) concept, batteries and supercapacitors are integrated into different phase arms of the MMC via DC–DC converters; low-frequency SM capacitor-voltage ripple can be suppressed under low-speed, high-torque operating conditions, the MV dc bus is regulated by a dedicated dc-link voltage control loop, and the impact of pulsed loads on the integrated power system (IPS) is mitigated [89]. In the mid-cell ‘modified MMC’ structure, the third-harmonic voltage injection selective (THVI)/harmonic current injection (SHCI) combination provides independent power degrees of freedom in the arm powers, enabling elimination of the dominant fundamental component and thereby reducing SM capacitor-voltage ripple; the mid-cell actively compensates for the CMV that THVI may generate [90]. Reference [91] presents an integrated MMC-power flow controller (PFC) approach for traction systems with asymmetric energy storage: batteries and supercapacitors are connected asymmetrically between upper and lower arms; power factor (PF) and voltage imbalance partial compensation is performed with hierarchical control and circulating-current suppression control (CCSC), branch currents and CVR decrease; HIL tests report RMS current $\approx 10\%$, CVR $\approx 30\%$, and field data report $\approx 19\%$ operational cost savings.

Those managing the DC-link and energy storage [1,80,83,89] (and in hybrid form [81]): the average DC level and power flow scales according to operating conditions via a series DC switch with step-down rectifier or integrated composite storage with bidirectional DC-DC; basic DC energy components are reduced → SM-CVR decreases even at low (near-0-Hz) frequencies. In MVDC IPS, it regulates the busbar with decoupled control and mitigates the pulsed load effect [89].

HB + FB hybrid phase-legs [84,85,86,87]: reshape the energy profile with negative voltage conditions, over-modulation, and selective $2\omega$ circulating-current injection degrees of freedom; Ref. [88] adjusts the arm power spectrum without distorting the output waveform, reducing CVR and CMV; arm-interchange [82] limits LF ripple by time-sharing of the DC bus and branch state changes; mid-cell + harmonic injection [90] reduces arm power components at source with 3rd harmonic + optimised $2\omega$ and compensates CMV.

The ripple reduction, hardware, control complexity, components used, and additional cost profiles of methods in this group are summarised in

Table 6. Comparison of C Group (hybrid-MMC: HB+FB and DC-bus management) approaches.

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
Hybrid MMC (DC-bus series switch) [1]	60.79% (s) at 10 Hz/62.63% (e) at 5 Hz	Medium	Series switch + snubber	Low–Medium	Low–Medium	No CMV; device current stress is nominal; industrially applicable.
Hybrid MMC operation: reducing average capacitor voltage [80]	≈58% cap.red.(s)/ $\approx 55-60\%$ est. cap. red. (e) at $2-10$ Hz	Low	No additional hardware	Very low	Low–Medium	Reduces required capacitance through operation.
HLC-MMC (horizontal coupling link + DC series switch) [81]	54.36% (s) at 10 Hz/N/A (e)	Medium	Horizontal tie + series switch	Medium	Medium	PMSM-focused; reported ripple and THD improvements as well.
Hybrid: Arm-Interchange concept [82]	12.3% (s) at 5 Hz/53.6% (e) at 5 Hz	Medium–High	Front-end stage + arm duty interchange	Medium	High	Strong at zero/low frequency; timing-sensitive.
Variable DC-bus (with multi-pulse rectifier) [83]	80% (s, approx) at 5 Hz/ 60% (e) at 3 Hz	Medium	12/24-pulse rectifier	Medium	Low–Medium	No circulating current injection; reduced bearing current risk; regeneration with AFE.
Hybrid MMC: raise m to 1.15 + 2nd-harmonic circulating current (SCCI) + 3rd-harmonic injection [84]	51% cap. red. (s)/51.85% ripple red. (e) at 50 Hz	Low–Medium	HBSM-MMC with a small number of FBSMs; software-based current and voltage injections	Low–Medium	Medium–High	Limits RMS arm current; no CMV is injected on the AC side; validated by experiment and simulation.
Hybrid MMC (HB + FB blend; design and operation) [85]	77.56% (s)/76.92% (e) at 50 Hz	Medium	Mixed HB + FB arms	Medium	Medium	Emphasizes DC fault blocking and device utilization optimization.
H-MMC: ripple minimization with optimal m in overmodulation [86]	44.40% (s)/40.00% (e) at 50 Hz	Low–Medium	No additional hardware	Low	Medium	Analytical + prototype validation; derives the m–ripple relationship.
Asymmetric Hybrid Phase-Leg MMC (HB phase leg + two FB hybrid legs) [87]	56.83% cap. red. (s)/N/A (e) at 50 Hz	Medium	Mix of FBSM and HBSM, directing switches (DS)	Medium	Medium–High	Compact volume, low DC current ripple, DC fault blocking; full range of m and PF.
Hybrid MMC (power redistribution with AC-side FBSMs) [88]	46.8% (s) at 20 Hz/50.0% (e) at 20 Hz	Medium–High	FBSM additions on the AC side	Medium	Medium–High	Ripple reduction plus potential CMV elimination.
Integrated composite energy storage: battery + supercapacitor (MMC-ICES) [89]	93.33% (s, approx) at 5 Hz/N/A (e)	High	Multiple DC-DC units + storage devices	High	Medium–High	Ripple suppression for low-speed, high-torque scenarios in shipboard MVDC.
Middle-cell + Third-Order Harmonic Voltage Injection (THVI/SHCI) [90]	57.14% (s)/51.25% (e) at 50 Hz	Medium–High	Middle-cell modules	Medium	Medium–High	Arm powers are reallocated; CMV cancellation is possible.
MMC-PFC + Asymmetric Energy Storage (battery on upper arm, supercapacitor on lower arm) [91]	30% (s) /30.77% (e) at 50 Hz	Medium–High	Battery + supercapacitor integration; PFC	Medium–High	High	PF/VU improvement; RMS current $-10\%$; field data; operating electricity cost $-19\%$.

.

4.4. Group D: SM-Level APD and Phase-Level APF Approaches

Group D approaches remove the low frequency power harmonics at $\omega$ and $2\omega$ from the main energy path and buffer them in an APD capacitor or an external storage element by adding active power decoupling stages at the submodule level or at the phase level. These stages can be realised using distributed or semi distributed architectures, for example as DC-DC APD converters placed in each submodule or in selected submodules, or as a per phase active power filter. By diverting the low frequency ripple power away from the main submodule capacitor, the required submodule capacitance is reduced and the submodule RMS current and losses decrease. The concept remains scalable when standard submodule voltage balancing measures are applied, for example capacitor voltage sorting and selection with appropriate insertion sequencing and, when needed, arm energy balancing via circulating current or zero sequence injection. The main disadvantage is the need for additional converter stages, inductors, and control loops.

The additional converter embedded within the SM is shown in Figure 16, while the phase-level separation with an APF (Active Power Filter) arm added per each phase is shown in Figure 17.

The component at $2\omega$ of the circulating current is suppressed by a closed loop [92]. In [93] the harmonic suppression is enhanced with PI + repetitive control without requiring HF common-mode voltage injection. The APD is implemented as an integrated APD-SM, sharing two switches with the full-bridge submodule; the APD, operating in buck and boost mode during the FB-SM’s zero-voltage switching (ZVS) intervals, transfers power to the auxiliary capacitor and reduces CVR [94]. Within the SM-internal (cellular) APD, the representative APD-SM arrangement shown in Figure 16 transfers the ripple power to the auxiliary capacitor within the cell via an auxiliary converter. In [95,96], based on a split-capacitor SM (SC-SM), the fundamental and second-harmonic components within the same SM are arranged to cancel each other, yielding an $88\%$ reduction in LF ripple and a relative ripple of about $2.0\%$ in laboratory measurements with dual-cycle control. Reference [97] directs ripple power to an auxiliary capacitor at the cellular level by placing a buck converter in each SM without adding an out-of-phase branch; the advantage is a significant reduction of CVR, the cost is an additional switch and inductor per SM and cellular control complexity.

Figure 16. Proposed MMC SM with active power decoupling [93,97].

Figure 16. Proposed MMC SM with active power decoupling [93,97].

At the phase level of the APF line, as shown in Figure 17, a buck-APF arm added to each phase collects the low-frequency ripple power in an external APF capacitor. Reference [98] proposes an APF-MMC that achieves higher suppression of low-frequency harmonics by using two high-frequency control degrees of freedom to shift the relevant power components to a higher-frequency region; the load current remains in the main converter power path, while the APF arm provides a separate current path for the low-frequency ripple power, so ripple buffering is physically separated from the main power transfer. Reference [99] combines a shared single mid-SM with a series buck-type APF; an additional buffer capacitor is used to handle the $2\omega$ ripple-power component, as the APF arm injects a compensating current that steers this component into the buffer capacitor rather than into the main SM capacitors, and an $\approx 50\%$ CVR reduction is reported in simulations and experiments. In [100], a buck-APF is placed in the nth SM of the upper arm and the lower arm’s first SM; SM ripple $\approx 50\%$ and average SM current $\approx 88\%$ reduction are reported (simulations and experiments).

Figure 17. Per-phase APF-integrated mid-SM APF-MMC topology (buck-APF in each phase) [100].

Figure 17. Per-phase APF-integrated mid-SM APF-MMC topology (buck-APF in each phase) [100].

From a comparative perspective, SM-internal topologies buffer the power harmonics within each submodule and enable faster local energy balancing by providing a short internal path for ripple-power exchange, whereas phase-level topologies largely preserve the existing SM topology and add an adjustable suppression channel per phase. When compact submodule-level integration is the main objective, SM-level APD is more attractive; when retrofit flexibility and phase-wise regulation are prioritised, phase-level APF becomes more appropriate. A comparison of these findings is provided in Table 7 (“Group D—Comparison of SM-level APF approaches”), which summarises the strengths and limitations of each method in terms of ripple reduction, hardware and control complexity, and additional cost.

Table 7. Comparison of Group D (SM-level APD) approaches.

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
SM with APD (auxiliary HB + L + split C) [92]	91.36% (s)/ 87.84% (e) at 50 Hz	Medium–High	Additional HB, L and C	Medium	Medium–High	Fundamental/2f power is routed through the APD path; required capacitance is reduced.
Intra-SM APD (bidirectional buck–boost; PI and repetitive control) [93]	84.78% (s)/86.67% (e) at 50 Hz	Medium–High	APD converter in each SM + APD capacitor	Medium	Medium	Low-frequency ripple is transferred to the APD capacitor without injecting HF CMV; validated by HIL simulation.
APD-SM (integrated, sharing two switches with FB-SM) [94]	85.08% (s)/82.03% (e) at 50 Hz	Medium	FB-SM with integrated APD	Medium	Medium	Buck and boost functionality; power buffering.
Split-Capacitor SM–based APD [95,96]	80%(est.) (s) /88.7% (e) at 50 Hz	Medium	Split-capacitor SM + APD arrangement	Medium	Medium	Fundamental and 2nd harmonic are suppressed.
Per-SM APD (buck type) [97]	92.00% (s) /90.74% (e) at 50 Hz	Medium–High	APD (switch + inductor) per SM + APD capacitor	Medium	Medium–High	Significant CVR reduction; per-SM control overhead.
APF-M3C (shared middle SM + buck-type APF) [99]	49.59% (s)/ 22.48% (e) at 50 Hz	Medium–High	Middle SM + APF inductor/switch	Medium	Medium–High	Loss reduction; balancing and control strategies provided.
APF-MMC (per-phase buck APF) with two HF degrees of freedom [98]	51.22% (s)/54.19% (e) at 10 Hz	Medium–High	APF leg + storage element	Medium	Medium–High	Fundamental power is shifted to HF; outperforms classical MMC at low speed (simulation + experiment).
APF-MMC (buck-APF inserted between selected upper–lower arm nodes) [100]	23.33% (s)/ 19.51% (e) at 50 Hz	Medium–High	APF (buck) + storage capacitor	Medium	Medium–High	SM average current less than ∼$88\%$; verified by simulation and experiment.

Table 7. Comparison of Group D (SM-level APD) approaches.

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
SM with APD (auxiliary HB + L + split C) [92]	91.36% (s)/ 87.84% (e) at 50 Hz	Medium–High	Additional HB, L and C	Medium	Medium–High	Fundamental/2f power is routed through the APD path; required capacitance is reduced.
Intra-SM APD (bidirectional buck–boost; PI and repetitive control) [93]	84.78% (s)/86.67% (e) at 50 Hz	Medium–High	APD converter in each SM + APD capacitor	Medium	Medium	Low-frequency ripple is transferred to the APD capacitor without injecting HF CMV; validated by HIL simulation.
APD-SM (integrated, sharing two switches with FB-SM) [94]	85.08% (s)/82.03% (e) at 50 Hz	Medium	FB-SM with integrated APD	Medium	Medium	Buck and boost functionality; power buffering.
Split-Capacitor SM–based APD [95,96]	80%(est.) (s) /88.7% (e) at 50 Hz	Medium	Split-capacitor SM + APD arrangement	Medium	Medium	Fundamental and 2nd harmonic are suppressed.
Per-SM APD (buck type) [97]	92.00% (s) /90.74% (e) at 50 Hz	Medium–High	APD (switch + inductor) per SM + APD capacitor	Medium	Medium–High	Significant CVR reduction; per-SM control overhead.
APF-M3C (shared middle SM + buck-type APF) [99]	49.59% (s)/ 22.48% (e) at 50 Hz	Medium–High	Middle SM + APF inductor/switch	Medium	Medium–High	Loss reduction; balancing and control strategies provided.
APF-MMC (per-phase buck APF) with two HF degrees of freedom [98]	51.22% (s)/54.19% (e) at 10 Hz	Medium–High	APF leg + storage element	Medium	Medium–High	Fundamental power is shifted to HF; outperforms classical MMC at low speed (simulation + experiment).
APF-MMC (buck-APF inserted between selected upper–lower arm nodes) [100]	23.33% (s)/ 19.51% (e) at 50 Hz	Medium–High	APF (buck) + storage capacitor	Medium	Medium–High	SM average current less than ∼$88\%$; verified by simulation and experiment.

4.5. Group E Structural/Topological Changes (SM/arm Architecture; MMC Relatives)

Group E encompasses approaches that passively reduce low-frequency power oscillations at $\omega$ and 2$\omega$ at their source through topological revisions made at the SM and arm levels on the standard MMC architecture. Instead of adding active APF channels, the converter’s internal energy-sharing paths are rearranged so that the ripple power is spread over more capacitors; thus, $V_{SM}$ becomes smoother and the capacitance required per individual SM can be reduced. The absence of an additional HF magnetic component or external power channel simplifies hardware integration; however, the topologies require a rethinking of the modulation, balancing, protection, and fault detection processes.

Parallel-C and three-level SM configurations reduce capacitor-voltage ripple (CVR) at low switching frequencies by enabling parallel connection of submodule capacitors at the intermediate level; some designs achieve a similar effect with fewer semiconductors, drivers and sensors [101,102]. In the diode-clamped HB-MMC group, often described as spontaneous capacitor parallel behaviors (SCPB), clamp diodes and RC damping networks, together with auxiliary networks distributed across phases produce inherent self-balancing of cell voltages, easing sensing and communication needs [103].

As illustrated in Figure 18, M-MMC introduces a mid-SM-assisted auxiliary coupling between the top and bottom SM capacitors, creating an internal equalisation path that reduces the fundamental and $2\omega$ components; suppression is strengthened with PI + R control, and a saving of one SM per phase is reported [104]. In Dual-MMC (open-end), two MMC legs are modulated with opposite phase and adjacent arms share a submodule capacitor; hence, the number of SM capacitors is halved (with the SM count unchanged), while high torque at low and zero frequencies is maintained [105]. Single-arm MMC (SAMMC) merges upper and lower arms into a single arm so that all capacitors are continuously engaged via four-terminal SMs; for the same voltage level and ripple target, the capacitance per SM is ≈52% and the total capacitance is ≈26% compared with a standard MMC [106]. In $3\times 3$-MMSC, phase decoupling, meaning that each phase operates as an electrically independent single-phase SM string with no internal inter-phase energy-exchange path, eliminates undesired circulating currents and the need for bulky arm inductors, improving CVR under variable-speed operation, particularly at low fundamental frequencies, with an efficiency close to that of the modular multilevel matrix converter (M3C) [107].

Within the same layer, reconfigurable topologies further reduce CVR by distributing power harmonics according to the operating conditions. With self-energy equalisation, an equalisation branch, made of a clamp IGBTs plus a limiting inductor, is added between the upper and lower arms of each leg; using appropriate switching sequences, arm energies are periodically balanced from 0 Hz to the rated frequency; no isolation transformer is needed and the additional semiconductor count is limited compared with EEM-style topologies [108]. For the LF and HF two-mode arrangement, in LF mode only the top and bottom SMs per arm remain active while the others are bypassed; the series DC-link switch is kept open (off) and a low-voltage auxiliary source through a series diode supports start-up, achieving high starting torque and very low CVR without injecting circulating-current and CMV; as frequency rises, a designed transition to HF mode is performed [109], suppressing fluctuations via the parallel interconnection of the top and bottom SM capacitors (accessorial cables) in LF mode.

In summary, Group E combines topologies that suppress low frequency power oscillations by revising the internal architecture of the standard MMC at SM and arm levels, without adding active power channels. SM-level parallel-capacitor and three-level, together with SCPBs reduce the ripple across $V_{SM}$ and reduce CVR by spreading ripple power across counter-phase paths within the cell [101,102,103]. Arm level derivatives (M-MMC, Dual-MMC, SAMMC, 33-MMSC) regulate how fluctuating power is shared within an arm, enabling low-CVR operation in the low frequency region while reducing capacitance, sensor and inductor requirements [104,105,106,107,108,109]. The comparison between the topologies of this group are synthesised in

Table 8. Comparison of E Group (structural/topological changes) approaches.

Method	Ripple Reduction	Hardware Complexity	Components	Additional Cost	Control Complexity	Additional Information
3-level SM (parallel-capable capacitors, 8 switches/ SM) [101]	39.39% (s)/17.72% (e) at 50 Hz	Medium	2× capacitors, 8 switches/SM	Medium	Medium	At low frequency, capacitor ripple decreases.
New 3-level SM with fewer semiconductors (parallel-capable capacitors) [102]	50% (s)/50% (e) at 50 Hz	Medium	Fewer switches and drivers; fewer sensors	Low–Medium	Medium	Compact SM; reduced SM capacitor ripple; simulation + experiment.
Diode-clamped HB-MMC (passive self-balancing) [103]	11.11% (s) /40.0% (est.) (e) at 50 Hz	Medium–High	Clamping diode + RC network	Medium	Medium	Reduces sensor and sorting requirements; ripple equalization via RC damping.
M-MMC (architectural modification) [104]	85.60% (est.) (s)/85.60% (e) at 20 Hz	Medium	Middle cell/architectural additions	Medium	Medium	Focused on 2nd-harmonic suppression; experimental prototype.
Dual-MMC (open-end) + Shared-Capacitor SM [105]	50% cap. red. (s)/n/a (e) at 50 Hz	Medium	Shared capacitor + additional switches	Medium	Medium	Reduces the volume of capacitors; requires an open-end stator.
Single-armed MMC (all capacitors engaged at all times) [106]	≈74.0% (s)/≈74.0% (e) at 60 Hz	Medium	Single-arm structure; parallel capacitor wiring	Medium	Medium	Total capacitance requirement decreases; experimentally validated.
3 × 3 MMSC (MMC relative, series-modular) [107]	78.50% (s) at 1 Hz/78% (est.) (e) at 1 Hz	Medium	Series-modular cells	Medium	Medium	Alternative to MMC; good low-frequency performance.
Self-energy-balancing MMC (passive equalization network) [108]	94.66% (s) at 2 Hz/45.28% (e) at 5 Hz	Medium	Passive equalization elements	Low–Medium	Low–Medium	Low ripple at 0/low frequency; simulation + experiment.
High torque at 0/low speed: Cable-based parallel connection of SM capacitors + pre-charge [109]	≈100% (s) at 50 Hz/≈97% (e) at 50 Hz	Medium	Cable links + simple additions (series switch + diode + DC source)	Low–Medium	Medium	Practical for fan/pump loads; prototype experiments available.

, in terms of ripple reduction, hardware complexity, component additions, incremental cost, control complexity, and additional information.

5. Design Trade-offs and Selection Guidelines

The insights from Groups A–E are synthesised in this section to provide application-driven selection guidance. Rather than restating the comparative metrics, the aim is to translate the reviewed evidence into practical trade-offs and indicative selection rules under realistic constraints in MV drives and grid-facing converters. These guidelines are intended primarily for low-frequency CVR mitigation in DC–AC MMCs; the DC–DC MMC topologies discussed in Section 3 are not included in

Table 9. Application-based selection guidelines for hardware-based CVR reduction methods (Groups A–E).

Primary Requirement/Constraint	Indicative Group(s)	Rationale and Practical Caveats
Low-speed/near-zero frequency operation (LF ripple dominates)	A, D, E	Energy-routing or buffering concepts can target LF ripple energy; add-on filtering may be feasible depending on power level and integration constraints. Consider scalability and additional losses.
High scalability with large number of SMs (minimise replicated hardware)	B, C, D (arm-level APF), E *	Approaches that avoid per-SM replication can scale more favourably; verify whether added components are per-arm, per-phase, or per-SM.
EMI and CMV	B, C	Isolated/HF channels may decouple ripple power but introduce HF EMI considerations; topological/hybrid choices can influence CMV behaviour depending on implementation.
Maintainability, modularity, and fault tolerance	C (selected), E	May reduce per-SM instrumentation/replication when achieved without per-SM added circuitry; however, hybrid protection coordination (C) and non-standard SM formats (E) can introduce maintenance and spare-parts challenges.
Cost and industrial feasibility	C, E *	Cost advantages are more likely when additional hardware is limited (often Group C) or when structural changes reduce capacitance (selected Group E); however, non-standard SM formats and certification/integration effort can dominate total cost.

* Group E is recommended only for selected topologies; applicability is platform-dependent. Note: The group recommendations are indicative and derived from the qualitative synthesis of the reviewed studies; final selection remains application- and specification-dependent.

, as they are associated with different operating objectives and evaluation criteria.

5.1. Low-Speed or Near-Zero Frequency Operation

Low-speed operation is a distinctive requirement for MV motor drives compared with grid-connected converters operating at a fixed fundamental frequency [9,109]. As the output frequency decreases, the dominant low-frequency arm-energy oscillations (typically associated with $\omega$ and $2\omega$ components, depending on operating point and internal power exchange) are spread over a longer time interval; consequently, for a fixed capacitance and power demand, the energy that must be buffered by the SM capacitors increases and the resulting CVR can become more pronounced [3,4,10,93,98]. This is why many recent CVR-mitigation concepts explicitly target the low-frequency region, reporting their effectiveness under low-frequency operation and near-zero-speed conditions [78,83].

From a mechanistic perspective, three indicative solution directions emerge in the reviewed literature. First, Group A approaches introduce dedicated physical channels (often isolated and HF-link-based) that route ripple power through a path distinct from the primary SM energy-storage route, providing a direct means to manage low-speed ripple energy [17,66,68,69]. Second, Group D concepts employ SM-level active power decoupling (APD) and phase-level active power filtering (APF) so that low-frequency ripple power is buffered in auxiliary storage elements rather than being fully absorbed by the SM capacitors [93,97,98,99,100]. Third, Group E topological modifications mitigate low-frequency ripple through architectural changes such as split-capacitor arrangements or inherent balancing behaviour, which can reduce the effective low-frequency voltage fluctuation without relying on HF isolation [95,96,101,103,108].

These benefits typically come with application-dependent trade-offs. HF-link channels may introduce additional EMI considerations, insulation and thermal-design requirements, and non-negligible auxiliary losses due to added HF switching nodes and magnetic components [66,68,69]. APD/APF-based buffering can reduce low-frequency CVR effectively, but it adds auxiliary power-processing stages and storage elements, with implications for component count, control interfacing, and efficiency [97,98,99]. Structural/topological solutions can be attractive from an integration standpoint, yet their effectiveness is sensitive to the platform’s wiring constraints, balancing strategy, and practical implementation limits [95,101,108]. Therefore, the group recommendations in Table 9 should be regarded as indicative starting points rather than universal prescriptions.

5.2. Scalability with the Number of Submodules

In practical MMC platforms, the number of submodules per arm can be high, making scalability one of the primary design criteria [17,65]. Even relatively small additional circuits, when replicated across many submodules, can lead to pronounced increases in bill of materials, wiring and assembly effort, footprint, and potential failure points [80,101]. Accordingly, in this review, “high scalability” refers primarily to minimising the per-submodule replication of added hardware as N grows.

From this perspective, a key distinction is whether a CVR mitigation concept introduces additional components per submodule (scaling approximately with N) or whether the added functionality can be realised at a more centralised level (e.g., per arm or per phase), which typically offers more favourable scalability [17,108]. Under this criterion, approaches in Group C are often attractive for high-N platforms when ripple reduction is achieved through architectural or operational measures with limited replicated hardware [1,80,82]. Likewise, Group B concepts can exhibit favourable scalability when the required additional cells/channels are implemented at arm level rather than being duplicated within each submodule. For Group D, scalability depends strongly on implementation: arm-level active filtering (APF) can avoid per-submodule replication and therefore scale favourably, whereas SM-internal active power decoupling (APD) typically introduces hardware that must be duplicated across submodules and may become less attractive as N increases [108]. Although Group A power-channel concepts can provide strong ripple-energy management, their scalability is highly case-dependent; therefore, they are not listed as a primary candidate under this criterion, unless the HF-link functionality is realised at a shared arm/phase level rather than replicated per submodule [17,65,66]. In general, Group E structural solutions are not primary candidates under the “high scalability” criterion because the required architectural modifications are typically replicated across all submodules (i.e., the intervention scales with N), increasing integration effort as the number of SMs grows. However, the two modified-MMC examples in [104,109] can be regarded as more scalable within Group E because their ripple-mitigation effect is achieved mainly through an arm-level reconfiguration with only a limited number of specialised elements: [104] introduces a single middle SM per phase and uses top–bottom SM coupling, whereas [109] realises the modified operation through a system-level auxiliary switching arrangement without requiring a dedicated modification in every regular SM.

Topologies that concentrate auxiliary circuitry at higher hierarchy levels (arm/phase) and avoid extensive per-submodule replication can serve as indicative starting points (Table 9), subject to performance requirements and practical integration constraints [17,80,108].

5.3. EMI/CMV Implications

Hardware-based interventions aimed at CVR reduction affect loss distribution and electromagnetic behaviour (EMI/CMV) as well as reducing ripple amplitude, since they alter which elements carry the power flow. In MV motor drives, CMV, dv/dt-induced parasitics, and bearing currents interact with circulating-current components and any added auxiliary power paths, becoming decisive for both efficiency and reliability. Therefore, selection is best framed as a design trade-off, not solely in terms of CVR reduction percentage, but also against target CMV/EMI limits and the allowable loss budget [15,17,97].

The groups exhibit different risk–benefit profiles along this axis. HF-link channel-based solutions in Group A can provide strong CVR suppression by transferring low-frequency ripple power into an auxiliary HF path; however, HF transformers and additional power stages introduce new high-frequency switching nodes. This can increase switching and magnetic (core/copper) losses and impose EMI-sensitive layout and filtering requirements [17,65,66,68]. Similarly, in Group D, SM-integrated APD or phase-level active power processing can potentially improve efficiency by reducing circulating-current and RMS-current components through buffering ripple energy to auxiliary storage; nevertheless, the additional switching losses and integration complexity of the auxiliary stages must be evaluated concurrently [97,99].

When EMI/CMV and bearing-current risk are primary concerns, the core motivation of Group B in the literature is to reshape power paths so as to reduce CMV and, in turn, mitigate bearing-current and EMI risk; star-channel and active cross-coupled structures explicitly target architectural advantages in this direction [15,55]. Modified MMC approaches that limit or suppress CMV generation reinforce the same selection rationale [75]. However, because EMI/CMV performance—especially for HF-channelled and hybrid architectures—is not systematically reported across most studies using platform-independent, standardised metrics, the indicators in Table 9 should be treated as starting points that require application-specific verification (loss budget, CMV/EMI measurements, cabling/grounding architecture, and filter design), rather than as final judgements. Selected Group C hybrid and DC-bus/operation-based schemes can also influence common-mode behaviour through their switching-state allocation and operating-point shaping, and may therefore offer a pragmatic compromise when CMV/EMI constraints must be balanced against CVR reduction and loss targets. However, as with HF-channelled solutions, the resulting EMI/CMV performance is highly implementation-dependent and should be verified experimentally under realistic cabling and grounding conditions.

5.4. Maintainability, Modularity, and Fault Tolerance

Maintainability, modularity, and fault tolerance are often just as decisive as efficiency in the industrial adoption of MMCs. Therefore, hardware-based interventions proposed for CVR reduction are evaluated not only in terms of ripple performance but also in relation to field maintenance processes, spare-parts strategy, diagnostics, and degraded-mode operation objectives. While the literature emphasises the contribution of MMC’s fundamental advantages (scalability, modular maintenance, fault tolerance) to system design, it is also indirectly evident that lower-level architectural changes can affect these advantages in different ways [3,9].

Along this axis, a practical distinction emerges between approaches that add “additional hardware per SM” and those that “simplify or reorganise the architecture.” Solutions such as SM-integrated active power decoupling (APD) (Group D) can manage electrical stresses by directing ripple energy to auxiliary storage; however, the switches, drivers, and measurement requirements added to each SM may introduce a new layer of complexity in terms of maintenance and failure reliability statistics [97]. Similarly, while HF-link channels or additional power-processing paths (Group A) can provide strong CVR suppression, the added magnetic components and auxiliary stages may require a more comprehensive platform approach in terms of both integration and service logistics [69]. Certain topological arrangements (Group E) (e.g., SM implementations that allow effective parallelisation of capacitor energy or exhibit inherent parallel balancing behaviour) may reduce measurement and balancing burdens, thereby alleviating maintenance and communication complexity [101,103,108]; however, from a practical engineering perspective, solutions that deviate from the standard SM form factor can complicate platform-level standardisation and module replacement logistics, even when their ripple and balancing benefits are attractive.

From a fault-tolerance perspective, the critical issue is how the CVR-reduction mechanism integrates with existing MMC protection and restart logic. Active bridging/channel-based structures (Group B; e.g., active cross-coupled connections and star-channel arrangements) introduce additional current paths and semiconductor devices, which can make fault-current trajectories, fault detection, and higher-level coordination requirements more pronounced [15,55]. In hybrid MMC architectures (Group C), additional switching states may offer advantages in CVR shaping, but DC-fault behaviour and protection coordination (blocking, energy-discharge paths, restart sequences) often require clearer definition; some hybrid approaches address this alongside objectives such as DC-fault blocking [1,14,87].

5.5. Cost and Industrial Feasibility

Hardware-based approaches aimed at reducing CVR have the potential to lower the SM capacitor value (and thus volume); however, at the same time, new switching elements, magnetic components, sensing, and auxiliary power paths can increase the bill of materials (BOM), packaging effort, and qualification burden. From an industrial feasibility perspective, cost is not solely a matter of part count; it is also evaluated in conjunction with repeated additions that scale with the number of submodules, isolation/EMC requirements, production and integration time, and field-service logistics [3,9]. Therefore, the choice is approached as a design trade-off around whether the targeted capacitance/volume gain can be achieved with acceptable additional hardware and integration cost, rather than as a goal of “maximum CVR suppression.”

The examined groups present distinct profiles in terms of cost and feasibility. HF-channel coupled solutions in Group A can provide strong suppression by transferring ripple power to an auxiliary HF path, but they tend to increase cost, layout complexity, and qualification requirements due to HF transformers and additional bridges [17,66,69]. Similarly, Group D’s SM-integrated APD or APF derivatives, while aiming to reduce CVR (and in some cases certain loss components), can increase BOM and integration burden because they add switching and control stages per SM [97,99,100]. In contrast, hybrid MMC derivatives (Group C) often target reduced capacitance requirements with comparatively limited additional hardware; in this direction, cost-oriented hybrid arm proposals and hybrid MMC sizing studies are particularly emphasised in the literature [1,14,84,85,86,87]. Topological revisions (Group E) are also presented in some cases with claims of reduced total capacitance, passive/semi-passive balancing, or “cost–size–weight” improvements; however, the degree of deviation from a standard SM form factor can ultimately determine application feasibility [101,103,105,106,107,108].

In practice, cost and feasibility claims are strongly platform-dependent; therefore, the indicators under this subheading should be treated as an initial screening framework rather than a final suitable or unsuitable judgement.

6. Conclusions

This paper has reviewed hardware-based circuit topologies that target the reduction of submodule (SM) capacitor-voltage ripple in modular multilevel converters at low-frequency operation. Building on the physical origin of low-frequency power oscillations in MMC arms, the proposed topologies have been organised into five groups: (A) high-frequency magnetic or switched physical power channels, (B) transformerless active channels and bridging cells, (C) hybrid MMC and DC-bus management schemes, (D) SM-level active power decoupling and phase-level active power filters, and (E) structural changes in the SM architecture. These groups were compared in terms of ripple reduction, required capacitance, hardware and control complexity, additional components and cost, as well as their impact on circulating currents, common-mode voltage (CMV), and drivability over the low-speed region.

Overall, the group-based comparison indicates that the reviewed hardware-based CVR mitigation approaches can be synthesised around three overarching mechanisms: (i) diverting low-frequency ripple power from the main SM-capacitor path to a dedicated auxiliary power channel or energy buffer (particularly Groups A and D), (ii) reshaping the ripple source and arm power sharing via transformerless bridging channels (Group B) and hybrid or DC-bus-level measures (Group C), and (iii) providing passive or semi-passive attenuation by altering the SM or arm coupling structure (Group E). This synthesis makes application-driven selection logic more explicit. Low-speed CVR can be reduced most directly by managing the ripple energy through an auxiliary power channel (Group A) or an active energy buffer (Group D: APD/APF), rather than relying on the SM capacitors to absorb and release that ripple energy. When CMV/EMI and bearing-current risk dominate, Group B options (e.g., star-channel and middle-cell concepts) and selected Group C variants that explicitly target CMV (e.g., HB + FB blending, THVI with compensation) can often offer a favourable balance by jointly shaping ripple and common-mode behaviour. In contrast, when cost constraints prevail and a moderate improvement is sufficient, hybrid/operation-based measures in Group C with limited additional equipment (e.g., DC-bus series switching or operation around an optimal modulation index) may represent pragmatic starting points, while Group E structural solutions can provide passive/semi-passive attenuation where architectural intervention is feasible. In such cases, implementation-level complements—including appropriate capacitor parallelisation practices and suitable pre-charge arrangements—can further support practical effectiveness.

The review has also highlighted several aspects that appear only partially covered in the existing hardware-based literature. First, quantitative comparison between Groups A–E is hampered by the fact that most case studies use different power ratings, motor-speed profiles, SM capacitances and switching frequencies; this makes it difficult to benchmark ripple reduction, circulating currents and losses under common conditions and suggests a need for standardised drive profiles and shared design points in terms of the number of SMs per arm, the SM-capacitance value and the switching frequency. Second, only a small subset of works evaluates the impact of SM-capacitor ripple and circulating current on semiconductors’ and capacitors’ lifetime; most report instantaneous or RMS values without linking them to thermal cycling or reliability metrics, so the long-term lifetime implications of the proposed schemes remain insufficiently quantified. Third, EMI/CMV behaviour and bearing-current mitigation are rarely quantified for HF-channel and hybrid topologies, even if the additional HF components and common-mode paths can strongly influence these effects. Finally, while the review has indicated that certain combinations of groups (e.g., C + B or D + C) can in principle address both low-frequency ripple and CMV, systematic design guidelines and experimental demonstrations of such integrated solutions are still scarce and represent a promising direction for future work.

An emerging direction concerns energy-storage-embedded MMC architectures, where low-frequency ripple-power management is increasingly discussed together with energy-management objectives such as SOC balancing. In this line, storage embedded submodules can be interpreted as controllable buffers that may enable multi-objective co-design across CVR mitigation, energy utilisation, and ancillary services, rather than treating ripple reduction as an isolated optimisation target [64,71,110,111,112]. In parallel, there appears to be a continued interest in ripple-power routing infrastructures (e.g., multiport and inter-module/arm power channels, including isolated HF-link and related power-channel concepts), which can provide additional degrees of freedom for redirecting ripple energy and may offer a platform for joint consideration of CVR with EMI/CMV and bearing-current constraints in drive-facing applications [17,65,66].