Ripple Minimization Method for a Modified Non-Inverting Buck–Boost DC–DC Converter

Abstract

This paper presents an improved switching strategy developed for the Modified Non-Inverting Step-Down/Up (MNI-SDU) DC–DC converter. Unlike previously studied switching strategies, the proposed approach changes the firing sequence and then the equivalent circuits without increasing the switching frequency. This switching technique alters the equations used to select the converter’s capacitors, enabling a different voltage ripple in the capacitors while maintaining the same capacitance as in the previous operation. The proposed switching technique is introduced with a theoretical explanation, and the feasibility of the proposed method is verified through experimental results on a 570 W prototype. The results indicate that the new operation reduces capacitor capacitance and achieves over 58% voltage ripple reduction for both capacitors, while preserving desired operation, specified capacitances, and voltage regulation. The proposed strategy provides a compact and effective solution for high-performance power converters in battery-regulated and renewable-energy systems.

1. Introduction

Power electronics enable efficient conversion of electrical power using semiconductor switching devices [1,2]. Among other converter types, DC–DC converters are essential in a wide range of applications such as renewable energy systems, electric vehicles, and portable electronics. In many cases voltage levels must be accurately regulated despite variations in input supply [3,4]. In such scenarios, maintaining a good operation and high conversion efficiency is important for improving the overall reliability and lifespan of elements such as lithium-ion batteries, supercapacitors, or fuel cells [5].

Some applications of DC–DC conversion demand converters capable of operating in both step-down and step-up modes while ensuring smooth current profiles and compact design. In recent years, several non-inverting buck–boost topologies have been proposed, aiming to offer advantages compared to conventional converters [6,7,8,9,10,11].

One of the recent contributions to the power electronics field in the buck–boost conversion field was the introduction of the so-called Modified Non-Inverting Step-Down/Up (MNI-SDU) converter [12,13]. This converter was initially introduced in [12] as an alternative combining high efficiency with a non-pulsating input current and a non-inverted output voltage. The MNI-SDU converter shown in Figure 1, uses two active switches and two capacitors arranged to enable partial direct power transfer between input and output, reducing redundant power processing. In its original configuration, both switches are driven synchronously by a single duty cycle, providing good regulation but limited flexibility for optimizing ripple and stress.

In a subsequent study [13], the operation of the MNI-SDU was improved through an asynchronous control strategy, where the two active switches were driven with a time offset between their gating signals. This offset allowed the introduction of an additional switching state, enabling better distribution of energy between stages. Experimental validation demonstrated that the asynchronous mode reduce the electrical stress of semiconductors and capacitors, improving efficiency and transient performance, and a noticeable reduction in the input current ripple [13].

This ripple reduction is particularly relevant given that it is achieved in a buck–boost converter. Although several ripple reduction techniques have been reported in the literature, they are more commonly applied in boost converters [14,15]. A representative example is the widely used interleaving technique, which employs multiple parallel phases operated with a fixed phase shift (typically 180° for two phases). By ensuring that the inductor currents in each phase do not reach their peak values simultaneously, interleaving (both combined, the switching signals and the topology) reduces the input current ripple seen by the source [16,17]. This approach is especially effective in boost converters; for example, the traditional buck–boost converter cannot benefit from this effect since the input current is not a triangular waveform.

This article proposes a further improvement in the operation of the MNI-SDU converter, which involves a different switching technique that allows for reducing the voltage ripple in both capacitors while maintaining the specified capacitance, without increasing the converter’s switching frequency or altering the voltage stress in components. The technique is introduced with a theoretical analysis, showing that the averaged model is not changed along with the steady-state and dynamic characteristics. The theoretical reduction in the voltage ripple in capacitors is demonstrated with experimental results. Then the proposed concept is validated through computer simulations and a 570 W laboratory prototype. The results confirm that the new capacitor selection equation achieves an over 58% reduction in the voltage ripple of both capacitors while maintaining the specified operation.

The rest of the paper is organized as follows: Section 2 introduces the MNI-SDU converter and reviews its operation under two established modulation strategies, synchronous two-state modulation and asynchronous modulation with time offset. Section 3 analyzes the proposed asynchronous phase-shift modulation with a time offset. Section 4 details the control scheme and presents experimental results from a 570 W prototype, including a comparative evaluation of the three strategies. Finally, Section 5 summarizes the concluding remarks.

2. The MNI-SDU Converter

The MNI-SDU converter shown in Figure 1 is composed of: a DC input voltage denoted by $E$; the output voltage $v_{C2}$, which corresponds to the voltage across the capacitor $C_2$; the transfer capacitor $C_1$; the inductors $L_1$ and $L_2$, corresponding to the input and output inductor, respectively; diodes $s_{1n}$ and $s_{2n}$; the active switches $s_1$ and $s_2$, which can operate either synchronously or asynchronously depending on the switching modulation strategy; and the load $R$. Here, $i_{L1}$ and $i_{L2}$ denote the currents through inductors $L_1$ and $L_2$, while $v_{C1}$ and $v_{C2}$ denote the voltages across capacitors $C_1$ and $C_2$. The duty cycle is represented by $d$.

This converter has the following advantages:

• The ability to step down or step up the input voltage.
• The transfer capacitor ensures a non-cascading interconnection between the input stage and the output stage, which reduces the redundant power processing.
• Low number of active and passive switches as well as electrical components.
• Non-pulsating input current, which makes it suitable for renewable energy processing applications.
• Non-inverting output voltage, with both input and output sharing a common ground reference.

Several operating modes for this converter have been proposed and described in the following subsections. The new operating mode introduced in this work is presented in detail in Section 3.

2.1. The Two-State Switching Strategy

The MNI-SDU converter introduced in [12] operates through synchronized switching of its two active transistors, i.e., they are turned ON and OFF simultaneously during each switching period. Therefore, a single control signal drives both switches as shown in Figure 2a, ensuring their synchronous operation, as illustrated in Figure 2b. Under this strategy, two equivalent circuits are obtained in continuous conduction mode (CCM): the ON-state circuit illustrated in Figure 3a and the OFF-state circuit illustrated in Figure 3b.

This modulation scheme is referred to as synchronous two-switching state modulation (STSS) and is applied to the MNI-SDU converter. The advantages of this modulation are the following:

• A simple circuit is used to generate pulse-width modulation (PWM), as both transistors share the same control signal.
• The converter analysis is straightforward since only two switching states are involved.
• For the proposed application, the required voltage gains remain close to unity. To achieve these gains, the operating mode requires duty cycles near 50%.

2.2. The Three-State Switching Strategy

In this subsection, the operating strategy in [13] is described, in which the two converter transistors are controlled asynchronously. This differs from the conventional synchronous operation described in Section 2.1, where both transistors switch simultaneously with a common duty cycle. The method proposed here assigns a duty cycle $d$ to the first transistor $s_1$, while the second transistor $s_2$ works with a time offset, i.e., it operates with a duty cycle $d+\delta$, where $\delta$ is the constant offset $1>\delta >0$. This modulation scheme is called asynchronous modulation with time offset (AMTO). The modulation circuit is shown in Figure 4a. The duty cycle signal is directly compared to the carrier signal, generating the modulation signal for the first transistor, represented by PWM₁. For the second transistor, a constant time offset is added to the duty cycle signal, and this is compared to the carrier signal to generate the second modulation signal represented by PWM₂. Figure 4b shows the pulse-width modulation signals with respect to the duty cycle. Both pulses start simultaneously, but the second pulse is wider.

This type of modulation generates three switching states, as observed in Figure 5, which generates several advantages compared to the STSS:

• The switching state {$s_1$, $s_2$} = {0, 1} increases the time in which energy from the source is directly delivered to the load; this further reduces redundant energy processing.
• It reduces current ripple values $\mathsf{\Delta }{i}_L$ in inductors and voltage ripple values $\mathsf{\Delta }{v}_C$ in capacitors.
• It decreases the voltage value of the transfer capacitor.
• It improves the overall efficiency.

Increasing the time offset $\delta$ leads to a significant reduction in ripple amplitude, transfer capacitor voltage, and overall converter power losses. Therefore, one of the key contributions of this work is the proposed methodology for selecting the time offset $\delta$. The methodology is summarized in the following steps:

• To ensure proper operation of the system, it is essential to define the voltage requirements according to the application. These specifications include the minimum voltage of the source $E_{min}$, the maximum voltage of the source $E_{max}$, and the required steady-state output voltage $V_{C2}$.
• Determine the voltage gain limits according to

  $$G_{\min }={\displaystyle \frac{V_{C2}}{E_{\max }}},$$

  (1)

  $$G_{\max }={\displaystyle \frac{V_{C2}}{E_{\min }}}.$$

  (2)
• Define the minimum and maximum critical duty cycles, denoted as $D_{crit-min}$ and $D_{crit-max}$, which establishes the operational boundaries required for reliable converter performance. To guarantee proper operation, the following inequality must be satisfied,

  $$D_{crit-\min }\le D<D+\delta \le D_{crit-\max }.$$

  (3)
• Obtain $\delta$ values that meet the maximum and minimum requirements. The value of $\delta$ to obtain the minimum voltage gain with the critical minimum duty cycle conditions is

  $${\delta }_a=-(1+G_{\min })D_{crit-\min }+G_{\min }.$$

  (4)
  Meanwhile, the value of $\delta$ to obtain the maximum voltage gain with the critical maximum duty cycle conditions is

  $${\delta }_b=\left(1+{\displaystyle \frac{1}{G_{\max }}}\right)D_{crit-\max }-1.$$

  (5)
• Select the value of $\delta$ as the lowest between ${\delta }_a$ and ${\delta }_b$, i.e.,

  $$\delta =\min \{{\delta }_{a,},{\delta }_b\},$$

  (6)

  this is the highest $\delta$ that achieves the set gain value without exceeding the duty cycle critical limits.

The methodology is summarized in the flowchart shown in Figure 6, which illustrates the logical sequence and facilitates understanding of the proposal.

3. The Proposed Switching Strategy

In this subsection, the proposed modulation strategy is presented. The two converter transistors are controlled asynchronously with a phase-shifted approach. This method applies the same duty cycle with a time offset for the second transistor, as outlined in Section 2.2. The main difference with respect to [13] lies in the phase-shift activation sequence of PWM₁ and PWM₂. This strategy also introduces asynchronous switch activation along with the associated time offset; however, the phase-shift effect leads to two distinct switching patterns for the step-up and step-down operation modes, as will become clear throughout this section. This proposed modulation scheme is referred to as asynchronous phase-shift modulation with time offset (APSMTO). The modulation circuit is illustrated in Figure 7a. The duty-cycle signal is directly compared with the carrier signal to generate ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$. For the second transistor, the duty cycle and a constant time offset $\delta ,$ are subtracted from unity; this result is then compared with the carrier signal and subsequently passed through a NOT gate to produce ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$. Figure 7b shows the pulse waveform relative to the duty cycle in step-down mode, while Figure 7c corresponds to step-up mode. Note that while the first pulse switches ON, the second pulse switches OFF.

Unlike STSS and AMTO strategies, where the switching states remain unchanged regardless of whether the converter operates in step-down or step-up mode, only the duty cycle increases during the transition, in APSMTO modulation; the duty cycle also increases when moving from the step-down to step-up operation mode. However, a switching state changes automatically during this transition. In step-down operation mode, PWM₁ does not overlap with PWM₂ due to the narrower duty cycle, resulting in a state where both transistors are OFF. In contrast, during boost operation, the larger duty cycle causes PWM₁ and PWM₂ pulses to overlap, creating a second state where both transistors are ON. Figure 8 illustrates the three switching states of the MNI-SDU converter in step-down mode, whereas Figure 9 depicts them in step-up mode.

Compared to the modulation approach presented in AMTO, the proposed strategy achieves a significant reduction in capacitor voltage ripple. A detailed analysis of this improvement is presented in the following subsection.

Modeling and Steady State Analysis

Based on the operating modes of the converter illustrated in Figure 8 and Figure 9, the average model of the system is derived. The first switching state occurs when transistor $s_1$ is turned ON and transistor $s_2$ is turned OFF, represented as {$s_1$, $s_2$} = {1, 0}. This state is common to both step-down and step-up modes, as shown in Figure 8a and Figure 9a. However, according to the APSMTO modulation scheme, this state occurs for a time fraction of $dT$ in step-down mode, as shown in Figure 7b, whereas in step-up mode, it remains for a time fraction of $\left(1-d-\delta \right)T$, as depicted in Figure 7c. The system model for this operating mode is as follows:

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E}{L_1}},$$

(7)

$${\displaystyle \frac{d{i}_{L2}}{dt}}=-{\displaystyle \frac{v_{C2}}{L_2}},$$

(8)

$${\displaystyle \frac{d{v}_{C1}}{dt}}=0,$$

(9)

$${\displaystyle \frac{d{v}_{C2}}{dt}}={\displaystyle \frac{i_{L2}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}.$$

(10)

The second switching state in step-down mode occurs when transistors $s_1$ and $s_2$ are turned OFF, represented as {$s_1$, $s_2$} = {0, 0} as shown in Figure 8b. This state occurs for a time fraction of $\left(1-d-\delta \right)T-dT=\left(1-2d-\delta \right)T$, as shown in Figure 7b. Hence, this operating mode is represented as

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E-v_{C1}-v_{C2}}{L_1}},$$

(11)

$${\displaystyle \frac{d{i}_{L2}}{dt}}=-{\displaystyle \frac{v_{C2}}{L_2}},$$

(12)

$${\displaystyle \frac{d{v}_{C1}}{dt}}={\displaystyle \frac{i_{L1}}{C_1}},$$

(13)

$${\displaystyle \frac{d{v}_{C2}}{dt}}={\displaystyle \frac{i_{L1}+i_{L2}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}.$$

(14)

The second switching state in step-up mode occurs when transistors $s_1$ and $s_2$ are turned ON, represented as {$s_1$, $s_2$} = {1, 1} as shown in Figure 9b. This state occurs for a time fraction of $dT-\left(1-d-\delta \right)T=\left(2d+\delta -1\right)T$, as shown in Figure 7c. This operating mode yields

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E}{L_1}},$$

(15)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_{C1}}{L_2}},$$

(16)

$${\displaystyle \frac{d{v}_{C1}}{dt}}=-{\displaystyle \frac{i_{L2}}{C_1}},$$

(17)

$${\displaystyle \frac{d{v}_{C2}}{dt}}=-{\displaystyle \frac{v_{C2}}{C_{2}R}}.$$

(18)

The third switching state occurs when transistor $s_1$ is turned OFF and transistor $s_2$ is turned ON, represented as {$s_1$, $s_2$} = {0, 1}. This state is common to both step-down and step-up modes, as shown in Figure 8c and Figure 9c. However, according to the APSMTO modulation scheme, this state occurs for a time fraction of $(d+\delta )T$ in step-down mode, as shown in Figure 7b, whereas in step-up mode it stayed for a time fraction of $\left(1-d\right)T$, as depicted in Figure 7c. Thus, the system model for this operating mode is

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E-v_{C1}-v_{C2}}{L_1}},$$

(19)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{v_{C1}}{L_2}},$$

(20)

$${\displaystyle \frac{d{v}_{C1}}{dt}}={\displaystyle \frac{i_{L1}-i_{L2}}{C_1}},$$

(21)

$${\displaystyle \frac{d{v}_{C2}}{dt}}={\displaystyle \frac{i_{L1}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}.$$

(22)

To obtain the average model of the converter in step-down mode, (7)–(10), (11)–(14), and (19)–(22) corresponding to the three switching states are considered. The state-variable expressions of each switching state are weighted by their respective time durations and then added. The resulting averaged model yields

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E}{L_1}}d+{\displaystyle \frac{E-v_{C1}-v_{C2}}{L_1}}(1-2d-\delta )+{\displaystyle \frac{E-v_{C1}-v_{C2}}{L_1}}(d+\delta ),$$

(23)

$${\displaystyle \frac{d{i}_{L2}}{dt}}=-{\displaystyle \frac{v_{C2}}{L_2}}d-{\displaystyle \frac{v_{C2}}{L_2}}(1-2d-\delta )+{\displaystyle \frac{v_{C1}}{L_2}}(d+\delta ),$$

(24)

$${\displaystyle \frac{d{v}_{C1}}{dt}}=0+{\displaystyle \frac{i_{L1}}{C_1}}(1-2d-\delta )+{\displaystyle \frac{i_{L1}-i_{L2}}{C_1}}(d+\delta ),$$

(25)

$${\displaystyle \frac{d{v}_{C2}}{dt}}=\left({\displaystyle \frac{i_{L2}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}\right)d+\left({\displaystyle \frac{i_{L1}+i_{L2}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}\right)(1-2d-\delta )+\left({\displaystyle \frac{i_{L1}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}\right)(d+\delta ).$$

(26)

To obtain the average model of the converter in step-up mode, (7)–(10), (15)–(18), and (19)–(22), corresponding to the three switching states, are now taken into account. As above, the state-variable expressions of each switching state are weighted by their respective time durations and then added. Hence, the average model of the system yields

$${\displaystyle \frac{d{i}_{L1}}{dt}}={\displaystyle \frac{E}{L_1}}(1-d-\delta )+{\displaystyle \frac{E}{L_1}}(2d+\delta -1)+{\displaystyle \frac{E-v_{C1}-v_{C2}}{L_1}}(1-d),$$

(27)

$${\displaystyle \frac{d{i}_{L2}}{dt}}=-{\displaystyle \frac{v_{C2}}{L_2}}(1-d-\delta )+{\displaystyle \frac{v_{C1}}{L_2}}(2d+\delta -1)+{\displaystyle \frac{v_{C1}}{L_2}}(1-d),$$

(28)

$${\displaystyle \frac{d{v}_{C1}}{dt}}=0-{\displaystyle \frac{i_{L2}}{C_1}}(2d+\delta -1)+{\displaystyle \frac{i_{L1}-i_{L2}}{C_1}}(1-d),$$

(29)

$${\displaystyle \frac{d{v}_{C2}}{dt}}=\left({\displaystyle \frac{i_{L2}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}\right)(1-d-\delta )-{\displaystyle \frac{v_{C2}}{C_{2}R}}(2d+\delta -1)+\left({\displaystyle \frac{i_{L1}}{C_2}}-{\displaystyle \frac{v_{C2}}{C_{2}R}}\right)(1-d).$$

(30)

To obtain a generalized averaged model for both operating modes, (23)–(26) and (27)–(30) are considered. By applying the same standard procedure used for the step-down and step-up operation modes, an overall averaged model for the converter operating in both modes is obtained as follows:

$${\displaystyle \frac{d{i}_{L1}}{dt}}=-{\displaystyle \frac{\left(1-d\right)}{L_1}}\left(v_{C1}+v_{C2}\right)+{\displaystyle \frac{E}{L_1}},$$

(31)

$${\displaystyle \frac{d{i}_{L2}}{dt}}={\displaystyle \frac{(d+\delta )}{L_2}}{v}_{C1}-{\displaystyle \frac{\left(1-d-\delta \right)}{L_2}}{v}_{C2},$$

(32)

$${\displaystyle \frac{d{v}_{C1}}{dt}}={\displaystyle \frac{\left(1-d\right)}{C_1}}{i}_{L1}-{\displaystyle \frac{(d+\delta )}{C_1}}{i}_{L2},$$

(33)

$${\displaystyle \frac{d{v}_{C2}}{dt}}={\displaystyle \frac{\left(1-d\right)}{C_2}}{i}_{L1}+{\displaystyle \frac{\left(1-d-\delta \right)}{C_2}}{i}_{L2}-{\displaystyle \frac{v_{C2}}{C_{2}R}}.$$

(34)

From the system dynamics (31)–(34), the steady-state values are obtained by considering the zero dynamics of the system. Therefore, the equilibrium equations are given by

$$V_{C1}=\left({\displaystyle \frac{1-D-\delta }{1-D}}\right)E,$$

(35)

$$V_{C2}=\left({\displaystyle \frac{D+\delta }{1-D}}\right)E,$$

(36)

$$I_{L1}=\left({\displaystyle \frac{D+\delta }{1-D}}\right){\displaystyle \frac{V_{C2}}{R}},$$

(37)

$$I_{L2}={\displaystyle \frac{V_{C2}}{R}}.$$

(38)

Notice that, to differentiate steady-state quantities from their time-varying counterparts, the former are represented using uppercase letters. By considering (36), the voltage ratio of the converter yields

$$G={\displaystyle \frac{V_{C2}}{E}}={\displaystyle \frac{D+\delta }{1-D}}.$$

(39)

For the design and selection of passive components, the peak-to-peak ripple limits for inductor currents, represented as $\Delta i_{L1}$ and $\Delta i_{L2}$, and for capacitor voltages, represented as Δv_C1 and Δv_C2, are taken into account. The switching frequency is denoted by $f_S=1/T$. Once these ripple specifications are defined, the required inductance and capacitance values can be calculated using the steady-state ripple relationships. The current ripples can be calculated, approximating the derivatives to increments, i.e., ${di}_L/dt=∆i_L/∆t$. Representing (7) in increments and considering $∆t=dT$, $\Delta i_{L1}$ can be obtained as (40). Representing (20) in increments and considering $∆t=(d+\delta )T$, $\Delta i_{L2}$ can be obtained as (41). Expressions (40) and (41) are valid for the converter operating in step-down and step-up modes.

$$\Delta i_{L1}={\displaystyle \frac{ED}{L_1{f}_S}},$$

(40)

$$\Delta i_{L2}={\displaystyle \frac{E(1-D-\delta )(D+\delta )}{(1-D)L_2{f}_S}}.$$

(41)

Conversely, the capacitor voltage ripple is obtained approximating the area under the current curve of capacitors when they are charged or discharged. The ripple values valid for the converter operating in step-down mode are

$$\Delta v_{C1}=\left({\displaystyle \frac{D+\delta }{C_1{f}_S}}\right)\left(I_{L2}-I_{L1}+{\displaystyle \frac{(\Delta i_{L1}+\Delta i_{L2})D}{2}}\right),$$

(42)

$$\Delta v_{C2}=\left({\displaystyle \frac{D+\delta }{C_2{f}_S}}\right)\left(I_{L2}-I_{L1}+{\displaystyle \frac{(\Delta i_{L1}+\Delta i_{L2})D}{2}}\right),$$

(43)

while the ripple values valid for the converter operating in step-up mode are

$$\Delta v_{C1}=\left({\displaystyle \frac{1-D}{C_1{f}_S}}\right)\left(I_{L1}-I_{L2}+{\displaystyle \frac{(\Delta i_{L1}+\Delta i_{L2})D}{2}}\right),$$

(44)

$$\Delta v_{C2}=\left({\displaystyle \frac{1-D}{C_2{f}_S}}\right)\left(I_{L1}-I_{L2}+{\displaystyle \frac{(\Delta i_{L1}+\Delta i_{L2})D}{2}}\right).$$

(45)

An important criterion for semiconductor selection is the voltage stress, which in this case is identical for all transistors and diodes. It corresponds to the sum of the capacitor voltages, as can be observed in Figure 8 and Figure 9. By adding expressions (35) and (36), we obtain

$$V_{stress}=V_{s1n}=V_{s2n}=V_{s1}=V_{s2}={\displaystyle \frac{E}{1-D}}.$$

(46)

4. Experimental Results

In this section, experimental results are presented to validate the effectiveness of the proposed switching modulation and control scheme. The approach is intended to regulate an input voltage ranging from 200 V to 250 V, which is typical in systems powered by lithium-ion battery packs, where voltage fluctuations occur due to variations in the state of charge of the battery. The strategy ensures a constant nominal output voltage of 220 V. To emulate the voltage variations in a battery pack for the experimental testing, a DC source model, Keysight DC3005 (Santa Rosa CA USA), is employed. The prototype is designed for an output power of 570 W and a switching frequency of 100 kHz. All relevant converter parameters are summarized in

Table 1. Parameters of the converter.

Parameters	Values
$\mathrm{Capacitor}, C_1$	2.2 µF
$\mathrm{Capacitor}, C_2$	2.2 µF
$\mathrm{Inductor}, L_1$	1.2 mH
$\mathrm{Inductor}, L_2$	1.2 mH
$\mathrm{Output} \mathrm{power}, P_{out}$	570 W
$\mathrm{Load}, R$	85 Ω
Input voltage, $E$	220 V nominal (200 V–250 V)
Switching frequency, $f_S$	100 kHz
Reference voltage, $V_{ref}$	220 V
$\mathrm{DIODE}, s_{1n}$	SCS315AHGC9
$\mathrm{DIODE}, s_{2n}$	SCS315AHGC9
$\mathrm{MOSFET}, s_1$	IPP026NIONF25
$\mathrm{MOSFET}, s_2$	SCT3120ALGC11

.

The methodology described in the flowchart of Figure 6 is employed to determine the optimal value of the time offset $\delta$. The voltage requirements according to the proposed application are $E_{min}=200 \mathrm{V}$, $E_{max}=250 \mathrm{V}$, and $V_{ref}=V_{C2}=220 \mathrm{V}$. Therefore, $G_{min}=220 \mathrm{V}/250 \mathrm{V}=0.88$ and $G_{max}=220 \mathrm{V}/200 \mathrm{V}=1.1$. The critical duty cycles are considered as $D_{crit-min}=0.2$ and $D_{crit-max}=0.8$. From (4) and (5), the parameter ${\delta }_a$ and ${\delta }_b$ are obtained as ${\delta }_a=0.5$ and ${\delta }_b=0.53$. Consequently, according to (6), $\delta$ is set to 0.5.

4.1. PI-PI Current Mode Controller

In this subsection, the loop-shaping control technique is used to design a controller for the MNI-SDU DC–DC converter operating under the APSMTO modulation scheme [18,19]. The design procedure begins with a standard small-signal linearization of the averaged model (31)–(34). The linearization is carried out around the operating point corresponding to the steady-state values defined in (35)–(38). Accordingly, the control signal and the four state variables are decomposed into two components: their nominal averaged values, denoted by uppercase letters, and their respective perturbations, indicated by a superscript “~”. The resulting linearized model is expressed as follows:

$$\left[\begin{array}{c}\begin{array}{l}{\dot{\tilde{i}}}_{L1}\\ \end{array}\\ \begin{array}{l}{\dot{\tilde{i}}}_{L2}\\ \end{array}\\ \begin{array}{l}{\dot{\tilde{v}}}_{C1}\\ \end{array}\\ {\dot{\tilde{v}}}_{C2}\end{array}\right]=\left[\begin{array}{cccc}0& 0& -{\displaystyle \frac{1-D}{L_1}}& -{\displaystyle \frac{1-D}{L_1}}\\ 0& 0& {\displaystyle \frac{D+\delta }{L_2}}& -{\displaystyle \frac{1-D-\delta }{L_2}}\\ -{\displaystyle \frac{1-D}{C_1}}& -{\displaystyle \frac{D+\delta }{C_1}}& 0& 0\\ {\displaystyle \frac{1-D}{C_2}}& -{\displaystyle \frac{1-D-\delta }{C_2}}& 0& {\displaystyle \frac{1}{C_{2}R}}\end{array}\right]\left[\begin{array}{c}\begin{array}{l}{\tilde{i}}_{L1}\\ \end{array}\\ \begin{array}{l}{\tilde{i}}_{L2}\\ \end{array}\\ \begin{array}{l}{\tilde{v}}_{C1}\\ \end{array}\\ {\tilde{v}}_{C2}\end{array}\right]+\left[\begin{array}{c}{\displaystyle \frac{V_{C1}+V_{C2}}{L_1}}\\ {\displaystyle \frac{V_{C1}+V_{C2}}{L_2}}\\ -{\displaystyle \frac{I_{L1}+I_{L2}}{C_1}}\\ -{\displaystyle \frac{I_{L1}+I_{L2}}{C_2}}\end{array}\right]\tilde{d},$$

(47)

$$\tilde{y}=\left[\begin{array}{cccc}1& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 0\\ 0& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{\tilde{i}}_{L1}\\ {\tilde{i}}_{L2}\\ {\tilde{v}}_{C1}\\ {\tilde{v}}_{C2}\end{array}\right].$$

(48)

In the linearized model, (47) has the form $\dot{\tilde{x}}=\mathit{A}\tilde{x}+\mathit{B}\tilde{d}$, while Equation (48) is expressed as $\tilde{y}=\mathit{C}\tilde{x}$. Using MATLAB (R2025b), the transfer functions of the system using Laplace transforms can be computed numerically by solving $\mathit{C}(s\mathit{I}-A{)}^{-1}\mathit{B}$. Table 1 presents the nominal parameters used for evaluation. These parameters also determine the average values of the state variables described in (35)–(38). Thus, the transfer function of interest can be computed numerically as

$${\displaystyle \frac{{\tilde{i}}_{L1}(s)}{\tilde{d}(s)}}={\displaystyle \frac{2.44\times {10}^5{s}^3+4.25\times {10}^9{s}^2+1\times {10}^{12}s+1.12\times {10}^{18}}{s^4+5.35\times {10}^3{s}^3+6.63\times {10}^6{s}^2+2.28\times {10}^{12}s+8.08\times {10}^{15}}},$$

(49)

$${\displaystyle \frac{{\tilde{v}}_{C2}(s)}{\tilde{d}(s)}}={\displaystyle \frac{-2.35\times {10}^6{s}^3+1.11\times {10}^{11}{s}^2-6.69\times {10}^{14}s+4.73\times {10}^{19}}{s^4+5.35\times {10}^3{s}^3+6.63\times {10}^6{s}^2+2.28\times {10}^{12}s+8.08\times {10}^{15}}}.$$

(50)

The poles of the transfer function ${\tilde{v}}_{C2}(s)/\tilde{d}(s)$ are located at $\left(-0.57\pm \mathrm{j}22.25\right)\times {10}^3$ and $\left(-2.12\pm \mathrm{j}12.59\right)\times {10}^3$, while the zeros at $49.61\times {10}^3$ and $\left(-1.22\pm \mathrm{j}20.09\right)\times {10}^3$. The transfer function ${\tilde{i}}_{L1}(s)/\tilde{d}(s)$ has the same poles, but the zeros are located at $-12.92\times {10}^3$ and $\left(-2.24\pm \mathrm{j}18.66\right)\times {10}^3$. It can be noticed that both transfer functions are stable, but ${\tilde{v}}_{C2}(s)/\tilde{d}(s)$ is the non-minimum phase, while ${\tilde{i}}_{L1}(s)/\tilde{d}(s)$ is the minimum phase. Thus, it is proposed to use a current-mode controller. This control scheme is shown in Figure 10. It is composed of two loops, an inner current loop and an outer voltage loop. Each loop incorporates a PI controller, where $k_{pi}$ and $k_{pv}$ represent the proportional gain, while $k_{ii}$ and $k_{iv}$ denote the integral gain of their respective loop.

To select the controller parameters, a loop-shaping technique is applied, which requires corresponding loop gains [20]. The loop-gain of the inner current control is denoted by $T_C$, while the loop gain of the outer voltage control is represented by $T_V$. According to the control scheme observed in Figure 10, they are defined as follows:

$$T_C=\left(k_{pi}+{\displaystyle \frac{k_{ii}}{s}}\right)\left({\displaystyle \frac{{\tilde{i}}_{L1}}{\tilde{d}}}\right),$$

(51)

$$T_V=\left(k_{pv}+{\displaystyle \frac{k_{iv}}{s}}\right)\left[{\displaystyle \frac{\left(k_{pi}+\frac{k_{ii}}{s}\right)\left(\frac{{\tilde{i}}_{L1}}{\tilde{d}}\right)}{1+\left(k_{pi}+\frac{k_{ii}}{s}\right)\left(\frac{{\tilde{i}}_{L1}}{\tilde{d}}\right)}}\right]\left({\displaystyle \frac{{\tilde{v}}_{C2}}{{\tilde{i}}_{L1}}}\right).$$

(52)

First, the Bode plot of the current-loop gain is derived from (51). The proportional and integral gains $k_{pi}$ and $k_{ii}$ are tuned so that the crossover frequency is approximately one decade below the switching frequency, with a slope of −40 dB/dec and an adequate phase margin, as illustrated in Figure 11. In this case, the selected gains $k_{pi}=0.3$ and $k_{ii}=2800$ meet these criteria, resulting in a bandwidth of 10,000 Hz and a phase margin of 40 degrees. Next, the Bode plot of the voltage-loop gain is obtained from Equation (52). Here, the gains $k_{pv}$ and $k_{iv}$ are adjusted so that the crossover frequency exhibits a slope of −20 dB/dec with appropriate phase and gain margins, as shown in Figure 12. The chosen gains $k_{pv}=0.003$ and $k_{iv}=56$ satisfy these requirements, yielding a bandwidth of 400 Hz, a phase margin of 85 degrees, and a gain margin of 20 dB.

The overall closed-loop diagram of the proposed strategy is illustrated in Figure 13. The DSP TMS320F28335 is used to implement the proposed modulation strategy and the PI–PI current-mode controller. The DSP employs two Simulink-generated ePWM blocks that provide high-resolution control through micro-edge positioning of approximately 150 ps, which is sufficient for the selected switching frequency of 100 kHz. In addition, the TMS320F28335 incorporates a 150 MHz high-performance CPU with fast interrupt handling, reducing memory-access latency and minimizing timing jitter. With respect to the sensors employed, a CLN-50 current sensor is used to sense the input current, and a LV-25P is used to sense the output voltage. To evaluate the closed-loop performance of the prototype, four categories of tests are conducted: steady-state, step changes in load, changes in the input voltage, and step changes in the voltage reference.

4.2. Closed-Loop Tests

Experimental validations under steady-state conditions are performed on the converter operating with an output power of 570 W, a time offset of $\delta =0.5$, and the proposed modulation scheme. Figure 14 illustrates the state variables of the converter at different voltage gain conditions. In Figure 14a, the converter operates in step-down mode, reducing the voltage from 250 V to 220 V. Under these conditions, the average input current is $I_{L1}=2.4 \mathrm{A}$, with a ripple of ${∆i}_{L1}=0.42 \mathrm{A}$, while the average current of the second inductor is $I_{L2}=2.6 \mathrm{A}$ with a ripple of ${∆i}_{L2}=0.55 \mathrm{A}$. The transfer capacitor voltage $V_{C1}$ reaches $93 \mathrm{V}$, and the output voltage remains regulated at $V_{C2}=220 \mathrm{V}$. In Figure 14b, the converter operates with unity voltage gain, maintaining the same voltage level of $220 \mathrm{V}$ at both the input and output terminals. Under these conditions, the input current is $I_{L1}=2.7 \mathrm{A}$ with a ripple of ${∆i}_{L1}=0.46 \mathrm{A}$, while the average current of the second inductor is $I_{L2}= 2.6 \mathrm{A}$ with a ripple of ${∆i}_{L2}=0.46 \mathrm{A}$. The transfer capacitor voltage $V_{C1}$ reaches $73 \mathrm{V}$, and the output voltage remains regulated at $V_{C2}=220 \mathrm{V}$. In Figure 14c, the converter operates in step-up mode, increasing the voltage from $200 \mathrm{V}$ to $220 \mathrm{V}$. Under these conditions, the average input current is $I_{L1}=3.0 \mathrm{A}$ with a ripple of ${∆i}_{L1}=0.48 \mathrm{A}$, while the average current of the second inductor is $I_{L2}=2.6 \mathrm{A}$ with a ripple of ${∆i}_{L2}=0.4 \mathrm{A}$. The transfer capacitor voltage $V_{C1}$ reaches $60 \mathrm{V}$, and the output voltage remains regulated at $V_{C2}=220 \mathrm{V}$. These graphs confirm the validity of the average state-variable expressions derived in the converter analysis using the proposed modulation scheme across different operating modes: step-up, unity voltage gain, and step-down.

Figure 15 shows the pulse-width modulation and current ripples in inductors with the converter operating at different voltage gain conditions. The output power is 570 W with an output voltage of $V_{C2}=220 \mathrm{V}$. In Figure 15a, the converter operates in step-down mode, reducing the voltage from 250 V to 220 V. Under these conditions, the input current ripple is ${∆i}_{L1}=0.42 \mathrm{A}$, while the current ripple of the second inductor is ${∆i}_{L2}=0.55 \mathrm{A}$. The pulse–width modulation of transistor $s_1$ denoted by ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$ works with a duty cycle of 20%, while pulse–width modulation of transistor $s_2$, denoted by ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$, works with a duty cycle of 70%. These pulse signals are phase shifted 30% of the time period between them. In Figure 15b, the converter operates with unity voltage gain, maintaining an equal voltage level of 220 V at both the input and output terminals. Under these conditions, the current ripples are ${∆i}_{L1}$= ${∆i}_{L2}=0.46 \mathrm{A}$. ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$ works with a duty cycle of 25%, while ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$ works with a duty cycle of 75%. These pulse signals are phase shifted 25% of the time period between them. In Figure 15c, the converter operates in step-up mode, increasing the voltage from 200 V to 220 V. Under these conditions, the input current ripple is ${∆i}_{L1}=0.48 \mathrm{A}$, while the current ripple of the second inductor is ${∆i}_{L2}=0.4 \mathrm{A}$. ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$ works with a duty cycle of 29%, while ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$ works with a duty cycle of 79%. These pulse signals are phase shifted 21% of the time period between them. These graphs confirm the validity of the current ripple expressions derived in the converter analysis using the proposed modulation scheme across different operating modes: step-up, unity voltage gain, and step-down.

Figure 16 presents the pulse-width modulation and voltage ripples in capacitors with the converter operating at different voltage gain conditions. The output power is 570 W with an output voltage of $V_{C2}=220 \mathrm{V}$. In Figure 16a, the converter operates in step-down mode, reducing the voltage from 250 V to 220 V. Under these conditions, the values of the voltage ripples are ${∆v}_{C1}=1 \mathrm{V}$ and ${∆v}_{C2}=0.7\mathrm{V}$. ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$ works with a duty cycle of 20%, while ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$ works with a duty cycle of 70%. These pulse signals are phase shifted 30% of the time period between them. In Figure 16b, the converter operates with unity voltage gain, maintaining equal voltage level of 220 V at both the input and output terminals. Under these conditions, the voltage ripples are ${∆v}_{C1}$= 0.5 and ${∆v}_{C2}=0.2\mathrm{V}$. ${PWM}_1$ works with a duty cycle of 25%, while ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$ works with a duty cycle of 75%. These pulse signals are phase shifted 25% of the time period between them. In Figure 16c, the converter operates in step-up mode, increasing the voltage from 200 V to 220 V. Under these conditions, the values of the voltage ripples are ${∆v}_{C1}=1.4 \mathrm{V}$ and ${∆v}_{C2}=1.1\mathrm{V}$. ${\mathrm{P}\mathrm{W}\mathrm{M}}_1$ works with a duty cycle of 29%, while ${\mathrm{P}\mathrm{W}\mathrm{M}}_2$ works with a duty cycle of 79%. These pulse signals are phase shifted 21% of the time period between them. These graphs confirm the validity of the voltage ripple expressions derived in the converter analysis using the proposed modulation scheme across different operating modes: step-up, unity voltage gain, and step-down.

To compare the performance of the APSMTO modulation proposed in this work with the STSS modulation presented in [12] and the AMTO modulation described in [13],

Table 2. Steady-state values for different modulations and operation modes of the converter.

	Step-Down Mode			Step-Up Mode
	$\mathit{E}=250 \mathbf{V},$${\mathit{V}}_{\mathit{C}2}=220$ V ${\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}}=570 \mathbf{W}$			$\mathit{E}=200 \mathbf{V},$${\mathit{V}}_{\mathit{C}2}=220 \mathbf{V}$ ${\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}}=570 \mathbf{W}$
	APSMTO with δ = 0.5 Proposed	AMTO with δ = 0.5 [13]	STSS [12]	APSMTO with δ = 0.5 Proposed	AMTO with δ = 0.5 [13]	STSS [12]
$D$	0.2	0.2	0.47	0.29	0.29	0.52
$D +$ δ	0.7	0.7	0.47	0.79	0.79	0.52
$I_{L1}$	2.4 A	2.4 A	2.5 A	3.0 A	3.0 A	3.1 A
$I_{L2}$	2.6 A	2.6 A	2.6 A	2.6 A	2.6 A	2.6 A
$V_{C1}$	94 V	94 V	250 V	60	60	200 V
$V_{C2}$	220 V	220 V	220 V	220 V	220 V	220 V
Δ$i_{L1}$	0.4 A	0.4 A	1 A	0.48 A	0.48 A	0.9 A
Δ$i_{L2}$	0.55 A	0.55 A	1 A	0.4 A	0.4 A	1 A
$\Delta v_{C1}$	1.0 V	2.4 V	5.5 V	1.4 V	3.4 V	6.2 V
Δ$v_{C2}$	0.7 V	2.4 V	5.5 V	1.1 V	3.4 V	6.2 V
$V_{stress}$	312 V	312 V	472 V	280 V	280 V	420 V

summarizes the steady-state values of the key parameters for both step-down and step-up operating modes. The results indicate that the average values of $I_{L1}$, $I_{L2}$, and $V_{C2}$ remain relatively unchanged across the different modulation strategies. However, significant reductions are observed in $V_{C1}$, $V_{stress}$, ${∆i}_{L1}$, ${∆i}_{L2}$, ${∆v}_{C1}$, and ${∆v}_{C2}$.

Table 3. Percentage reduction in parameters.

	Step-Down Mode		Step-Up Mode
${\mathit{\%}}_{\mathit{r}\mathit{e}\mathit{d}}$	APSMTO vs. STSS	APSMTO vs. AMTO	APSMTO vs. STSS	APSMTO vs. AMTO
${\%}_{red}$ $\mathrm{in} V_{C1}$	62.4%	0%	70%	0%
${\%}_{red}$ $\mathrm{in} \Delta i_{L1}$	60%	0%	46.7%	0%
${\%}_{red}$ $\mathrm{in} \Delta i_{L2}$	45%	0%	60%	0%
${\%}_{red}$ $\mathrm{in} \Delta v_{C1}$	81.8%	58.3%	77.4%	58.8%
${\%}_{red}$ $\mathrm{in} \Delta v_{C2}$	87.3%	70.8%	82.2%	67.6%
${\%}_{red}$ $\mathrm{in} V_{STRESS}$	33.9%	0%	33.3%	0%

presents the percentage reduction in these key parameters achieved by the APSMTO strategy compared to the previous SSTS and AMTO strategies. The percentage improvement is computed as

$${\%}_{red}=\left({\displaystyle \frac{x_{fv}-x_{nv}}{x_{fv}}}\right),$$

(53)

where $x_{nv}$ denotes the new values obtained using the APSMTO strategy, while $x_{fv}$ corresponds to the former values associated with the strategy being compared. These values are taken from Table 2.

According to Table 3, the percentage reduction achieved by APSMTO compared to STSS is as follows: the voltage $V_{C1}$ decreases by 62.4% in step-down mode and 70% in step-up mode; the current ripple ${∆i}_{L1}$ decreases by 60% in step-down mode and 46.7% in step-up mode; the voltage ripple ${∆v}_{C1}$ decreases by 81.8% in step-down mode and 77.4% in step-up mode; the voltage ripple ${∆v}_{C2}$ decreases by 87.3% in step-down mode and 82.2% in step-up mode; and the stress voltage $V_{STRESS}$ decreases by 33.9% in step-down mode and 33.3% in step-up mode.

On the other hand, when comparing APSMTO with AMTO, there is no reduction in parameters $V_{C1}$, $V_{stress}$, ${∆i}_{L1}$, and ${∆i}_{L2}$. However, a significant improvement is observed in voltage ripples. The voltage ripple ${∆v}_{C1}$ decreases by 58.3% in step-down mode and 58.8% in step-up mode, while ${∆v}_{C2}$ decreases by 70.8% in step-down mode and 67.6% in step-up mode.

For a general visualization of the ripple behavior in the inductor currents and the capacitor voltages, Figure 17 presents comparative plots of these ripples for the SSTS, AMTO, and APSMTO modulation methods. Here, the parameters of the prototype are considered, along with an output power of 570 W, a constant output voltage of $V_{C2}=200 \mathrm{V}$, and a time offset of $\delta =0.5$. Thus, the input voltage is varied to obtain different gain values. Theoretically, the minimum duty cycle is $D=0$, and the maximum duty is $D=0.5$, given that the proposed modulation scheme is fixed to the following rule $D+\delta \le 1$. According to (39), the range of the voltage gain is $0.5\le G\le 2$. The ripple plots are shown as a function of the voltage gain within the aforementioned interval.

Figure 17a shows the behavior of the input current ripple ${∆i}_{L1}$ across different voltage gains. The ripple behavior is identical for both the AMTO and APSMTO modulations. A considerable reduction in ripple is observed for these two modulations compared with SSTS, particularly when the converter operates with voltage gains below $G=1.25$. Figure 17b illustrates the current ripple of the second inductor ${∆i}_{L2}$, which is also identical for AMTO and APSMTO. In this case, the ripple reduction becomes more significant relative to SSTS when the converter operates with voltage gains above $G=0.75$. Figure 17c shows the voltage ripple ${∆v}_{C1}$, which exhibits a substantial reduction under APSMTO compared with the other methods. This reduction is especially pronounced for gain values between 0.75 and 1.25. Similarly, Figure 17d shows the voltage ripple of capacitor ${∆v}_{C2}$, where APSMTO again provides superior performance in the same gain range (0.75 to 1.25). Overall, these plots provide a clearer perspective on ripple behaviors, highlighting the most significant reductions, particularly in capacitor voltage ripple when the converter operates at voltage gains around unity.

Up to this point, the advantages of the proposed strategy over previous approaches have been experimentally validated. Nevertheless, certain limitations have been identified:

• The converter ratio of the converter decreases as the time offset increases according to (39).
• The proposed strategy is specifically designed for two-switch step-down/up converters.
• The benefits of this approach are most pronounced near unity gain, as in the present case, where the gain range is 0.88 to 1.1.
• The active switches operate close to the critical limits of duty cycles.

To evaluate the transient response of the converter under the proposed modulation and control scheme, stepwise changes in the load from 570 W to 285 W are applied at different voltage gain conditions, while maintaining a constant output voltage of $V_{C2}=220 \mathrm{V}$. In Figure 18a, the converter operates in step-down mode, reducing the voltage from 250 V to 220 V. Here, the average value of $i_{L1}$ changes from 1.2 A when the load is 285 W to 2.4 A when the load is 570 W. The average value of $i_{L2}$ changes from 1.3 A when the load is 285 W to 2.6 A when the load is 570 W. The average value of $v_{C1}$ is 94 V, while $v_{C2}$ is 220 V. In Figure 18b, the converter operates with unity voltage gain, maintaining an equal voltage level of 220 V at both the input and output terminals. Here, the average value of $i_{L1}$ changes from 1.4 A when the load is 285 W to 2.7 A when the load is 570 W. The average value of $i_{L2}$ changes from 1.3 A when the load is 285 W to 2.6 A when the load is 570 W. The average value of $v_{C1}$ is 73 V, while $v_{C2}$ is 220 V. In Figure 18c, the converter operates in step-up mode, increasing the voltage from 200 V to 220 V. Here, the average value of $i_{L1}$ changes from 1.5 A when the load is 285 W to 3.0 A when the load is 570 W. The average value of $i_{L2}$ changes from 1.3 A when the load is 285 W to 2.6 A when the load is 570 W. The average value of $v_{C1}$ is 60 V, while $v_{C2}$ is 220 V. These experimental graphics demonstrate that the control strategy effectively maintains the output voltage at a constant reference level despite the applied load variations.

To evaluate the converter’s ability to tolerate input voltage variations, a test was conducted in which the input voltage gradually changed from 200 V to 250 V, as observed in Figure 19, considering an output power of 570 W, and a time offset of 0.5. This emulates the voltage fluctuations typically observed in renewable energy sources, such as lithium-ion batteries. Here, the average input current $i_{L1}$ gradually changes from 2.4 A to 3.0 A. The average current of the second inductor $i_{L2}$ is maintained at 2.6 A. The voltage of the transfer capacitor $v_{C1}$ changes from 60 V to 94 V. The output voltage $v_{C2}$ stayed constant at the desired value of 220 V. This test confirms the effectiveness of the converter, along with the control algorithm and the modulation strategy in maintaining proper regulation despite variations in the source.

To assess the converter’s ability to track changes, a test was conducted with step variations in the reference voltage from 200 V to 250 V. Figure 20 shows the behavior of the state variables in response to these changes. Here, the average input current $i_{L1}$ changed from 2.3 A to 3.5 A. The average current $i_{L2}$ changed from 2.3 A to 2.9 A. The voltage of the transfer capacitor $v_{C1}$ changed from 80 V to 63 V. The output voltage $v_{C2}$ properly tracked the step variation in the voltage reference from 200 V to 250 V.

Experimental results validate the correct operation of the MNI-SDU converter when using the proposed APSMTO modulation combined with a current-mode control scheme. Furthermore, this modulation and control approach can be extended to other dual-switch step-down/up converters for voltage regulation applications, particularly in scenarios involving input source fluctuations. Non-cascaded configurations of conventional buck, boost, and buck–boost converters, based on the principles of reduced redundant power processing [21,22], can lead to the development of novel two-stage converters featuring two active switches. Both cascaded and non-cascaded converters could be driven with the APSMTO strategy, which analysis may lead to future research. It is the case of the step-up/down converter proposed in [23]. Other cases are the cascaded buck–boost converter [24] and the cascaded boost–buck converter [25]. Particularly, the cascaded boost–buck converter shares a similar structure with the MNI-SDU converter, differing primarily in the position of the transfer capacitor $C_1$. This change in the capacitor’s position allows us to reduce the voltage $V_{C1}$ in the MNI-SDU converter compared with the cascaded boost–buck converter. A lower voltage requirement directly translates into a smaller capacitor volume. The APSMTO strategy could be applied to other topologies to mitigate ripples and reduce voltage stress on the semiconductor devices. A promising direction for future work would be to analyze the performance of other converters under this strategy and compare the results with those presented in this study.

5. Conclusions

This paper presented a new switching strategy for the Modified Non-Inverting Step-Down/Up (MNI-SDU) DC–DC converter. The proposed firing sequence alters the equivalent circuits involved in the switching cycle, allowing a new set of capacitor selection equations to be derived while preserving the same averaged model and steady-state behavior as in previous operation modes. The main advantage of the proposed switching strategy (APSMTO) is that it enables a reduction in the capacitance required for a specified output voltage ripple. Simulation and experimental results obtained from a 570 W laboratory prototype confirmed the theoretical predictions. The new operation achieved a considerable reduction in the voltage ripple on both capacitors of over 58%. Additionally, the voltage stress on semiconductors and current ripples on inductors remained unchanged compared with the AMTO strategy, maintaining high efficiency and stable dynamic response.

The proposed approach thus provides a simple yet effective method to enhance power density and reduce component size in the MNI-SDU converter. These improvements make the converter more attractive for applications in battery-regulated systems, renewable energy interfaces, and compact DC microgrids, where reduced size, high efficiency, and low ripple are key design requirements.