Search Results (20)

With the continuous scaling of CMOS technology, stress engineering has become increasingly critical at advanced technology nodes, especially in tall and narrow FinFET structures. Asymmetric layout environments (such as dual-Fin structures or poly cuts) can introduce stress imbalance originating from shallow trench isolation (STI), which in turn affects device performance. In this study, TCAD simulations were performed on n-type FinFETs representative of the 10 nm technology node, with a physical gate length of 20 nm, to investigate the correlation between asymmetric stress and device drive current. As the Fin width decreases, the asymmetric stress from STI induces noticeable performance fluctuations, with the mobility enhancement under saturation bias reaching a maximum of 8.42% at W = 6 nm. Similarly, as the Fin body angle deviates from 90° and the Fin top narrows, with W_top = 6 nm and W_bottom = 8 nm, the mobility enhancement peaks at 7.65%. The simulation results confirm that STI-induced asymmetric stress has a significant impact on the Fin sidewall channel, while its effect on the top channel is minimal. To mitigate these effects, CESL stress engineering is proposed as an effective solution to amplify the top channel current, thereby reducing the influence of asymmetric stress on device performance. A CESL stress of 2.0 GPa is shown to improve device stability by approximately 20%. Full article

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR). Full article

The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this issue in DRAM technology, employing 10 nm node technology with buried channel array transistors. To evaluate the efficacy of our proposals, we utilized SILVACO for simulating various DRAM configurations. Our approach centers on two key structural optimizations: the introduction of a spherical Shallow Trench Isolation (STI) and the incorporation of a silicon nitride (Si₃N₄) layer within the spherical STI structure. These optimizations were meticulously designed to mitigate the PGE by considering several factors that are highly influential in its manifestation. To validate our approach, we conducted comprehensive simulations, comparing the PGE factors of typical DRAM structures with those of our proposed configurations. The results of our analysis strongly support the effectiveness of our proposed structural enhancements in alleviating the PGE when contrasted with conventional DRAM structures. Remarkably, our optimizations achieved a remarkable 82.4% reduction in the PGE, marking a significant breakthrough in the field of DRAM technology. By addressing the PGE challenge and substantially reducing its impact, our research contributes to the advancement of DRAM technology, offering practical solutions to enhance data integrity and reliability in the era of 10 nm node DRAM. Full article

The effects of proton irradiation on CMOS Single-Photon Avalanche Diodes (SPADs) are investigated in this article. The I–V characteristics, dark count rate (DCR), and photon detection probability (PDP) of the CMOS SPADs were measured under 30 MeV and 52 MeV proton irradiations. Two types of SPAD, with and without shallow trench isolation (STI), were designed. According to the experimental results, the leakage current, breakdown voltage, and PDP did not change after irradiation at a DDD of 2.82 × 10⁸ MeV/g, but the DCR increased significantly at five different higher voltages. The DCR increased by 506 cps at an excess voltage of 2 V and 10,846 cps at 10 V after 30 MeV proton irradiation. A γ irradiation was conducted with a TID of 10 krad (Si). The DCR after the γ irradiation increased from 256 cps to 336 cps at an excess voltage of 10 V. The comparison of the DCR after proton and γ-ray irradiation with two structures of SPAD indicates that the major increase in the DCR was due to the depletion region defects caused by proton displacement damage rather than the Si-SiO₂ interface trap generated by ionization. Full article

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain ${\beta }_0$ of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher ${\beta }_0$ of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on ${\beta }_0$ increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model. Full article

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC. Full article

The total ionizing dose sensitivity of planar 150 nm CMOS technology is evaluated by measuring the DC responses of nMOSFETs at several irradiation steps up to 125 krad(SiO₂). Different TID sensitivities are measured for transistors built with different channel dimensions and operating voltages (I/O and core). The experimental results evidence strong relations between TID sensitivity and the doping profiles in the channel. I/O transistors have the highest TID sensitivity due to their thicker gate oxide and lower bulk doping compared with core devices. In general, narrow-channel devices have the worst degradation with negative threshold voltage shifts, transconductance variations and increased subthreshold leakage currents, suggesting charge trapping in shallow trench isolation (STI). The enhanced TID tolerance of short-channel core devices is most likely related to the increased channel doping induced by the overlapping of halo implantations. Finally, transistors fabricated for low-leakage applications exhibit near insensitivity to TID due to higher bulk doping used during the fabrication to minimize the drain-to-source leakage current. Full article

This study concerns the development of a gap-fill process technology for isolating trench patterns. There are various gap-filling techniques in the case of trench patterns; nevertheless, a processing technology adopting the DED (deposition/etch/deposition) method was developed in this study. After the etch step, an Ar/O₂ (1:2) plasma treatment technology reduced the residual amount of F in the films to 0.05%. By improving the etch uniformity, the deposition uniformity after the DED process on a 12-inch flat wafer was secured within <1%, and a high-quality SiO₂ thin film with a dielectric constant of 3.97 and a breakdown field of 11.41 MV/cm was fabricated. The DED method can be used for gap-filling even in patterns with a high aspect ratio by changing process parameters, such as RF power and division of etch steps, according to the shape, depth, and CD size of the pattern. This study confirmed that a void-free gap-fill process can be developed in a trench pattern with a maximum aspect ratio of 40:1. Full article

The combined effect of total ionizing dose (TID) and electrical stress is investigated on NMOSFETs. For devices bearing both radiation and electrical stress, the threshold voltage shift is smaller than those only bearing electrical stress, indicating that the combined effect alleviates the degradation of the devices. The H bond is broken during the radiation process, which reduces the participation of H atoms in the later stage of electrical stress, thereby reducing the degradation caused by electrical stress. The positive charges of the oxide layer generated by radiation neutralize part of the tunneling electrons caused by electrical stress, and consume some of the electrons that react with the H bond, resulting in weaker degradation. In addition, the positive charges in shallow trench isolation (STI) generated by radiation create parasitic leakage paths at the interfaces of STI/Si, which increase the leakage current and reduce the positive shift of the threshold voltage. The parasitic effect generated by the positive charges of STI makes the threshold voltage of the narrow-channel device degrade more, and due to the gate edge effect, the threshold voltage of short-channel devices degrades more. Full article

The total ionizing dose (TID) effects on single-event upset (SEU) hardness are investigated for two silicon-on-insulator (SOI) static random access memories (SRAMs) with different layout structures in this paper. The contrary changing trends of TID on SEU sensitivity for 6T and 7T SOI SRAMs are observed in our experiment. After 800 krad(Si) irradiation, the SEU cross-sections of 6T SRAMs increases by 15%, while 7T SRAMs decreases by 60%. Experimental results show that the SEU cross-sections are not only affected by TID irradiation, but also strongly correlate with the layout structure of the memory cells. Theoretical analysis shows that the decrease of SEU cross-section of 7T SRAM is caused by a raised OFF-state equivalent resistance of the delay transistor N5 after TID exposure, which is because the radiation-induced charges are trapped in the shallow trench, and isolation oxide (STI) and buried oxide (BOX) enhance the carrier scattering rate of delay transistor N5. Full article

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process. Full article

Surface gravity wave interaction with a semi-infinite floating elastic plate in the presence of multiple undulations has been studied under the assumption of linearized water wave theory and small amplitude structural response. The elastic plate is modeled using the Euler-Bernoulli beam equation, whilst the multiple undulations are categorized as an array of submerged trenches or breakwaters. The numerical solution obtained in finite water depth using the boundary element method is validated with the semi-analytic solution obtained under shallow water approximation. Bragg resonance occurs due to the scattering of surface waves by an array of trenches or breakwaters irrespective of the presence of the floating semi-infinite plate. The zero-minima in wave reflection occur when the width of the trench and breakwater is an integer multiple of $0.6$ and $0.35$ times wavelength, respectively, as the number of trenches or breakwaters increases. In contrast to trenches and breakwaters in isolation, non-zero minima in wave reflection occur in the presence of a semi-infinite plate. Moreover, the number of complete cycles in trenches is less than the number of complete cycles in breakwaters, irrespective of the presence of the floating structure. The frequency of occurrence of zero minimum in wave reflection is reduced in the presence of the semi-infinite plate, and wave reflection increases with an increase in rigidity of the floating plate. Time-dependent simulation of free surface displacement and plate deflection due to multiple undulations of seabed in the presence of the semi-infinite floating plate is demonstrated in different cases. Full article

In this paper, we extend the model developed in part-I of this work to include the effects of the back-end-of-line (BEOL) metal layers and test its validity against on-wafer measurement results of SiGe heterojunction bipolar transistors (HBTs). First we modify the position dependent substrate temperature model of part-I by introducing a parameter to account for the upward heat flow through BEOL. Accordingly the coupling coefficient models for bipolar transistors with and without trench isolations are updated. The resulting modeling approach takes as inputs the dimensions of emitter fingers, shallow and deep trench isolation, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are first validated against 3D TCAD simulations including the effect of BEOL followed by validation against measured data obtained from state-of-art multifinger SiGe HBTs of different emitter geometries. Full article

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation ($c_{ij,nt}$). As a second step, using the value of $c_{ij,nt}$, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations ($c_{ij,st}$). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device ($c_{ij,dt}$) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated. Full article

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (V_t1), holding voltage (V_h) and secondary breakdown current (I_t2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the V_t1 and V_h values were closest to 21.85, and 9.27 V, respectively. The I_t2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low V_h characteristic. By removing the entire heavily doped drain-side N⁺ region, the equivalent series resistance in the drain region was increased, so that the I_t2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high V_h behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%. Full article