Search Results (899)

This paper examines whether information-theoretic complexity measures enhance industry-group return forecasting and portfolio construction within a machine-learning framework. Using daily data for 25 U.S. GICS industry groups spanning more than three decades, we augment gradient-boosted decision tree models with Shannon entropy and fuzzy entropy computed from recent return dynamics. Models are estimated at weekly, monthly, and quarterly horizons using a strictly causal rolling-window design and translated into two economically interpretable allocation rules, a maximum-profit strategy and a minimum-risk strategy. Results show that the top performing strategy, the weekly maximum-profit model augmented with Shannon entropy, achieves an accumulated return exceeding 30,000%, substantially outperforming both the baseline model and the fuzzy-entropy variant. On monthly and quarterly horizons, entropy and fuzzy entropy generate smaller but robust improvements by maintaining lower volatility and better downside protection. Industry allocations display stable and economically interpretable patterns, profit-oriented strategies concentrate primarily in cyclical and growth-sensitive industries such as semiconductors, automobiles, technology hardware, banks, and energy, while minimum-risk strategies consistently favor defensive industries including utilities, food, beverage and tobacco, real estate, and consumer staples. Overall, the results demonstrate that entropy-based complexity measures improve both economic performance and interpretability, yielding industry-rotation strategies that are simultaneously more profitable, more stable, and more transparent. Full article

As semiconductor process nodes shrink to 3 nm and beyond, traditional optical proximity correction (OPC) and resolution enhancement technologies (RETs) can no longer meet the high patterning precision needs of advanced chip manufacturing due to the sub-wavelength lithography limits. Inverse lithography technology (ILT), a key part of computational lithography, has become a critical solution for these issues. From an EDA industry perspective, this review provides an original and systematic summary of ILT’s development and applications, which helps integrate the scattered research into a clear framework for both academic and industrial use. Compared with traditional OPC, the latest ILT has three main advantages: (1) better patterning accuracy, as a result of the precise optical models that fix complex optical issues (like diffraction and interference) in advanced lithography systems; (2) a wider process window, as it optimizes mask designs by working backwards from the target wafer patterns, making lithography more stable against process changes; and (3) stronger adaptability to new lithography scenarios, such as High-NA EUV and extended DUV nodes. This review first explains ILT’s working principles (the basic concepts, mathematical formulae, and main methods like level-set and pixelated approaches) and its development history, highlighting key events that boosted its progress. It then analyzes ILT’s current application status in the industry (such as hotspot fixing, full-chip trials, and EUV-era use) and its main bottlenecks: a high computational complexity leading to long runtime, difficulties in mask manufacturing, challenges in model calibration, and a conservative market that slows large-scale adoption. Finally, it discusses promising future directions, including hybrid ILT-OPC-SMO strategies, improving model accuracy, AI/ML-driven design, GPU acceleration, multi-beam mask writer improvements, and open-source data to solve data shortage problems. By combining the latest research and industry practices, this review fills the gap of comprehensive ILT summaries that cover the principles, progress, applications, and prospects. It helps readers fully understand ILT’s technical landscape and offers practical insights for solving the key challenges, thus promoting ILT’s industrial use in advanced chip manufacturing. Full article

As the global transition toward carbon neutrality accelerates, the sustainability of power electronics has received growing attention from both academia and industry. Nevertheless, standardized methodologies for evaluating the sustainability of power electronic systems—particularly traction inverters—remain limited, largely due to the absence of comprehensive databases and unified assessment frameworks. Leveraging industrial extensive design experience, this paper presents an enhanced methodology for sustainability evaluation of traction inverters. The proposed framework combines advanced component-level modelling with multi-physics-based analysis to more accurately quantify the environmental impacts associated with different power semiconductor technologies. A Random Forest (RF)-based algorithm is employed for junction temperature (T_J) estimation, offering reliable thermal data crucial for sustainability assessment. Experimental validation on a prototype automotive inverter confirms the accuracy and robustness of the RF-based T_J estimation approach, ensuring realistic thermal–environmental coupling within the evaluation workflow. From a thermal perspective, the sizing of power electronics key components (PEKCs) is performed with high precision, enabling a more accurate estimation of power electronics-related material (PERM) usage. Combined with a preliminary CO₂-equivalent (CO₂e) emissions database, this allows sustainability assessment to be integrated directly into the design stage of the traction inverter. The effectiveness of the proposed approach is demonstrated through a comparative evaluation of three representative inverter topologies. Full article

In this paper, complementary metal-oxide semiconductor (CMOS) circuit realization of a low-pass elliptic filter of order (1 + α) is realized using the inverse follow-the-leader feedback (IFLF) topology. The transfer functions to approximate the passband and stopband ripple characteristics of the second-order elliptic low-pass filter are synthesized using the nonlinear least squares (NLS) optimization routine. The elliptic filters of orders 1.4, 1.6, and 1.8 are designed using a cross-coupled operational transconductance amplifier (OTA) in the United Microelectronics Corporation (UMC) 180 nm CMOS process. The dynamic range of the filter was found to be 49.7 dB, 52.08 dB, and 54.02 dB for an order of 1.4, 1.6, and 1.8, respectively. The circuit simulation results such as magnitude, phase, transient, and group delay plots, are validated with the MATLAB simulation plots. Monte Carlo and PVT analyses have demonstrated the accuracy and robustness of the design. The proposed approach supports quality education and industry, innovation, and infrastructure. Full article

Ammonia, as an essential chemical, plays an indispensable role in both industry and agriculture. However, the traditional Haber–Bosch technique for ammonia synthesis suffers from high energy consumption and significant CO₂ emissions. Therefore, developing an energy-efficient and eco-friendly method for ammonia production is imperative. Photoelectrochemical (PEC) nitrate reduction to ammonia has emerged as a promising green alternative, which utilizes renewable solar energy to convert nitrate into valuable ammonia, thereby contributing to nitrogen recycling and wastewater remediation. This review systematically summarizes recent advances in PEC nitrate reduction to ammonia, focusing on the rational design of efficient photocathodes with the development of semiconductor materials, cocatalysts, p–n junction and heterostructure strategies. Furthermore, the integration of photocathodes with photoanodes enables the assembly of bias-free PEC systems capable of simultaneously producing ammonia and value-added chemicals, demonstrating the potential for scalable solar-driven ammonia synthesis. The mechanistic studies and future research directions are also discussed. The review aims to offer valuable insights and promote the further development of PEC nitrate reduction to ammonia. Full article

Food fraud, particularly in the olive oil sector, represents a pressing concern within the agri-food industry, with implications for consumer trust and product authenticity. Certified products like Protected Designation of Origin (PDO) Extra Virgin Olive Oil (EVOO) are premium products that undergo strict quality controls, must comply with specific production regulations, and generally have a higher market price. These characteristics make them particularly vulnerable to economically motivated adulteration. In this study, the adulteration of PDO EVOO with Olive Pomace Oil (POO) and Olive Oil (OO) was investigated through a combined analytical approach. A traditional technique, gas chromatography–mass spectrometry (GC-MS) combined with solid-phase microextraction (SPME), was employed alongside an innovative method based on an electronic nose equipped with metal oxide semiconductor (MOX) sensors. GC-MS analysis enabled the identification of characteristic volatile compounds, providing a detailed chemical fingerprint of the different oil samples. Concurrently, the MOX sensor array successfully detected variations in the volatile profiles released by the adulterated oils, demonstrating its potential as a rapid and cost-effective screening tool. The complementary use of both techniques highlighted the reliability of MOX sensors in differentiating authentic PDO EVOO from adulterated samples and underscored their applicability in routine quality control and fraud prevention strategies. Full article

With the rapid development of semiconductor manufacturing technology, methods to effectively control the production process, reduce variation in the manufacturing process, and improve the yield rate represent important competitive factors for wafer factories. Wafer bin maps, a method for characterizing wafer defect patterns, provide valuable information for engineers to quickly identify potential root causes through accurate pattern recognition. Vision-based deep learning approaches rely on visual patterns to achieve robust performance. However, they rarely exploit the rich semantic information embedded in defect descriptions, limiting interpretability and generalization. To address this gap, we propose YOLO-LA, a lightweight prototype-based vision–language alignment framework that integrates a pretrained frozen YOLO backbone with a frozen text encoder to enhance wafer defect recognition. A learnable projection head is introduced to map visual features into a shared embedding space, enabling classification through cosine similarity Experimental results on the WM-811K dataset demonstrate that YOLO-LA consistently improves classification accuracy across different backbones while introducing minimal additional parameters. In particular, YOLOv12 achieves the fastest speed while maintaining competitive accuracy, whereas YOLOv10 benefits most from semantic prototype alignment. The proposed framework is lightweight and suitable for real-time industrial wafer inspection systems. Full article

Accurate classification of wafer map defect patterns is crucial for enhancing yield in semiconductor manufacturing. To address the problem of deep learning model over-fitting to label noise present in real industrial data, this study proposes a fuzzy logic-based framework for identifying both single and composite-type defect patterns. To demonstrate the robustness of our approach, we utilized the public dataset WM-811K and developed a Fuzzy Inference System (FIS) that leverages quantitative metrics such as the Center Zone Density (CZD). Data quality was also improved through preprocessing steps, including resolving class imbalances and refining labels via expert review. The performance of the proposed FIS was evaluated against a quantitative feature-based neural network, an FIS-neural network hybrid, and a CNN model. Experimental results showed that in single-pattern classification, the proposed FIS model achieved the highest accuracy of 99.20%, followed by the feature-based neural network (91.63%), the FIS-neural network hybrid model (88.55%), and the CNN (81.06%). These results prove that the proposed FIS approach maintains high classification accuracy while offering the advantages of interpretability and rule-based adjustability. This framework presents a practical solution that can effectively integrate domain knowledge to reduce the risk of overfitting in data environments with imperfect labels. Full article

Gas-assisted coaxial electrospinning (GACES), a simple and versatile technique for the large-scale fabrication of coaxial nanofiber membranes, possesses significant industrial potential across advanced manufacturing sectors including semiconductors—particularly for fabricating high-precision dielectric layers, high-uniformity encapsulation materials, and flexible semiconductor substrates requiring tailored core-shell architectures. However, there is still a lack of relevant studies on the effective regulation of the core-shell structures of coaxial fibers based on GACES, which greatly limits the batch preparation and wide application of coaxial fibers. Finite element simulation analysis of the flow field and development of the coaxial jet mechanics model with a gas-driven flow field—two key methodologies in this study—successfully uncovered the influence mechanism of gas-assisted flow fields on the core-shell structures of coaxial nanofibers. By adjusting the gas-assisted flow fields parameters, we reduced the total diameter of coaxial fibers by 47.33% (average fiber diameter: 334.12 ± 16.29 nm → 175.98 ± 1.18 nm), decreased the shell thickness by 72.98%, increased the core-shell ratio by 289% (core-shell ratio: 0.49 → 1.91), and improved the uniformity of the total diameter distribution of coaxial fibers by 30.64%. This study delivers a practical conceptual framework and robust experimental underpinnings for the scalable fabrication of coaxial nanofiber membranes with controllable core-shell structures, thereby promoting their practical application in semiconductor devices such as ultra-thin dielectric layers, precisely structured encapsulation materials, and high-uniformity templates for nanoscale circuit patterning. Full article

A novel two-in-one sensor for both carbon dioxide and hydrogen detection has been obtained based on a hybrid heterostructure. It consists of a 30 nm thick TiO₂ nanocrystalline film grown by atomic layer deposition (ALD), thermally annealed at 610 °C, and subsequently coated with bimetallic AgAu nanoparticles and covered with a PV4D4 nanolayer, which was thermally treated at 430 °C. Two types of gas response behaviors have been registered, as n-type for hydrogen gas and p-type semiconductor behavior for carbon dioxide gas detection. The highest response for carbon dioxide has been registered at an operating temperature of 150 °C with a value of 130%, while the highest response for hydrogen gas was registered at 350 °C with a value of 230%, although it also attained a relatively good gas selectivity at 150 °C. It is considered that a thermal annealing temperature of 610 °C is better for the properties of TiO₂ nanofilms, since it enhances gas sensor sensitivity too. Polymer coating on top is also believed to contribute to a higher influence on selectivity of the sensor structure. Accordingly, to our previous research where PV4D4 has been annealed at 450 °C, in this research paper, a lower temperature of 430 °C for annealing has been used, and thus another ratio of cyclocages and cyclorings has been obtained. Knowing that the polymer acts like a sieve atop the sensor structure, in this study it offers increased selectivity and sensitivity towards carbon dioxide gas detection, as well as maintaining a relatively increased selectivity for hydrogen gas detection, which works as expected with Ag and Au bimetallic nanoparticles on the surface of the sensing structure. The results obtained are highly important for biomedical and environmental applications, as well as for further development of the sensor industry, considering the high potential of two-in-one sensors. A carbon dioxide detector could be used for assessing respiratory markers in patients and monitoring the quality of the environment, while hydrogen could be used for both monitoring lactose intolerance and concentrations in cases of therapeutic gas, as well as monitoring the safe handling of various concentrations. Full article

The integration of operational technology (OT) and information technology (IT) within the Industrial Internet of Things (IIoT) has posed prominent security challenges for resource-constrained devices. Existing authentication architectures often suffer from critical vulnerabilities: one is their reliance on centralized trusted third parties, which creates single points of failure; the other is their use of static credentials like biometrics, which pose severe privacy risks if compromised. To address these limitations, this paper proposes DLR-Auth, which combines chaotic synchronization of semiconductor superlattice physically unclonable functions (SSL-PUFs) with Shamir’s secret sharing (SSS) to enable decentralized registration and revocable templates. Notably, DLR-Auth is a two-party authentication framework that removes the need for a separate online registration authority that operates directly between a user device ($U{D}_i$) and a server (S). In our setting, the server S still acts as the central relying party and hardware authority embedding the matched SSL-PUF module. The protocol also includes an efficient multi-access mechanism optimized for high-frequency interactions. Formal security analysis with the Real-or-Random (ROR) model proves the semantic security of the session key, while performance evaluations demonstrate that DLR-Auth has significant advantages in computational and communication efficiency. DLR-Auth thus offers a robust, scalable, lightweight solution for next-generation secure IIoT systems. Full article

Semiconductor wafer manufacturing is one of the most complex and data-intensive processes in the industry, encompassing the front-end (FEOL), middle-end (MOL), and back-end (BEOL) stages, involving thousands of interdependent processes. Each stage can introduce potential variability, thereby reducing yield, making metrology and inspection crucial for process control. However, due to capacity, cost, and destructive testing constraints, exhaustive metrology for every wafer or die is impractical. Therefore, this study aims to introduce sampling strategies that have evolved to balance the accuracy, risk, and efficiency of measurement allocation. This review presents a literature review of static, adaptive, and dynamic sampling and discusses recent intelligent sampling techniques. The results show that traditional static sampling provides fixed, rule-based inspection schemes that ensure comparability and compliance but lack responsiveness to process variations. Adaptive sampling introduces flexibility, allowing measurement density to be adjusted based on detected drift, anomalies, or statistical control limits. Building on this, dynamic sampling represents a paradigm shift towards predictive, real-time decision-making driven by machine learning, risk analysis, and digital twin integration. The dynamic framework continuously assesses process uncertainties and prioritizes metrology to maximize information gain, thereby significantly reducing metrology workload without impacting yield or quality. Static, adaptive, and dynamic sampling together constitute a continuous evolution from deterministic control to self-optimizing intelligence. As semiconductor nodes move towards sub-3 nm, this intelligent sampling technology is crucial for maintaining yield, cost competitiveness, and process flexibility in autonomous, data-centric wafer fabs. Full article

Wafer-level thin-film stress measurement is essential for reliable semiconductor fabrication. However, existing techniques present limitations in practice. Interferometry achieves high precision but at a cost that becomes prohibitive for large wafers. Meanwhile laser-scanning systems are more affordable but can only provide sparse data points. This work develops a phase-measuring deflectometry (PMD) system to bridge this gap and deliver a full-field solution for wafer stress mapping. The implementation addresses three key challenges in adapting PMD. First, screen positioning and orientation are refined using an inverse bundle-adjustment approach, which performs multi-parameter optimization without re-optimizing the camera model and simultaneously uses residuals to quantify screen deformation. Second, a backward-propagation ray-tracing framework benchmarks two iterative strategies to resolve the slope-height ambiguity which is a fundamental challenge in PMD caused by the absence of a fixed optical center on the source side. The reprojection constraint strategy is selected for its superior convergence precision. Third, this strategy is integrated with regional wavefront reconstruction based on Hermite interpolation to effectively eliminate edge artifacts. Experimental results demonstrate a peak-to-valley error in the reconstructed topography of 0.48 µm for a spherical mirror with a radius of 500 mm. The practical utility of the system is confirmed through curvature mapping of a 12-inch patterned wafer and further validated by stress measurements on an 8-inch bare wafer, which show less than 5% deviation from industry-standard instrumentation. These results validate the proposed PMD method as an accurate and cost-effective approach for production-scale thin-film stress inspection. Full article

With the rapid development of the photovoltaic (PV) and semiconductor fields, the reserves of traditional high-purity quartz raw materials can no longer meet the demands of various industries, creating an urgent need to develop new types of high-purity quartz feedstock. In this study, three groups of vein quartz samples from different mining areas were subjected to calcination at 950 °C for 2 h. The impurity states of the vein quartz before and after calcination were characterized using XRD, ICP, Raman and XRF. The migration behavior of metal cations in vein quartz under high-temperature conditions was systematically investigated, and the structural changes in the vein quartz before and after calcination were discussed from the perspectives of impurity element distribution and phase transformation. The results demonstrate that impurity cations in vein quartz migrate from the interior to the surface of the material under high-temperature environments. Quantitative ICP analysis of the inner and outer layers of the quartz samples before and after calcination revealed that, among the three groups, the surface impurity cation content of the sample with the most pronounced migration effect reached four times that of its internal structure. Combined with other characterization techniques, it was confirmed that after the cation migration process, the vein quartz samples exhibited a layered structure from the surface to the interior: a hematite mineralized layer, a high lattice impurity layer, and a low lattice impurity layer. This indicates that high-purity vein quartz with low lattice impurity content can be obtained by subjecting quartz to high-temperature calcination and subsequently removing the mineralized layer and the surface high lattice impurity layer. Consequently, vein quartz of ordinary quality can also be converted into high-purity quartz raw material of 4N grade or higher through the processes of cation migration and tailing removal. Full article

Transistor-level Integrated Circuit (IC) design is fundamental to modern electronics, yet it remains one of the most expertise-intensive and time-consuming stages of chip development. As circuit complexity continues to rise, the need to automate this low-level design process has become critical to sustaining innovation and productivity across the semiconductor industry. This study presents a fully automated methodology for transistor-level IC design using a novel framework that integrates Grammatical Evolution (GE) with Cadence SKILL code. Beyond automation, the framework explicitly examines how symmetry and asymmetry shape the evolutionary search space and resulting circuit structures. To address the time-consuming and expertise-intensive nature of conventional integrated circuit design, the framework automates the synthesis of both digital and analogue circuits without requiring prior domain knowledge. A specialised attribute grammar (AG) evolves circuit topology and sizing, with performance assessed by a multi-objective fitness function. Symmetry is analysed at three levels: (i) domain-level structural dualities (e.g., NAND/NOR mirror topologies and PMOS/NMOS exchanges), (ii) objective-level symmetries created by logic threshold settings, and (iii) representational symmetries managed through grammatical constraints that preserve valid connectivity while avoiding redundant isomorphs. Validation was carried out on universal logic gates (NAND and NOR) at multiple logic thresholds, as well as on a temperature sensor. Under stricter thresholds, the evolved logic gates display emergent duality, converging to mirror-image transistor configurations; relaxed thresholds increase symmetric plateaus and slow convergence. The evolved logic gates achieve superior performance over conventional Complementary Metal–Oxide–Semiconductor (CMOS), Transmission Gate Logic (TGL), and Gate Diffusion Input (GDI) implementations, demonstrating lower power consumption, a reduced Power–Delay Product (PDP), and fewer transistors. Similarly, the evolved temperature sensor exhibits improved sensitivity, reduced power, and Integral Nonlinearity (INL), and a smaller area compared to the conventional Proportional to Absolute Temperature (PTAT) or “gold” circuit, without requiring resistors. The analogue design further demonstrates beneficial asymmetry in device roles, breaking canonical structures to achieve higher performance. Across all case studies, the evolved designs matched or outperformed their manually designed counterparts, demonstrating that this GE-based approach provides a scalable and effective path toward fully automated, symmetry-aware integrated circuit synthesis. Full article