Search Results (1,994)

Accurate gas analysis plays a critical role in aerospace missions, including spacecraft safety assurance, crew health monitoring, and deep-space scientific exploration. Although conventional gas chromatography (GC) techniques are well established, their large size, high power consumption, and long analysis time limit their applicability in modern aerospace missions that require miniaturized, low-power, and highly integrated analytical systems. The development of microelectromechanical systems (MEMS) technology provides an effective pathway for the miniaturization of gas chromatography. MEMS-based micro gas chromatography columns enable the integration of meter-scale separation channels onto centimeter-scale chips through micro- and nanofabrication techniques, significantly reducing system volume and power consumption while improving analysis speed and integration capability. Compared with conventional GC systems, MEMS µGC exhibits clear advantages in size, weight, energy efficiency, and response time. This review systematically summarizes the fundamentals, structural designs, fabrication processes, and stationary phase preparation of MEMS micro gas chromatography columns. Representative aerospace application cases along with related experimental and engineering validation studies are highlighted; we re-evaluate these systems using Technology Readiness Levels (TRL) to distinguish flight heritage from concept demonstrations and propose a standardized validation roadmap for environmental reliability. In addition, key technical challenges for aerospace deployment are discussed. This work aims to provide a useful reference for the development of aerospace gas analysis systems and the engineering application of MEMS-based technologies. Full article

Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration. Full article

This paper presents an experimental framework that allows damage identification and retrofitting assessment in reinforced concrete (RC) beam with implemented piezoelectric lead zirconate titanate (PZT) sensors embedded into the concrete matrix. The study was conducted with concrete prepared from 30% refuse-derived fuel (RDF) fly ash and 70% cement as part of research on sustainable materials for structural health monitoring (SHM). Electromechanical impedance (EMI) was employed for detecting structural degradation, with progressive damage and evaluation of recovery effects made using root-mean-square deviation (RMSD) and conductance changes. Concrete beam specimens with dimensions of 700 mm × 150 mm × 150 mm and embedded with 10 mm × 10 mm × 0.2 mm PZT sensors were cast and later subjected to three damage stages: concrete chipping (Damage I), 50% steel bar cutting (Damage II), and 100% steel bar cutting (Damage III). Three retrofitting stages were adopted: reinforcement welding (Retrofitting I and II), and concrete patching (Retrofitting III). The results demonstrated that the embedded PZT sensors with EMI and RMSD analytics represent a powerful technique for early damage diagnosis, reserved retrofitting assessment, and proactive infrastructure maintenance. The combination of SHM systems and sustainable retrofitting strategies can be a promising path toward resilient and smart civil infrastructure. Full article

Background/Objectives: Ulcerative colitis (UC) is an inflammatory bowel disease and a major cause of ulcers and chronic inflammation in the colon and rectum. Recurring symptoms include abdominal pain, rectal bleeding, and diarrhoea, and patients with UC are at a higher risk of developing comorbidities such as colorectal cancer and poor mental health. In UC, the decreased diversity and changed metabolic profile of gut microbiota, along with a diminished mucus layer, leads to disruption of the underlying epithelial barrier, with an ensuing excessive and detrimental inflammatory response. Treatment options currently rely on drugs that reduce the inflammation, but less emphasis has been placed on improving the resilience of the epithelial barrier. Macrolide antibiotics exhibit epithelial barrier-enhancing capacities unrelated to their antibacterial properties. Methods: We investigated two novel barriolides, macrolides with reduced antibacterial effects in common bacterial strains. Gut epithelial cell barrier resistance in the Caco-2 cell line, with and without co-culture with mucus-producing HT-29 cells, was increased when treated with barriolides. Using ^AXGut-on-Chip technology with inflammatory cytokine-stimulated Caco-2/HT-29 co-cultures, the effectiveness of the barriolides was confirmed. Lastly, we reveal the barrier-enhancing and inflammation-reducing effects of the barriolides in a dextran-sulphate sodium (DSS)-induced colitis mouse model. Results: We show the predictive power of the novel ^AXGut-on-Chip system and the effectiveness of the novel barriolides. Indications include reduced inflammatory response, increased epithelial barrier and decreased overall clinical score. Conclusions: The results of this study indicate the notion that barriolides could be used as a treatment option for UC. Full article

Vertical cavity surface emitting lasers (VCSELs) have shown great potential in high-speed communication, quantum information processing, and 3D sensing due to their excellent beam quality and low power consumption. However, generating high-purity and controllable circularly polarized light usually requires external optical components such as quarter-wave plates, which undoubtedly increases system complexity and volume, hindering chip-level integration. To address this issue, we propose a monolithic integration scheme that directly integrates a custom-designed double-layer asymmetric metasurface onto the upper distributed Bragg reflector of a chiral VCSEL. This metasurface consists of a rotated GaAs elliptical nanocolumn array and an anisotropic grating above it. By precisely controlling the relative orientation between the two, the in-plane symmetry of the structure is effectively broken, introducing a significant optical chirality response at a wavelength of 1550 nm. Numerical simulations show that this structure can achieve a near 100% high reflectivity for the left circularly polarized light (LCP), while suppressing the reflectivity of the right circularly polarized light (RCP) to approximately 33%, thereby obtaining an efficient in-cavity circular polarization selection function. Based on this, the proposed VCSEL can directly emit high-purity RCP without any external polarization control components. This compact circularly polarized laser source provides a key solution for achieving the next generation of highly integrated photonic chips and will have a profound impact on frontier fields such as spin optics, secure communication, and chip-level quantum light sources. Full article

Epileptic seizures arise from abnormally synchronized neural activity and remain a major global health challenge, affecting more than 50 million people worldwide. Despite advances in pharmacological interventions, a significant proportion of patients continue to experience uncontrolled seizures, underscoring the need for alternative neuromodulation strategies. Rhythmic neural entrainment has recently emerged as a promising mechanism for disrupting pathological synchrony, but most existing systems rely on complex analog electronics or high-power stimulation hardware. This study investigates a proof-of-concept digital custom-designed chip that generates a stable 6 Hz oscillation capable of imposing a stable rhythmic pattern onto digitized seizure-like EEG dynamics. Using a publicly available EEG seizure dataset, we extracted and averaged analog seizure waveforms, digitized them to emulate neural front-ends, and directly interfaced the digitized signals with digital output recordings acquired from the chip using a Saleae Logic analyser. The chip’s pulse train was resampled and low-pass-reconstructed to produce an analog 6 Hz waveform, allowing direct comparison between seizure morphology, its digitized representation, and the entrained output. Frequency-domain and time-domain analyses demonstrate that the chip imposes a narrow-band 6 Hz rhythm that overrides the broadband spectral profile of seizure activity. These results provide a proof-of-concept for low-power digital custom-designed entrainment as a potential pathway toward simplified, wearable neuromodulation device for future healthcare diagnostics. Full article

Convolutional Neural Networks (CNNs) generally suffer from excessive computational overhead, high resource consumption, and complex network structures, which severely restrict the deployment on microprocessor chips. Existing related accelerators only have an energy efficiency ratio of 2.32–6.5925 GOPs/W, making it difficult to meet the low-power requirements of embedded application scenarios. To address these issues, this paper proposes a low-power and high-energy-efficiency CNN accelerator architecture based on a central processing unit (CPU) and an Application-Specific Integrated Circuit (ASIC) heterogeneous computing architecture, adopting an operator-fused systolic array algorithm with the YOLOv5n target detection network as the application benchmark. It integrates a 2D systolic array with Conv-BN fusion technology to achieve deep operator fusion of convolution, batch normalization and activation functions; optimizes the RISC-V core to reduce resource usage; and adopts a locking mechanism and a prefetching strategy for the asynchronous platform to ensure operational stability. Experiments on the Nexys Video development board show that the architecture achieves 20.6 GFLOPs of computational performance, 1.96 W of power consumption, and 10.46 GOPs/W of energy efficiency ratio, which is 58–350% higher than existing mainstream accelerators, thus demonstrating excellent potential for embedded deployment. Full article

Focusing on the challenges posed by the strong randomness, weak manifestation, and difficulty in diagnosing intermittent faults (IFs) in high-density integrated circuits (HDICs)—often induced by bonding wire defects—this paper takes the GPIO interfaces of a typical DSP chip as the research object. It systematically analyzes the response characteristics of intermittent short-circuit and open-circuit faults and proposes a hybrid intelligent diagnosis method based on the Sparrow Search Algorithm-optimized Variational Mode Decomposition and Attention-based Support Vector Machine (SSA–VMD–Attention–SVM). A dedicated fault injection circuit is designed to accurately replicate IFs and acquire the power supply current response signals. The Sparrow Search Algorithm (SSA) is employed to adaptively optimize the parameters of Variational Mode Decomposition (VMD) for effective extraction of frequency-domain features from fault signals. A three-level attention mechanism is introduced to adaptively weight multi-domain features, thereby highlighting the key fault components. Finally, the Support Vector Machine (SVM) is utilized to achieve high-precision fault classification under small-sample conditions. Experimental results demonstrate that the proposed method achieves a diagnostic accuracy of 97.78% for intermittent short-circuit and open-circuit faults in the GPIO interfaces of the DSP chip, significantly outperforming traditional methods and exhibiting notable advantages in terms of diagnostic accuracy, robustness, and interpretability. Full article

This work presents a 6T-SRAM-based in-memory computing (IMC) system fabricated in a 180 nm CMOS technology. A total of 128 integrated polysilicon R2R-DACs for fully analog wordline control and performance analysis are integrated into the system. The proposed architecture enables analog computation directly inside the memory array and introduces a compact 1-bit per-column comparator scheme for energy-efficient classification without requiring ADCs. A dedicated pull-down-dominant SRAM sizing and an analog activation scheme ensure stable analog discharge behavior and precise control of the computation through time-dependent bitline dynamics. The system integrates a complete sensor front-end, which allows real eddy current data to be classified directly on-chip. Measurements demonstrate a performance density of 3.2 TOPS/mm², a simulated energy efficiency of 45 TOPS/W at 50 MHz, and a measured efficiency of 3.4 TOPS/W at 5 MHz on silicon. The implemented online training mechanism further improves classification accuracy by adapting the SRAM cell states during operation. These results highlight the suitability of the presented IMC architecture for compact, low-power edge intelligence and sensor-driven machine learning applications. Full article

Peptide arrays represent a powerful tool for investigating a wide application field for biomedical questions. This review summarizes recent applications of peptide chips in oncology, with a focus on tumor microenvironment, metastasis, and drug mechanism of action for various cancer types. These high-throughput platforms enable the simultaneous screening of thousands of peptides. We report on recent achievements in peptide array technology for tumor microenvironments, an enhanced ability to decipher complex cancer-related signaling pathways, and characterization of cell-adhesion-mediating peptides. Furthermore, we highlight the applications in high-throughput drug screenings for development of immune therapies, e.g., the development of novel neoantigen therapies of glioblastoma. Moreover, epigenetic profiling using peptide arrays has uncovered new therapeutic targets across various cancer types with clinical impact. In conclusion, we discuss artificial intelligence-driven peptide array analysis as a tool to determine tumor origin and metastatic state, potentially transforming diagnostic approaches. These innovations promise to accelerate the development of precision cancer approaches. Full article

We propose an external-cavity laser that combines wide tunability with narrow linewidth. The design utilizes a low-loss Si₃N₄ waveguide and a thermally tuned cascaded triple-ring resonator to enable continuous wavelength tuning. The numerical simulations indicate that the proposed laser exhibits a tuning range of 64 nm with a sub-kHz linewidth, an SMSR of more than 80 dB, an output power of 24 mW and a linewidth of 193 Hz at 1550 nm. Furthermore, we perform comparative system-level simulations using QPSK and 16QAM coherent optical fiber links at 50 Gbaud over 100 km. Under identical conditions, when the laser linewidth is reduced from 1 MHz level to 193 Hz, the BER of 16QAM decreases from 1.5 × 10⁻³ to 5.3 × 10⁻⁵. These results indicate that a narrow linewidth effectively mitigates phase noise degradation in high-order modulation formats. With its narrow linewidth, wide tuning range, high SMSR, and high output power, this laser serves as a promising on-chip light source for high-resolution sensing and coherent optical communications. Full article

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions. Full article

The prefetcher is one of the key performance subsystems in RISC-V processors, and its design can significantly enhance memory access efficiency, reduce latency, and improve overall processor performance. This paper conducts in-depth research on the design methods of the prefetcher for RISC-V processors and proposes a practical prefetcher implementation scheme that balances performance and usability. The hybrid prefetching technology proposed in this scheme, on the basis of integrating two classic modes, automatic hardware prefetching and software-prefetch instructions, introduces a software template prefetcher and elaborates on its specific implementation logic in detail. For the hardware prefetcher, this paper further proposes a hierarchical prefetching strategy based on the cache hierarchical architecture and clarifies the design methods of the prefetcher corresponding to each level of cache. This design balances prediction accuracy, performance, power consumption, and design complexity. It employs different prefetching strategies and algorithms to achieve efficient memory access, thus boosting the processor’s overall performance. Both the processor and the prefetcher are designed using Verilog HDL and the implementation and verification are completed on the FPGA prototype verification platform, while the design and implementation of the 12 nm processor chip are carried out. The resulting processor core occupies an area of 5.128 mm². Performance comparison between the processor equipped with this prefetcher and Xuantie C908 and Xuantie C910 shows that on the FPGA platform, the performance of this processor is improved by 25% to 35.8% compared with the comparison objects. In addition, when the processor with the prefetcher enabled is compared with that with the prefetcher disabled, it is shown that the processor performance can be improved by 25.67% to 61%. Full article

Electromagnetic flowmeters face significant challenges in measuring complex fluids, characterized by weak flow signals and severe noise interference. Conventional solutions, such as dual-frequency rectangular wave excitation, suffer from multiple drawbacks including rich harmonic components, high electromagnetic noise during switching transitions, a propensity for resonance which shortens stabilization time, reduced sampling windows, and complex circuit implementation. Similarly, traditional single-frequency excitation struggles to balance zero stability with the suppression of slurry noise. To address these limitations, this paper proposes a novel converter design based on dual-frequency sinusoidal wave excitation. A pure hardware circuit is used to generate the composite excitation signal, which superimposes low-frequency and high-frequency components. This approach eliminates the need for a master control chip in signal generation, thereby reducing both circuit complexity and computational resource allocation. The signal processing chain employs a technique of “high-order Butterworth separation filtering combined with synchronous demodulation,” effectively suppressing power frequency, orthogonal, and in-phase interference, achieving an improvement in interference rejection by approximately three orders of magnitude (1000×). Experimental results show that the proposed converter featured simplified circuitry, achieved a measurement accuracy of class 0.5, and validated the overall feasibility of the scheme. Full article

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption. Full article