Search Results (27)

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications. Full article

Optimizing charge transport in organic semiconductors is crucial for advancing next-generation optoelectronic devices. The performance of organic field-effect transistors (OFETs) is significantly influenced by the alignment of films in the channel direction and the quality of the dielectric surface, which should be uniform, smooth, and free of charge-trapping defects. Our study reports the enhancement of OFET performance using large-area, uniform, and oriented thin films of regioregular poly[3-hexylthiophene] (RR-P3HT), prepared via the Floating Film Transfer Method (FTM) on octadecyltrichlorosilane (OTS) passivated SiO₂ surfaces. SiO₂ surfaces inherently possess dangling bonds that act as charge traps, but these can be effectively passivated through optimized surface treatments. OTS treatment has improved the optical anisotropy of thin films and the surface wettability of SiO₂. Notably, using octadecene as a solvent during OTS passivation, as opposed to toluene, resulted in a significant enhancement of charge carrier transport. Specifically, passivation with OTS-F (10 mM OTS in octadecene at 100 °C for 48 h) led to a >150 times increase in mobility and a reduction in threshold voltage compared to OTS-A (5 mM OTS in toluene for 12 h at room temperature). Under optimal conditions, these FTM-processed RR-P3HT films achieved the best device performance, with a saturated mobility (μ_sat) of 0.18 cm²V⁻¹s⁻¹. Full article

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory. Full article

Three-dimensional printing (3DP) has emerged as a promising method for creating intricate scaffold designs. This study assessed three 3DP scaffold designs fabricated using biodegradable poly(lactic) acid (PLA) through fused deposition modelling (FDM): mesh, two channels (2C), and four channels (4C). To address the limitations of PLA, such as hydrophobic properties and poor cell attachment, a post-fabrication modification technique employing Polyelectrolyte Multilayers (PEMs) coating was implemented. The scaffolds underwent aminolysis followed by coating with SiCHA nanopowders dispersed in hyaluronic acid and collagen type I, and finally crosslinked the outermost coated layers with EDC/NHS solution to complete the hybrid scaffold production. The study employed rotating wall vessels (RWVs) to investigate how simulating microgravity affects cell proliferation and differentiation. Human mesenchymal stem cells (hMSCs) cultured on these scaffolds using proliferation medium (PM) and osteogenic media (OM), subjected to static (TCP) and dynamic (RWVs) conditions for 21 days, revealed superior performance of 4C hybrid scaffolds, particularly in OM. Compared to commercial hydroxyapatite scaffolds, these hybrid scaffolds demonstrated enhanced cell activity and survival. The pre-vascularisation concept on 4C hybrid scaffolds showed the proliferation of both HUVECs and hMSCs throughout the scaffolds, with a positive expression of osteogenic and angiogenic markers at the early stages. Full article

This study evaluated the use of silica/poly(tetrahydrofuran)/poly(ε-caprolactone) (SiO₂/PTHF/PCL-diCOOH) 3D-printed scaffolds, with channel sizes of either 200 (SC-200) or 500 (SC-500) µm, as biomaterials to support the chondrogenesis of sheep bone marrow stem cells (oBMSC), under in vitro conditions. The objective was to validate the potential use of SiO₂/PTHF/PCL-diCOOH for prospective in vivo ovine studies. The behaviour of oBMSC, with and without the use of exogenous growth factors, on SiO₂/PTHF/PCL-diCOOH scaffolds was investigated by analysing cell attachment, viability, proliferation, morphology, expression of chondrogenic genes (RT-qPCR), deposition of aggrecan, collagen II, and collagen I (immunohistochemistry), and quantification of sulphated glycosaminoglycans (GAGs). The results showed that all the scaffolds supported cell attachment and proliferation with upregulation of chondrogenic markers and the deposition of a cartilage extracellular matrix (collagen II and aggrecan). Notably, SC-200 showed superior performance in terms of cartilage gene expression. These findings demonstrated that SiO₂/PTHF/PCL-diCOOH with 200 µm pore size are optimal for promoting chondrogenic differentiation of oBMSC, even without the use of growth factors. Full article

Electrical characteristics with various program temperatures (T_PGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the T_PGM up to 120 °C and the read temperature (T_READ) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (I_BL) and threshold voltage (V_T). The V_T shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔV_T,CL) component and the poly-Si GB (ΔV_T,GB) component. The extracted ΔV_T,GB increases at higher T_PGM due to the reduced GB potential barrier. Additionally, the ΔV_T,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (X_GB) and the bit line voltage (V_BL). Full article

In this study, we enhance the synaptic behavior of artificial synaptic transistors by utilizing nanowire (NW)-type polysilicon channel structures. The high surface-to-volume ratio of the NW channels enables efficient modulation of the channel conductance, which is interpreted as the synaptic weight. As a result, NW-type synaptic transistors exhibit a larger hysteresis window compared to film-type synaptic transistors, even within the same gate voltage sweeping range. Moreover, NW-type synaptic transistors demonstrate superior short-term facilitation and long-term memory transition compared with film-type ones, as evidenced by the measured paired-pulse facilitation and excitatory post-synaptic current characteristics at varying frequencies and pulse numbers. Additionally, we observed gradual potentiation/depression characteristics, making these artificial synapses applicable to artificial neural networks. Furthermore, the NW-type synaptic transistors exhibit improved Modified National Institute of Standards and Technology pattern recognition rate of 91.2%. In conclusion, NW structure channels are expected to be a promising technology for next-generation artificial intelligence (AI) semiconductors, and the integration of NW structure channels has significant potential to advance AI semiconductor technology. Full article

In this study, we investigated the gas-sensing mechanism in bottom-gate organic field-effect transistors (OFETs) using poly(triarylamine) (PTAA). A comparison of different device architectures revealed that the top-contact structure exhibited superior gas-sensing performance in terms of field-effect mobility and sensitivity. The thickness of the active layer played a critical role in enhancing these parameters in the top-contact structure. Moreover, the distance and pathway for charge carriers to reach the active channel were found to significantly influence the gas response. Additionally, the surface treatment of the SiO₂ dielectric with hydrophobic self-assembled mono-layers led to further improvement in the performance of the OFETs and gas sensors by effectively passivating the silanol groups. Under optimal conditions, our PTAA-based gas sensors achieved an exceptionally high response (>200%/ppm) towards NO₂. These findings highlight the importance of device and interface engineering for optimizing gas-sensing properties in amorphous polymer semiconductors, offering valuable insights for the design of advanced gas sensors. Full article

Recent years have shown a growing interest in the application of membranes exhibiting magnetic properties in various separation processes. The aim of this review is to provide an in-depth overview of magnetic membranes that can be successfully applied for gas separation, pervaporation, ultrafiltration, nanofiltration, adsorption, electrodialysis, and reverse osmosis. Based on the comparison of the efficiency of these separation processes using magnetic and non-magnetic membranes, it has been shown that magnetic particles used as fillers in polymer composite membranes can significantly improve the efficiency of separation of both gaseous and liquid mixtures. This observed separation enhancement is due to the variation of magnetic susceptibility of different molecules and distinct interactions with dispersed magnetic fillers. For gas separation, the most effective magnetic membrane consists of polyimide filled with MQFP-B particles, for which the separation factor (α_rat O₂/N₂) increased by 211% when compared to the non-magnetic membrane. The same MQFP powder used as a filler in alginate membranes significantly improves water/ethanol separation via pervaporation, reaching a separation factor of 12,271.0. For other separation methods, poly(ethersulfone) nanofiltration membranes filled with ZnFe₂O₄@SiO₂ demonstrated a more than four times increase in water flux when compared to the non-magnetic membranes for water desalination. The information gathered in this article can be used to further improve the separation efficiency of individual processes and to expand the application of magnetic membranes to other branches of industry. Furthermore, this review also highlights the need for further development and theoretical explanation of the role of magnetic forces in separation processes, as well as the potential for extending the concept of magnetic channels to other separation methods, such as pervaporation and ultrafiltration. This article provides valuable insights into the application of magnetic membranes and lays the groundwork for future research and development in this area. Full article

The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB. Full article

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH₃COO⁻ and OH⁻) and cations (H⁺) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems. Full article

The low–temperature poly–Si oxide (LTPO) backplane is realized by monolithically integrating low–temperature poly–Si (LTPS) and amorphous oxide semiconductor (AOS) thin–film transistors (TFTs) in the same display backplane. The LTPO–enabled dynamic refreshing rate can significantly reduce the display’s power consumption. However, the essential hydrogenation of LTPS would seriously deteriorate AOS TFTs by increasing the population of channel defects and carriers. Hydrogen (H) diffusion barriers were comparatively investigated to reduce the H content in amorphous indium–gallium–zinc oxide (a–IGZO). Moreover, the intrinsic H–resistance of a–IGZO was impressively enhanced by plasma treatments, such as fluorine and nitrous oxide. Enabled by the suppressed H conflict, a novel AOS/LTPS integration structure was tested by directly stacking the H–resistant a–IGZO on poly–Si TFT, dubbed metal–oxide–on–Si (MOOS). The noticeably shrunken layout footprint could support much higher resolution and pixel density for next–generation displays, especially AR and VR displays. Compared to the conventional LTPO circuits, the more compact MOOS circuits exhibited similar characteristics. Full article

In this article, we present the design, fabrication, and characterization of a thermopile infrared sensor array (TISA) pixel. This TISA pixel is composed of a dual-layer p+/n- poly-Si thermopile with a closed membrane and an n-channel metal oxide semiconductor (NMOS) switch. To address the challenges in fabrication through the 3D integration method, the anode of the thermopile is connected to the drain of the NMOS, both of which are fabricated on the same bulk wafer using a CMOS compatible monolithic integration process. During a single process sequence, deposition, etching, lithography, and ion implantation steps are appropriately combined to fabricate the thermopile and the NMOS simultaneously. At the same time as ensuring high thermoelectric characteristics of the dual-layer p+/n- poly-Si thermopile, the basic switching functions of NMOS are achieved. Compared with a separate thermopile, the experimental results show that the thermopile integrated with the NMOS maintains a quick response, high sensitivity and high reliability. In addition, the NMOS employed as a switch can effectively and quickly control the readout of the thermopile sensing signal through the voltage, both on and off, at the gate of NMOS. Thus, such a TISA pixel fabricated by the monolithic CMOS-compatible integration approach is low-cost and high-performance, and can be applied in arrays for high-volume production. Full article

The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO₂/Si₃N₄/Al₂O₃ and CAAC-IGZO thin films, where Al₂O₃ was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (I_on), improved field effect carrier mobility (μ_FE), a lower body trap (N_ss), a wider memory window (ΔV_th), and better retention and endurance characteristics were attained using the CAAC-IGZO device. Full article