Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory

Abstract

Electrical characteristics with various program temperatures (T_PGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the T_PGM up to 120 °C and the read temperature (T_READ) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (I_BL) and threshold voltage (V_T). The V_T shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔV_T,CL) component and the poly-Si GB (ΔV_T,GB) component. The extracted ΔV_T,GB increases at higher T_PGM due to the reduced GB potential barrier. Additionally, the ΔV_T,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (X_GB) and the bit line voltage (V_BL).

1. Introduction

As NAND flash memory is widely used in smartphones and data centers, the demand for high-density, low-cost NAND flash memory continues to surge. Due to the limitations in scaling, the conventional planar two-dimensional (2-D) NAND has been rapidly substituted with three-dimensional (3-D) NAND [1,2]. In 3-D NAND, the vertical stacking of cells is less constrained by the scaling challenges, effectively boosting the storage capacity. Furthermore, multi-level cell technology has been adopted to further enhance the storage capacity and has evolved to the point of 4-bits/cell (quadruple level cell, QLC) development [3]. However, as the number of bits per cell increases, the threshold voltage (V_T) window narrows, necessitating the tight V_T distribution. A slight change in V_T can cause a fail bit, which is greatly affected by the environmental temperature.

NAND flash memory operates within a temperature range typically from 0 °C to 85 °C. However, such as in automotive or aerospace applications, NAND flash memory can be designed to function within a broader temperature range, extending from −40 °C to 125 °C [4,5]. The NAND operations, such as program and read, need to be executed precisely within the prescribed temperature range, even if the temperatures vary during operations. The temperature change can significantly impact both the trapped charge within the nitride layer and the electrical characteristics of the channel [6,7,8]. The utilization of SiN material as a charge storage layer causes various charge loss mechanisms and V_T changes during the retention in NAND flash memory. At elevated temperatures, the thermal emission of trapped electrons accelerates, consequently increasing the amount of de-trapping from the charge trap layer (CTL) to the channel. Additionally, the continuous CTL in the 3-D NAND induces additional charge migration in the lateral direction. This lateral migration is dominantly caused by Poole-Frenkel emission and becomes more pronounced at higher temperatures [9,10]. These charge loss mechanisms can change the V_T and potentially influence the reliability of the NAND devices in response to temperature variations.

Three-dimensional NAND is fabricated in the following process. The multi-stacked SiN/oxide layers are deposited. The memory hole is formed through the etching process, and it is then filled by the ONO layer and channel layer deposition. Subsequently, the SiN layers are removed, and empty spaces are filled by gate stack deposition [11]. The poly-Si, which can be easily formed through the deposition process, is used as a channel material in 3-D NAND due to the difficulty of single crystalline silicon growth in the process sequence. In the poly-Si deposition process, amorphous silicon is deposited and annealed to form grains [12]. Therefore, the poly-Si channel contains grain boundaries (GBs) between the Si grains. Depending on the bias conditions, carriers can be trapped at these GBs [13]. The GB trapped charges form the potential barrier (Φ_B) and interfere with carrier transport [14,15,16,17]. An elevated temperature can decrease the trap occupancy, lowering the Φ_B of GB compared with room temperature [18,19]. Consequently, it leads to low V_T and high bit line current (I_BL) even though the channel mobility is degraded [8]. Hence, when the temperature changes during the NAND operations, the temperature-induced V_T variation attributed to charge loss and poly-Si GB should be considered.

The cross-temperature is the condition where the program temperature (T_PGM) differs from the subsequent read temperature (T_READ). Additional fail bits during read operation occur in cross-temperature conditions. There are many studies on controlling additional fail bits in the cross-temperature conditions at the system level. The most common methods are to use the temperature compensation circuits, which track temperature changes through sensors and then change the read reference voltages [20,21]. However, these compensation methods struggle to address all fail bits in cross-temperature conditions [22,23]. The relevant temperature coefficient in the compensation circuit differs among individual cells [24]. Even in the same cell, this coefficient varies depending on the temperature conditions: a high temperature program and low temperature read (HPLR) condition or a low temperature program and high temperature read (LPHR) condition [25,26]. Therefore, more detailed analyses at the cell level are needed to understand the cross-temperature phenomena and effectively reduce the fail bits in 3-D NAND.

Here, the retention characteristics of a programmed cell under the HPLR conditions are characterized and decomposed into the charge loss and poly-Si GB components using a neutral cell. The poly-Si GB components are further investigated with different bit line voltages (V_BL). Technology Computer Aided Design (TCAD) simulation is conducted to understand the relationship between the V_BL and the GB position.

2. Results and Discussion

2.1. Cross-Temperature Effects on Retention Characteristics

Figure 1 shows the schematic of the 3-D NAND flash memory with 24 stacked word line (WL) layers used in this experiment. It is composed of the filler oxide, poly-Si channel, bandgap-engineered tunneling oxide (BE-TOX) consisting of O1/N1/O2 layers, CTL, blocking oxide with high-κ material (BOX), and WL. Each WL is separated by the spacer. In contrast to the 2-D planar NAND structure, a poly-Si channel with randomly distributed multiple grains is used. Each grain forms GBs, where channel carriers can be trapped. The Φ_B of the GB is formed due to the trapped charges at the GB and interferes with carrier transport. Both ends of the channel are connected by the source line (SL) and bit line (BL).

Figure 2a shows the time-dependent I_BL versus read voltage (V_READ) characteristics at T_PGM = 30 °C and 120 °C. For the read operation, V_READ was applied to the target cell as the word line voltage, and pass voltage was applied to the rest of the cells except the target cell. The V_BL was applied with 1 V. The retention characteristics were measured for the E-P-E pattern, with the 7th-program verifying (PV7) level. All cells in the string were initially erased to eliminate the residual electrons in CTL to prevent any additional charge loss by electrons of the neighbor cell, and only the target cell was programmed. The initial read operation was performed at 30 s immediately after the program operation. All cases of T_PGM > 30 °C are HPLR conditions. The T_READ was promptly lowered to 30 °C through cooling after the program operation in HPLR conditions. This means that the initial T_READ is the same as T_PGM, and the T_READ gradually decreases over time. The final T_READ after 4 h is 30 °C. For T_PGM = 30 °C, the I_BL-V_READ curve shifts towards the left direction over time. For T_PGM = 120 °C, the I_BL-V_READ curve shifts towards the right direction over time. Figure 2b shows the retention characteristics at T_PGM = 30 °C, 75 °C, and 120 °C. In all cases, the T_READ after 4 h is 30 °C. The V_T was extracted using the constant current method at I_BL = 1 µA. The ΔV_T was calculated by subtracting the initial V_T from the V_T at each retention time. The negative ΔV_T is observed at T_PGM = 30 °C, indicating the decrease in V_T over time. For T_PGM = 75 °C, the ΔV_T negligibly changes over time, even though trapped electrons are emitted from CTL to the channel in the vertical direction or spread from the gate to spacer in the lateral direction during the retention. For T_PGM = 120 °C, the positive ΔV_T over time is observed up to 4 h.

Figure 3 shows the ΔV_T after 4 h (ΔV_T,4h) with respect to T_PGM. All cases except T_PGM = 30 °C are HPLR conditions. For all T_PGM values ranging from 30 °C to 120 °C, the T_READ after 4 h is 30 °C. The ΔV_T,4h increases linearly with T_PGM up to 120 °C. For T_PGM = 30 °C, the negative ΔV_T,4h is observed due to the ΔV_T by charge loss (ΔV_T,CL). At the elevated T_PGM, the ΔV_T,4h increases due to the ΔV_T by poly-Si GB (ΔV_T,GB). Since ΔV_T,CL has a negative value at elevated T_PGM, the increase in ΔV_T,4h by T_PGM indicates that the influence of ΔV_T,GB on ΔV_T,4h is higher than that of ΔV_T,CL at elevated T_PGM.

To decompose the ΔV_T of the target cell under the E-P-E pattern into ΔV_T,GB and ΔV_T,CL components, the ΔV_T,GB is primarily extracted by using the E-N-E pattern. The E-N-E pattern is adopted to suppress the charge loss of the target cell in CTL, which is obtained by erasing all cells and soft programming the target cell up to the V_T of the fresh cell. The ΔV_T,GB of E-N-E pattern (ΔV_T,GBN) between T_READ = 30 °C and T_READ = T can be obtained by the following equation,

$$\mathsf{\Delta }{V}_{T,GBN}=V_{T,N}(30 °\mathrm{C})-V_{T,N}\left(T\right)$$

(1)

where V_T,N (T) is the V_T of the E-N-E pattern at T_READ = T. The neutral cell has no trapped charges in CTL, which causes negligible ΔV_T,CL during retention [6,27]. Figure 4a shows the I_BL-V_READ curves at T_READ = 30 °C and 120 °C for the E-N-E pattern. The subthreshold swing (SS) is higher at T_READ = 120 °C compared to T_READ = 30 °C. Figure 4b shows the I_BL-V_READ curves at T_READ = 30 °C and 120 °C for the E-P-E pattern. The SS is also higher at T_READ = 120 °C than at T_READ = 30 °C. The SS difference in the E-N-E pattern between T_READ = 30 °C and T_READ = 120 °C is lower than that in the E-P-E pattern.

The SS differences in the E-N-E and E-P-E patterns are analyzed using TCAD simulation [28]. The string of 3-D NAND used in the TCAD simulation consisted of a source select line, a drain select line, two dummy cells on both sides, and five word lines to minimize the simulation time. Except for the number of WLs, all dimension parameters used to construct the simulation structure were the same as the actual device dimension parameters. For the electron and hole traps in CTL, the Gaussian energy distributions were used. Hurkx band-to-band tunneling model for gate induced drain leakage (GIDL) erase, and the Shockley-Read-Hall (SRH) model for capture or emission of carriers into traps were adopted. Transient simulation with the non-local tunneling model was applied for program and erase operations [29]. Figure 5a shows the channel electron density near the BE-TOX interface along the BL direction for the neutral and programmed target cells at the subthreshold region. The V_BL is applied with 1 V. For the programmed cell, the trapped charge density in the CTL is higher at the middle of the gate region than at the gate edge. The channel electron density of the programmed cell is higher than that of the neutral cell at the edge region. Figure 5b shows the conduction energy band (E_C) profile in the channel near the BE-TOX interface along the BL direction for the neutral and programmed target cells at the subthreshold region. For the programmed cell, the E_C peak is higher than the neutral cell and the effective channel length decreases due to the nonuniform trapped charge distribution in the CTL [30]. As the effective channel length is reduced, the influence of GB decreases and the SS difference in the E-P-E pattern between different T_READ is higher than the SS difference in the E-N-E pattern [8]. Therefore, the ΔV_T,GB of the E-P-E pattern is lower than the ΔV_T,GBN. The ΔV_T,GB of the E-P-E pattern can be obtained using the ΔV_T,GBN with the following equation,

$$\mathsf{\Delta }{V}_{T,GB}=\mathsf{\Delta }{V}_{T,GBN}-V_{SS}$$

(2)

where V_SS value is the SS difference correction voltage, which is defined using the threshold current (I_T) at V_READ = V_T and off-current (I_OFF) as follows:

$$V_{SS}=\left(\mathsf{\Delta }{SS}_P-\mathsf{\Delta }{SS}_N\right)\times {\log }_{10}(I_T/I_{OFF})$$

(3)

where ΔSS_P and ΔSS_N are the SS difference values between T_READ = 30 °C and T_READ = T for the E-P-E and E-N-E patterns, respectively.

Figure 6a shows the decomposed results of ΔV_T into ΔV_T,GB and ΔV_T,CL for T_PGM = 75 °C and 120 °C. The charge loss components are obtained by subtracting the GB components from ΔV_T of the E-P-E pattern, which is expressed as follows:

$$\mathsf{\Delta }{V}_{T,CL}=\mathsf{\Delta }{V}_{T,TOTAL}-\mathsf{\Delta }{V}_{T,GB}$$

(4)

where ΔV_T,TOTAL is the measured ΔV_T of the E-P-E pattern. The ΔV_T,GB increases during the retention time for both T_PGM = 75 °C and 120 °C. The ΔV_T,CL has a negative value up to 4 h. Figure 6b shows the absolute values of the decomposed ΔV_T,4h at T_PGM = 75 °C and 120 °C. The ΔV_T,CL diminishes at the elevated T_PGM due to the fact that the higher T_PGM results in more significant charge loss within the initial 30 s, corresponding to the range of short-term retention [26,31,32]. The ΔV_T,GB increases at the elevated T_PGM due to the decrease in Φ_B of the GB at higher temperatures. The ΔV_T,GB is 15% lower than the ΔV_T,CL at T_PGM = 75 °C, and the ΔV_T,CL is 45% lower than the ΔV_T,GB at T_PGM = 120 °C. With an increase in T_PGM under the HPLR condition, the influence of ΔV_T,GB on ΔV_T,4h becomes more pronounced.

2.2. Threshold Voltage Shift by Poly-Si GB

Figure 7a shows the ΔV_T,GB observed in 50 cells as a function of V_BL. In order to exclude the influence of differences in memory hole diameter that may occur depending on the location of the WL, only the middle five WLs from several different strings were used.

The physical dimensions of the measured cells are all the same. The ΔV_T,GB is the V_T difference between T_READ = 30 °C and T_READ = T. The neutral cells were used to evaluate only the ΔV_T,GB. Figure 7b shows the average value of ΔV_T,GB for T = 120 °C at each V_BL. The average ΔV_T,GB decreases by 10% with an increase in V_BL from 1 V to 2 V. To further understand the effect of V_BL on the ΔV_T,GB, the E_C profile in the channel was investigated using the TCAD simulation. A single GB was introduced in the channel under the target cell, varying the GB position (X_GB) in the function of gate length (L_G). The edge of the target cell on the SL side was defined as X_GB = 0. The 3-D random Voronoi grain pattern was applied under the remaining channel regions [33,34]. A U-shaped GB trap profile consisting of donor-like states and acceptor-like states was used for each GB [35]. The interface traps were also considered at the BE-TOX/channel and filler oxide/channel interfaces. The constant mobility for the drift/diffusion transport within the grain and the thermionic boundary conditions at GBs were utilized in the channel [17,18].

Figure 8a shows the simulated E_C profiles of the channel along the BL direction for X_GB = 0. The V_T of the cell with GB is applied as V_READ for both cells with GB and without GB. For the cell with GB, the Φ_B induced by GB has an effect as an additional potential barrier. The Φ_B of the cell with GB is higher than that of the cell without GB due to the Φ_B of GB. Figure 8b shows the E_C profiles for X_GB = L_G/2. The Φ_B of the cell with GB is also higher than that of the cell without GB due to the Φ_B of GB. For X_GB = 0 and L_G/2, the E_C difference between the cells with GB and without GB is more significant for T_READ = 30 °C than T_READ = 120 °C. It is due to the increase in Φ_B of GB at lower temperatures. Figure 8c shows the E_C profiles for X_GB = L_G. When GB is located at X_GB = L_G, the Φ_B of GB has negligible effect as the additional potential barrier. The E_C difference between the cells with GB and without GB is reduced at both T_READ = 30 °C and 120 °C due to the decrease in the influence of GB. Figure 8d shows the simulated ΔV_T,GB for T = 120 °C at each X_GB. A higher Φ_B is formed at 0 < X_GB < L_G/2, resulting in the substantial ΔV_T,GB. At L_G/2 < X_GB < L_G, the GB effect diminishes and the ΔV_T,GB decreases. When the GB is located under the spacer region, the GB has negligible influence on the ΔV_T,GB.

Figure 9a shows the simulated E_C profiles of the channel depending on the V_BL at T_READ = 30 °C for X_GB = 0. The Φ_B remains consistent regardless of the V_BL. Figure 9b shows the E_C profiles for X_GB = L_G/2. As the V_BL increases, the E_C peak induced by the word line voltage difference between the target cell and adjacent cells shifts towards the SL side. For this reason, the additional barrier effect induced by the Φ_B of GB is diminished. The E_C near the SL side becomes higher and the influence of GB decreases with the increase in V_BL. Figure 9c shows the E_C profiles for X_GB = L_G. As the V_BL increases, the E_C peak induced by the word line voltage difference shifts towards the SL side. The GB effect, which is nearly negligible at V_BL = 1 V, indicates no variation with respect to V_BL. Figure 9d shows the simulated ΔV_T,GB depending on V_BL (= 1 V, 1.5 V, and 2 V) for T = 120 °C at each X_GB. When the GB is located near the SL side edge under the target cell, the ΔV_T,GB is less influenced by V_BL. However, as the X_GB shifts from 0 to L_G, the ΔV_T,GB decreases due to the elevated V_BL. At the X_GB under the spacer region, where the influence of GB is already limited, the variation in ΔV_T,GB caused by V_BL is not substantial. Therefore, the average ΔV_T,GB decreases with the increase in V_BL, as shown in Figure 7b.

3. Conclusions

The retention characteristics in HPLR conditions are investigated to understand the cross-temperature effects on the V_T variation in 3-D NAND flash memory. The HPLR conditions consisting of the T_PGM with a range of 30 °C to 120 °C and T_READ of 30 °C are used. The ΔV_T of the programmed cell is successfully decomposed into the ΔV_T,CL and the ΔV_T,GB using a neutral cell. The ΔV_T,GB is lower than the ΔV_T,CL at T_PGM = 75 °C. Compared to the ΔV_T,CL, the ΔV_T,GB becomes dominant at T_PGM = 120 °C due to the decrease in Φ_B of the GB. The average ΔV_T,GB extracted from the 50 cells decreases by 10% with increasing V_BL from 1 V to 2 V. The effect of V_BL on ΔV_T,GB varies according to the X_GB. The characteristics of ΔV_T,GB versus V_BL can be utilized to measure the GB’s influences on the characteristics of I_BL in 3-D NAND flash memory.