Search Results (53)

Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (t_d(on)), rise time (t_r), and turn-on loss (E_ON) show no significant changes. In contrast, the turn-off delay time (t_d(off)), fall time (t_f), and turn-off loss (E_OFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (V_TH) and the increase in gate-source capacitance (C_GS) and gate-drain capacitance (C_GD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance. Full article

In MOSFETs, mobility enhancement is a key factor for improving the electrical performance and enabling their use in new applications, such as low-power, digital, and medical applications. This mobility improvement can be technically achieved by using different techniques that exploit the complex behavior of mobility (Coulomb, phonon, and surface roughness mobilities). Previous reviews have primarily focused on two main technologies: the introduction of mechanical stress and crystallographic orientation. Therefore, this review summarizes all key techniques that can enhance mobility, and each of these techniques is linked to a physical origin. Mechanical stress notably affects phonon mobility, whereas silicon thickness and channel impurities mainly affect the Coulomb mobility. Moreover, the dielectric oxide type, heat treatments, surface cleaning, ionic implantation in the oxide, and oxynitrides affect surface roughness mobility. In addition, the crystallographic orientation affects Coulomb, phonon, and surface roughness mobilities. Furthermore, the study of the series resistance engineering also affects the performance. Therefore, the simultaneous use of multiple of these techniques leads to an enhancement of the effective mobility at low, medium, and high effective electric fields, and the combined effect results in a more significant mobility increase. Full article

NMOSFET, whose gate is on the top of the n-p-n junction with gate oxide in between, is called the n-channel transistor. This bipolar junction underneath the gate oxide may provide an n-n-n-conductive channel as the gate is applied with a positive bias over the threshold voltage (V_th). Conceptually, the definition of an n-type or p-type semiconductor depends on whether the corresponding Fermi energy is higher or lower than the intrinsic Fermi energy, respectively. The positive bias applied to the gate would bend down the intrinsic Fermi energy until it is lower than the original p-type Fermi energy, which means that the p-type becomes strongly inverted to become an n-type. First, the thickness of the inversion layer is derived and presented in a planar 40 nm MOSFET, a 3D 240 nm FinFET, and a power discrete IGBT, with the help of the p (1/m³) of the p-type semiconductor. Different ways of finding p (1/m³) are, thus, proposed to resolve the strong inversion layers. Secondly, the conventional formulas, including the triode region and saturation region, are already modified, especially in the triode region from a continuity point of view. The modified formulas then become necessary and available for fitting the measured characteristic curves at different applied gate voltages. Nevertheless, they work well but not well enough. Thirdly, the electromagnetic wave (EM wave) generated from accelerating carriers (radiation by accelerated charges, such as synchrotron radiation) is proposed to demonstrate phonon scattering, which is responsible for the Source–Drain current reduction at the adjoining of the triode region and saturation region. This consideration of reduction makes the fitting more perfect. Fourthly, the strongly inverted layer may be formed but not conductive. The existing trapping would stop carriers from moving (nearly no mobility, μ) unless the applied gate bias is over the threshold voltage. The quantum confinement addressing the quantum well, which traps the carriers, is to be estimated. Full article

The transition of SiC MOSFET structure from planar to trench-based architectures requires the optimization of gate dielectric layers to improve device performance. This study utilizes a range of characterization techniques to explore the interfacial properties of ZrO₂ and SiO₂/ZrO₂ gate dielectric films, grown via atomic layer deposition (ALD) in SiC epitaxial trench structures to assess their performance and suitability for device applications. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements showed the deposition of smooth film morphologies with roughness below 1 nm for both ZrO₂ and SiO₂/ZrO₂ gate dielectrics, while SE measurements revealed comparable physical thicknesses of 40.73 nm for ZrO₂ and 41.55 nm for SiO₂/ZrO₂. X-ray photoelectron spectroscopy (XPS) shows that in SiO₂/ZrO₂ thin films, the binding energies of Zr 3d_5/2 and Zr 3d_3/2 peaks shift upward compared to pure ZrO₂. Electrical characterization showed an enhancement of E_BR (3.76 to 5.78 MV·cm⁻¹) and a decrease of I_{ON_EBR} (1.94 to 2.09 × 10⁻³ A·cm⁻²) for the SiO₂/ZrO₂ stacks. Conduction mechanism analysis identified suppressed Schottky emission in the stacked film. This indicates that the incorporation of a thin SiO₂ layer effectively mitigates the small bandgap offset, enhances the breakdown electric field, reduces leakage current, and improves device performance. Full article

The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters. Full article

This work introduces a novel temperature-triggered threshold voltage shift (T3VS) method to study the energy-dependent $D_{it}$ distribution close to the conduction band edge in commercial 1.2 kV 4H-SiC MOSFETs with planar and trench gate structures. Traditional $D_{it}$ extraction methodologies are complicated and require sophisticated instrumentation, complex analysis, and/or prior information related to the device design and fabrication, which is generally unavailable to the consumers of commercial devices. This methodology merely utilizes the transfer characteristics of the device and is straightforward to implement. The $D_{it}$ analysis using the T3VS method shows that trench devices have significantly lower $D_{it}$ in comparison to the planar devices, making them more reliable and efficient in practical applications. Furthermore, this study examines the impact of a novel room temperature gate oxide screening methodology called screening with adjustment pulse (SWAP) on the $D_{it}$ distribution in commercial planar MOSFETs, utilizing the proposed T3VS method. The result demonstrates that the SWAP technique is aggressive in nature and can introduce new defect states close to the conduction band edge. Hence, additional care is needed during screening optimization to ensure the reliability and usability of the screened devices in the consequent applications. Full article

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure. Full article

The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO₂ and SiO₂/HfO₂ gate dielectrics grown by atomic layer deposition (ALD) on SiC trench structures. The trench structure morphology was revealed using scanning electron microscopy (SEM). Atomic force microscopy (AFM) measurements showed that the roughness of both films was below 1nm. Spectroscopic ellipsometry (SE) indicated that the physical thicknesses of HfO₂ and SiO₂/HfO₂ were 38.275 nm and 40.51 nm, respectively, demonstrating their comparable thicknesses. X-ray photoelectron spectroscopy (XPS) analysis of the gate dielectrics revealed almost identical Hf 4f core levels for both HfO₂ and the SiO₂/HfO₂ composite dielectrics, suggesting that the SiO₂ interlayer and the SiC substrate had minimal impact on the electronic structure of the HfO₂ film. The breakdown electric field of the HfO₂ film was recorded as 4.1 MV/cm, with a leakage current at breakdown of 1.1 × 10⁻³A/cm². The SiO₂/HfO₂ stacked film exhibited significantly better performance, with a breakdown electric field of 6.5 MV/cm and a marked reduction in leakage current to 3.7 × 10⁻⁴ A/cm². A detailed extraction and analysis of the leakage current mechanisms were proposed, and the data suggested that the introduction of thin SiO₂ interfacial layers effectively mitigated small bandgap offset issues, significantly reducing leakage current and improving device performance. Full article

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered. Full article

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (R_DS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in R_DS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in R_DS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article

A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, R_on × C_gd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article

A novel planar silicon carbide (SiC) MOSFET integrated with both MOS-channel diode (MCD) and junction barrier Schottky diode (JBS) on the same chip (MCD-JBSFET) is proposed and investigated through Technology Computer-Aided Design (TCAD) simulations in this paper. The proposed device features the lowest turn-on voltage and the best current conduction capability under the reverse-biased conditions, allowing it to achieve the same reverse conduction capability with fewer MCDs compared to conventional MOSFET with MCD structures (MCDFET). This reduction in the number of MCDs enables more channels to operate under forward-biased conditions, thereby improving power density. Compared to a conventional MOSFET integrated with JBS structure (JBSFET), the reverse current in the MCD-JBSFET flows through both the MCD and JBS, which suppresses the peak lattice temperature at Schottky contact and enhances the high-temperature robustness, especially under surge current conditions. In addition, the split-gate structure in the proposed structure optimizes the reverse capacitance and the figure of merit R_on,sp × Q_g by factors of 0.65 and 2.15, respectively. Finally, the switching losses are reduced by 40.2%, indicating the suitability of MCD-JBSFET for high-frequency and high-current applications. Full article

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage $\left({\mathrm{V}}_{\mathrm{t}\mathrm{h}}\right)$ and gate leakage current $\left({\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}\right)$ in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in ${\mathrm{S}\mathrm{i}\mathrm{O}}_2$ caused by oxide electric field $\left({\mathrm{E}}_{\mathrm{o}\mathrm{x}}\right)$ stress affect the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ of SiC MOSFETs. The saturation and turnaround behavior of the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift and ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. Full article

FinFET transistors with fin channel lengths of 160 nm and 2000 nm and a planar MOSFET transistor with channel lengths of 180 nm and 90 nm are presented with characteristic curves at various Gate biases. A finalized algorithm with kink effects was effectively responsible for addressing the field effect transistors. The algorithm included the modified conventional current–voltage formula and a nonlinear heat-associated kink solution which was simplified as a Gaussian form. Three parameters in the modified model included k_N (which was related with channel width, channel length, and gate oxide capacitor, and was proportional to the mobility of carriers), Vth (threshold voltage), and λ (the inverse of early voltage). Those parameters were determined to minimize the discrepancies between the measured data and the fitting values, but left kinks located at around (V_GS-Vth), which were deliberately eliminated by the Gaussian form because of the agitation of thermal kink effects. The whole fitting was made to be as close as possible to the as-measured I_DS-V_DS. In the meantime, those determined parameters were physically meaningful after the analysis had been performed. Full article

The surge in demand for 3D MOSFETs, such as FinFETs, driven by recent technological advances, is explored in this review. FinFETs, positioned as promising alternatives to bulk CMOS, exhibit favorable electrostatic characteristics and offer power/performance benefits, scalability, and control over short-channel effects. Simulations provide insights into functionality and leakage, addressing off-current issues common in narrow band-gap materials within a CMOS-compatible process. Multiple structures have been introduced for FinFETs. Moreover, some studies on the fabrication of FinFETs using different materials have been discussed. Despite their potential, challenges like corner effects, quantum effects, width quantization, layout dependencies, and parasitics have been acknowledged. In the post-planar CMOS landscape, FinFETs show potential for scalability in nanoscale CMOS, which leads to novel structures for them. Finally, recent developments in FinFET-based sensors are discussed. In a general view, this comprehensive review delves into the intricacies of FinFET fabrication, exploring historical development, classifications, and cutting-edge ideas for the used materials and FinFET application, i.e., sensing. Full article