Search Results (23)

Accurate and fast junction-temperature estimation in Silicon Carbide (SiC) power modules is crucial for reliable operation, health monitoring and predictive control of power electronic converters in different applications. However, direct temperature measurement inside the module is difficult and high-fidelity thermal models are often very computationally expensive for real-time implementation. This paper proposes a digital twin development approach for fast and accurate temperature estimation in all three dimensions of a SiC MOSFET power module by a combination of finite element method (FEM) modelling and neural networks. The work is especially relevant in thermal monitoring and managing power electronics converters such as renewable energy systems, energy storage systems, Electric Vehicles (EV), etc. The model incorporates a neural network trained on data generated from an FEM model built in COMSOL Multiphysics. The developed digital twin can estimate the temperature distribution, including the ten junction temperatures of the Wolfspeed EAB450M12XM3 module, with an average estimation time of 0.063 s, enabling predictive control. In order to improve practical applicability and model synchronization with the physical system, NTC-based feedback techniques are discussed (single-Temperature Coefficient (NTC) and double-NTC approaches). The proposed framework is investigated in terms of prediction accuracy and computational performance related to the FEM-generated reference data. The approach improves model reliability by adjusting the parameters of the critical digital and physical modules. The combination of FEM-based modelling and machine learning can provide a foundation for accurate, real-time thermal monitoring in power electronic modules. Full article

Single-Event Burnout (SEB) is one of the most critical failure mechanisms in silicon power MOSFETs operating in radiation environments, particularly under heavy-ion irradiation, and often limits device operation through excessive voltage derating. In this work, SEB robustness of a silicon VDMOS power device is investigated using detailed electro-thermal transient simulations. The study evaluates two complementary device-level modifications: the introduction of a buffer layer between the epitaxial layer and the substrate, which has been reported in the past, and a new approach considering the incorporation of a novel highly doped boron BOX implant within the P-body region. Heavy-ion impacts are simulated using a physically based model implemented in SENTAURUS TCAD, accounting for ion energy deposition, impact position, and thermal effects. The results show that the buffer layer increases the second breakdown voltage and can suppress high-current operating points, while the BOX implant raises the parasitic BJT activation threshold by reducing the P-body resistance. When combined, both modifications lead to a significant reduction in the peak temperature reached during after-impact transients, without introducing measurable degradation of static electrical characteristics. These results demonstrate that combining buffer layer engineering with localized P-body resistance reduction is an effective strategy to improve SEB robustness in silicon VDMOS power devices without relying on excessive derating. Full article

Triboelectric nanogenerators (TENGs) offer intrinsically high open-circuit voltages in the kilovolt range; however, conventional diode rectifier interfaces clamp the voltage prematurely, restricting access to the high-energy portion of the mechanical cycle and preventing delivery-centric control. This work develops a unified physical basis for contact–separation (CS) TENGs by confirming the consistency of the canonical $V_{oc}$–$C_s$ relation with a dual-capacitor energy model and analytically establishing that both terminal voltage and storable electrostatic energy peak near maximum plate separation. Leveraging this insight, a self-powered gas-discharge-tube (GDT) rectifier bridge is devised to replace two diodes and autonomously trigger conduction exclusively in the high-voltage window without auxiliary bias. An inductive buffer regulates the current slew rate and reduces $I^{2}R$ loss, while the proposed topology realizes two decoupled power rails from a single CS-TENG, enabling simultaneous sensing/processing and actuation. A low-power microcontroller is powered from one rail through an energy-harvesting module and executes an operator-based nonlinear controller to regulate the actuator-side rail via a MOSFET–resistor path. Experimental results demonstrate earlier and higher-efficiency energy transfer compared with a diode-bridge baseline, robust dual-rail decoupling under dynamic loading, and accurate closed-loop voltage tracking with negligible computational and energy overhead. These findings confirm the practicality of the proposed self-powered architecture and highlight the feasibility of integrating operator-theoretic control into TENG-driven rectifier interfaces, advancing delivery-oriented power extraction from high-voltage TENG sources. Full article

In situ estimations of gate oxide degradation and junction temperature are critical for SiC MOSFETs, as these parameters are key for device-level health management. However, the indicators used in existing evaluation methods primarily focus on one aspect and do not effectively integrate the assessment of both targets, as they require different indicators. To address this problem, this paper proposes a unified evaluation method that uses a single indicator to simultaneously estimate both gate oxide degradation and junction temperature. An on-state resistance (R_ON) model is used as the indicator. The R_ON model is first proposed to characterize the influence of temperature and gate degradation on R_ON. An iterative approach is introduced to determine the R_ON model parameters, utilizing R_ON measurements across various temperatures and gate degradation levels, while accounting for the physical characteristics of the parameters. Furthermore, an in situ estimation method for gate degradation and junction temperature is developed based on a two-level turn-on strategy. By analyzing R_ON before and after gate voltage changes, the gate degradation level and junction temperature can be simultaneously estimated. The proposed method’s effectiveness is demonstrated in a DC-DC converter application. Full article

This study proposes a novel framework integrating long short-term memory (LSTM) networks with Bayesian optimization (BO) to address process–device co-optimization challenges in trench-gate metal–oxide–semiconductor field-effect transistor (MOSFET) manufacturing. Conventional TCAD simulations, while accurate, suffer from computational inefficiency in high-dimensional parameter spaces. To overcome this, an LSTM-based TCAD proxy model is developed, leveraging hierarchical temporal dependencies to predict electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to physical simulations. The model, validated on both N-type and P-type 20 V trench MOS devices, outperforms conventional RNN and GRU architectures, reducing average relative errors by 1.78% through its gated memory mechanism. A BO-driven inverse optimization methodology is further introduced to navigate trade-offs between conflicting objectives (e.g., minimizing on-resistance while maximizing breakdown voltage), achieving recipe predictions with a maximum deviation of 8.3% from experimental data. Validation via TCAD-simulated extrapolation tests and SEM metrology confirms the framework’s robustness under extended operating ranges (e.g., 0–40 V drain voltage) and dimensional tolerances within industrial specifications. The proposed approach establishes a scalable, data-driven paradigm for semiconductor manufacturing, effectively bridging TCAD simulations with production realities while minimizing empirical trial-and-error iterations. Full article

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron. Full article

Statistical simulation is a necessary step in integrated circuit design since it provides a realistic picture of the circuit’s behavior in the presence of manufacturing process variations. When some of the circuit components lack an accurate analytical model, as is often the case for emerging semiconductor devices or ones working at cryogenic temperatures, an approximation model is necessary. Such models are usually based on a lookup table or artificial neural network individually fitted to measurement data. If the number of devices available for measurement is limited, so is the number of approximation model instances, which renders impossible a reliable statistical circuit simulation. Approximation models using the device’s physical parameters as inputs have been reported in the literature but are only useful if the end user knows the statistical distributions of those parameters, which is not always the case. The solution proposed in this work uses a type of artificial neural network called the variational autoencoder that, when exposed to a small sample of I-V curves under process variations, captures their essential features and subsequently generates an arbitrary number of similarly disturbed curves. No knowledge of the underlying physical sources of these variations is required. The proposed generative model trained on as few as 20 instances of a MOSFET is shown to precisely reproduce the period and power consumption distributions of a ring oscillator built with these MOSFETs. Full article

Accurate fault simulation and failure prediction have long been challenges for SiC MOSFETs users. This paper presents a behavior model of Silicon Carbide (SiC) double-implanted MOSFET (DMOSFET), considering thermal-runaway failures in short-circuit and avalanche breakdown faults on the basis of cell-level physical processes. The proposed model can simulate the faults with extremely high accuracy and precisely predict SiC DMOSFET’s short-circuit withstand time and critical avalanche energy. By finite-element simulations, cell-level physical processes of short-circuit and avalanche breakdown faults are clarified. The mechanisms of thermal-runaway failures are deeply discussed with references to existing studies. Based on semiconductor and device physics mechanisms, the proposed model is constructed upon a traditional behavior model of SiC MOSFET with several parallel branches that are proposed to describe the thermal-runaway failures during both faults. The Cauer thermal network model is used for estimating junction temperature within it. The proposed model is constructed in Simulink, and it is validated using short-circuit and unclamped inductive switching (UIS) tests. Full article

In this paper, a single-event transient model based on the effective space charge for MOSFETs is proposed. The physical process of deposited and moving charges is analyzed in detail. The influence of deposited charges on the electric field in the depletion region is investigated. The electric field decreases in a short time period due to the neutralization of the space charge. After that, the electric field increases first and then decreases when the deposited charge is moved out. The movement of the deposited charge in the body mainly occurs through ambipolar diffusion because of its high-density electrons and holes. The derivation of the variation in electric field in the depletion region is modeled in the physical process according to the analysis. In combination with the ambipolar diffusion model of excessive charge in the body, a physics-based model is built to describe the current pulse in the drain terminal. The proposed model takes into account the influence of multiple factors, like linear-energy transfer (LET), drain bias, and the doping concentration of the well. The model results are validated with the simulation results from TCAD. Through calculation, the root-mean-square error (RMSE) between the simulation and model is less than 3.7 × 10⁻⁴, which means that the model matches well with the TCAD results. Moreover, a CMOS inverter is simulated using TCAD and SPICE to validate the applicability of the proposed model in a circuit-level simulation. The proposed model captures the variation in net voltage in the inverter. The simulation result obviously shows the current plateau effect, while the relative error of the pulse width is 23.5%, much better than that in the classic model. In comparison with the classic model, the proposed model provides an RMSE of 7.59 × 10⁻⁵ for the output current curve and an RMSE of 0.158 for the output voltage curve, which are significantly better than those of the classic model. In the meantime, the proposed model does not produce extra simulation time compared with the classic double exponential model. So, the model has potential for application to flow estimation of the soft error rate (SER) at the circuit level to improve the accuracy of the results. Full article

The performance requirements for power devices in airborne equipment are increasingly demanding, while environmental and working stresses are becoming more diverse. The degradation mechanisms of devices subjected to multiple stresses become more complex. Most proposed degradation mechanisms and models in current research only consider a single stress, making it difficult to describe the correlation between multiple stresses and the correlation of failures. Then, a multi-physical field coupling model based on COMSOL is proposed. The influence relationship between temperature, moisture, electrical load, and vibration during device operation is considered, and a three-dimensional finite element model is built to investigate the multi-stress degradation mechanism under multi-physical field coupling. The simulation results show that, compared with single-stress models, the proposed multi-stress coupled model can more accurately simulate the degradation process of SiC MOSFET. This provides references for improving the reliability design of power device packaging. Full article

Nowadays, the performance of silicon-based devices is almost approaching the physical limit of their materials, which have difficulty meeting the needs of modern high-power applications. The SiC MOSFET, as one of the important third-generation wide bandgap power semiconductor devices, has received extensive attention. However, numerous specific reliability issues exist for SiC MOSFETs, such as bias temperature instability, threshold voltage drift, and reduced short-circuit robustness. The remaining useful life (RUL) prediction of SiC MOSFETs has become the focus of device reliability research. In this paper, a RUL estimation method using the Extended Kalman Particle Filter (EPF) based on an on-state voltage degradation model for SiC MOSFETs is proposed. A new power cycling test platform is designed to monitor the on-state voltage of SiC MOSFETs used as the failure precursor. The experimental results show that the RUL prediction error decreases from 20.5% of the traditional Particle Filter algorithm (PF) algorithm to 11.5% of EPF with 40% data input. The life prediction accuracy is therefore improved by about 10%. Full article

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design. Full article

Wide band gap (WBG) power electronic devices, such as silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) and gallium–nitride high-electron-mobility transistors (GaN HEMTs) have been widely used in various fields and occupied a certain share of the market with rapid momentum, owing to their excellent electrical, mechanical, and thermal properties. The reliability of WBG power electronic devices is inseparable from the reliability of power electronic systems and is a significant concern for the industry and for academia. This review attempts to summarize the recent progress in the failure mechanisms of WBG power electronic semiconductor chips, the reliability of WBG power electronic packaging, and the reliability models for predicting the remaining life of WBG devices. Firstly, the typical structures and dominant failure mechanisms of SiC MOSFETs and GaN HEMTs are discussed. This is followed by a description of power electronic packaging failure mechanisms and available packaging materials for WBG power electronic devices. In addition, the reliability models based on physics-of-failure (including time-dependent dielectric breakdown models, stress–strain models, and thermal cycling models), and data-driven models are introduced. This review may provide useful references for the reliability research of WBG power devices. Full article

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8× and 1.4× acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21× reduction in computational time. Full article

CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed. Full article