Single-Event Burnout Mitigation in Silicon VDMOS Power Devices: An Electro-Thermal TCAD Study

Abstract

Single-Event Burnout (SEB) is one of the most critical failure mechanisms in silicon power MOSFETs operating in radiation environments, particularly under heavy-ion irradiation, and often limits device operation through excessive voltage derating. In this work, SEB robustness of a silicon VDMOS power device is investigated using detailed electro-thermal transient simulations. The study evaluates two complementary device-level modifications: the introduction of a buffer layer between the epitaxial layer and the substrate, which has been reported in the past, and a new approach considering the incorporation of a novel highly doped boron BOX implant within the P-body region. Heavy-ion impacts are simulated using a physically based model implemented in SENTAURUS TCAD, accounting for ion energy deposition, impact position, and thermal effects. The results show that the buffer layer increases the second breakdown voltage and can suppress high-current operating points, while the BOX implant raises the parasitic BJT activation threshold by reducing the P-body resistance. When combined, both modifications lead to a significant reduction in the peak temperature reached during after-impact transients, without introducing measurable degradation of static electrical characteristics. These results demonstrate that combining buffer layer engineering with localized P-body resistance reduction is an effective strategy to improve SEB robustness in silicon VDMOS power devices without relying on excessive derating.

1. Introduction

Power devices intended for applications exposed to ionizing radiation typically incorporate protection mechanisms to endure reliable operation. These mechanisms may be related to the operation mode and conditions, such as shielding or electrical derating, or to structural modifications implemented at the device level to mitigate radiation-induced failures.

Silicon Vertical Double-Diffused MOS (VDMOS) power devices operating in radiation environments are susceptible to several failure mechanisms, including Single-Event Burnout (SEB), Single-Event Gate Rupture (SEGR), Total Ionizing Dose (TID) and Displacement Damage (DD), [1,2,3,4,5,6]. The occurrence and severity of these effects strongly depend on radiation characteristics. Consequently, the selection or design of radiation-hardened (Rad-Hard) devices must be accompanied by a clear definition of the radiation environment in which the device is expected to operate.

This work focuses on Single-Event Burnout (SEB), a destructive failure mechanism triggered by the interaction of high-energy ions (typically of space origin) with the device. SEB occurs when ion-induced charge deposition activates the parasitic bipolar transistor (BJT) inherent to VDMOS structures, leading to a transient latch-up condition that can result in permanent device failure if the power dissipated and subsequent temperature rise during the event is sufficiently high [7].

The onset of SEB is primarily determined by three factors: the ion impact location, the magnitude and spatial distribution of the deposited charge, and the applied bias conditions. The most critical impact location is generally the one that maximizes the hole current flowing into the P-well immediately after the ion strike. Although, previous studies have shown that the thermal worst-case does not necessarily coincide with the position of maximum hole current [8]. The spatial distribution of the deposited energy is typically characterized by parameters such as LET and radial charge density, which are commonly obtained using simulation tools such as SRIM/TRIM or GEANT4 [9]. In addition, the applied voltage in the blocking mode influences the transient currents, dissipated power and peak temperatures reached during the event. In space applications, ion properties such as atomic mass, energy, and fluence are dictated by the mission orbit, making SEB a critical concern in Rad-Hard power device design.

A widely adopted approach to mitigate SEB in radiation environments consists of applying voltage and current derating to commercial off-the-shelf (COTS) devices [10]. However, the degree of oversizing required to ensure safe operation can be substantial, often resulting in increased cost, reduced power density, and limited applicability. To overcome these limitations, numerous studies have proposed device-level design modifications aimed at improving SEB robustness without resorting to excessive derating. These approaches include the introduction of buffer layers between the epitaxial layer and the substrate to increase the second breakdown voltage and reduce dissipated power [11], the reduction in P-well resistance or the redirection of the hole current paths to suppress parasitic latch-up [12,13] and the incorporation of regions with enhanced recombination to remove excess holes before they reach the P-body [14]. Nevertheless, such modifications may lead to undesired changes in the device’s electrical characteristics.

In this context, the present work evaluates, through electro-thermal transient simulations, the SEB robustness and its improvement in a 60 V silicon VDMOS device. Planar VDMOS technologies are widely used in space applications, and commercial devices based on this architecture are already available. The proposed approach combines the incorporation of a buffer layer with a novel P-body BOX implant within the P-body region without significantly increasing process device technology and cost, achieving enhanced SEB robustness without degrading the device’s electrical performance in terms of specific on-resistance (R_ONxS) and breakdown voltage (V_BR). Due to the easy incorporation of the BOX profile together with the inclusion of the buffer layer, the SEB robustness could be enhanced in a wide spectrum of silicon power VDMOS. The analysis is based on detailed physical modeling of both the ion strike and device structure, implemented using SENTAURUS TCAD [15].

This paper is organized as follows. Section 2 describes the SEB mechanism as a function of external parameters and temperature. Section 3 presents the VDMOS model and simulation boundary conditions. Section 4 analyzes the effect of introducing a buffer layer. Section 5 investigates the impact of the BOX implant profile. Section 6 discusses the combined effects of both modifications. Finally, Section 7 summarizes the main conclusions and contributions of this work.

2. SEB Dependence on V_DS, Ion Characteristics and Temperature

The SEB phenomenon has been extensively described in the literature [1,2], and its dependence on operating conditions such as applied voltage, ion properties, and temperature is well established. The SEB process can be divided into two main stages:

Following the ion impact, a localized generation of electron–hole pairs occur, whose magnitude depends on the ion LET, which defines the energy deposited per area and depth by the ion along its path, and atomic mass. When the generated charge density locally exceeds the epitaxial doping concentration, the electric field distribution within the device in blocking mode is significantly modified. In particular, the electric field peak may shift from the P⁻/N⁻ junction toward the N⁻/N⁺ junction, where additional electron-hole pairs can be generated through avalanche multiplication. Simultaneously, due to applied device bias, the holes generated by the ion flow toward the source through the P-body, as schematically illustrated in Figure 1.

If the hole current flowing through the P-body is sufficiently high, it can activate the parasitic BJT inherent to the VDMOS structure, leading to a latch-up condition. Once activated, the BJT injects additional electrons from the source, further increasing current density in the device. Depending on the applied drain-source voltage (V_DS) and the increment of hole current ($∆I_{holes}$), the system may evolve toward different equilibrium states. For V_DS exceeding the second breakdown voltage (defined as the voltage at which, due to the Kirk effect, the electric field at the N⁻/N⁺ junction generates enough holes through impact ionization to sustain the BJT injection [11]), and $∆I_{holes}$ larger than a critical threshold, $(∆I_{holes2nd}$) the equilibrium point corresponds to a destructive high-current state (SEB) associated with the second breakdown, as shown in Figure 2a, which illustrates the relation of SEB onset conditions with the quasi-stationary avalanche curve [11]. In contrast, for the intermediate of $∆I_{holes},$ ($∆I_{holesBJT}<∆I_{holes}<∆I_{holes2nd}$), the device may return to its pre-impact state (Figure 2b), although with higher dissipated power compared to the case without parasitic BJT activation. It should be noted that $∆I_{holes}$ also depends on the holes generated by the Kirk effect, as well as on the temperature of the N⁻/N⁺ junction and the applied V_DS. Consequently, a wide range of recovery behaviors may occur, and each scenario must be analyzed individually.

From this analysis, it becomes evident that the applied V_DS, the ion-induced charge generation and the device temperature are the main variables governing the SEB transient. The applied V_DS directly determines the electric field distribution, which, as described in Section 1, consequently increases the likelihood of additional carrier generation through impact ionization. Moreover, it sets the current levels in the various device regions and strongly influences the post-transient stability. For this reason, voltage derating is commonly employed in power devices intended for radiation environments.

The role of temperature in SEB behavior is multifaceted and involves several competing mechanisms. First, carrier lifetimes generally increase with temperature, reducing hole recombination rates and favoring parasitic BJT activation through an increased current gain. Second, the base–emitter turn-on voltage of the parasitic BJT decreases with temperature, while the P-body resistance increases, both effects contributing to enhanced latch-up susceptibility. On the other hand, hole generation through avalanche multiplication decreases with increasing temperature due to the reduced carrier mean free path, implying that a higher initial ambient temperature may result in a lower hole current when avalanche is the dominant generation mechanism [16]. Finally, during a second breakdown transient, the rapid temperature increase in the N⁻/N⁺ junction can lead to a decrease in the generated current, potentially allowing the device to return to a stable operating point.

Although SEB is influenced by the applied voltage, ion characteristics, and device structure, it is ultimately limited by thermal constraints. Therefore, for each ion-induced transient, it is necessary to assess how these factors affect the total power dissipated and maximum temperature reached in the sensitive regions of the VDMOS device.

3. Model and Simulation Strategy

3.1. VDMOS Model

The simulated unit cell corresponds to a typical VDMOS structure, schematically shown in Figure 3. It features: a 7 µm N⁻ epitaxial layer with a resistivity of 0.65 Ω·cm grown on a N⁺ substrate with a resistivity of 0.03 Ω·cm, with total cell width of 24 µm. These epitaxial parameters ensure a breakdown voltage of approximately 60 V, consistent with the target device class. The device structure was generated using the SENTAURUS TCAD SPROCESS module following a realistic sequence of fabrication steps, resulting in electrical characteristics representative of an actual VDMOS power device. For all simulations, a Z-axis depth of 1 µm is considered, making the half-cell drain area equal to 12 µm².

3.2. Ion Model

The ion model incorporates the necessary physical characteristics to reproduce the SEB response of a simulated VDMOS cell. Depending on the ion’s energy and atomic mass, the model defines a specific LET, radial distribution, and penetration depth [17,18,19].

To evaluate the impact of the proposed device modifications, a worst-case ion was selected in terms of fluence, LET, and penetration depth. According to [20], which defines fluence as a function of energy (LET), atomic number (Z), and orbit; geostationary orbit presents the highest fluence values over energies and atomic numbers. Fluence for ions with Z ≥ 26 (iron) decreases by several orders of magnitude, and since maximum LET scales quadratically with Z [21], iron is selected as the representative worst-case ion as it has the maximum LET-per-fluence ratio. Figure 4 shows the LET dependence on ion energy and penetration depth for several ions, including iron, obtained with SRIM/TRIM simulations. For iron, a peak LET value of 29.3 MeV·cm²/mg is reached at an energy of 120 MeV (point A), corresponding to a penetration depth of approximately 22.5 µm, sufficient to traverse the entire epitaxial layer and extent partially into the substrate. It should be noted that, according to [2], electron–hole pairs generated deep in the substrate have a negligible impact on SEB due to rapid recombination.

The radial distribution of the deposited charge is complex to describe analytically. Semi-empirical models [15] allow for an approximate definition of this distribution. For the selected ion (Fe, 120 MeV), approximating the radial charge distribution using an exponential function, as defined in Equation (1) [22], yields a characteristic radius (Wt) below 10 nm. Such a small radius would require extremely fine meshing in the impact region, increasing computational cost. However, due to the strong initial charge gradients, the distribution exhibits large drift and diffusion, and the initial radius can be increased without significantly altering the simulated SEB transient, as demonstrated in Figure 5a. Increasing the radius by a factor of 20 produces nearly similar current and temperature transients, while allowing for a coarser mesh and reduced simulation time. Based on this analysis, a value of Wt = 50 nm is adopted in all simulations, as illustrated in Figure 5b.

$$\mathrm{R}\left(\mathrm{r}\right)=\mathrm{e}\mathrm{x}\mathrm{p}(-{\displaystyle \frac{\mathrm{r}}{{\mathrm{w}}_{\mathrm{t}}}})$$

(1)

3.3. Simulation Considerations

3.3.1. Heavy Ion Model

Ion-induced transients are simulated using the SENTAURUS TCAD SDEVICE module in combination with the HeavyIon model. This model deposits a charge profile at time t₀ according to Equation (1), with a temporal evolution described by Equation (2), where a characteristic evolution time associated with the ion-track energy deposition process of S_HI = 2 × 10⁻¹² s is assumed, consistent with reported values in the literature [16].

$$\mathrm{T}\left(\mathrm{t}\right)={\displaystyle \frac{2·\exp \left(-{\left(\frac{\mathrm{t}-{\mathrm{t}}_0}{\sqrt{2}{\mathrm{S}}_{\mathrm{H}\mathrm{I}}}\right)}^2\right)}{\sqrt{2}{\mathrm{S}}_{\mathrm{H}\mathrm{I}}\sqrt{\mathsf{\pi }}\left(1+\mathrm{erf}\left(\frac{{\mathrm{t}}_0}{\sqrt{2}{\mathrm{S}}_{\mathrm{H}\mathrm{I}}}\right)\right)}}$$

(2)

The electro-thermal simulations are based on the standard lattice heat equation, where carrier energy dissipation is coupled to the lattice through Joule heating and impact ionization. Non-equilibrium carrier–phonon dynamics and two-temperature effects are important at the track center after the impact; however, they are not explicitly modeled due to the fact that SEB mechanisms have characteristic time orders of magnitude slower than the non-equilibrium effects.

3.3.2. Heavy Ion Impact Position and Basic Cell Symmetry

As discussed in Section 1, impact position is critical for SEB behavior. The impact location that maximizes the hole current through the P-body is commonly regarded as the worst case, since it enables SEB at the lowest V_DS. However, several studies have reported that the maximum temperature during the transient may occur when the ion impacts the channel region rather than the JFET region, due to a higher initial current peak, even though the parasitic BJT activation is weaker and the total power dissipated lower in this case [8,23].

For simulations of the ion impacts in the JFET region, only half of the VDMOS basic cell is required due to structural symmetry. In contrast, full-cell simulations are necessary for channel impacts to avoid overestimating the amount of deposited charge contribution to the transient. Figure 6a illustrates a channel impact simulated on the full cell, while Figure 6b shows the resulting current and temperature transients for 120 MeV iron at V_DS = 45 V comparing different impact positions. The results confirm that higher-peak temperatures are reached for channel impacts.

Based on these observations, SEB robustness must be evaluated for both JFET and channel impact positions when assessing the effect of the buffer layer and BOX implant profile for the P-well region.

3.3.3. Thermal Boundaries

For electro-thermal simulations, the following thermal boundary conditions were applied. An initial ambient temperature of 300 K was assumed. Although the absolute temperature peak depends on the initial temperature, a larger temperature increase (ΔT) is generally obtained when starting from lower ambient temperatures [7]. A Dirichlet boundary condition (T = 300 K) was applied at the drain contact assuming that the substrate volume is sufficiently large to absorb the dissipated energy without significant temperature rise during the transient. Neumann (adiabatic) boundary conditions were imposed at the lateral boundaries and at the aluminum–air interface, assuming negligible heat exchange within the nanosecond time scale of the simulated event.

3.3.4. Limitations of 2D Simulation

All ion impact simulations were performed using a two-dimensional (2D) device model, as is common in device-level numerical analysis. As a consequence, cylindrical effects associated with the radial symmetry of ion-induced charge deposition cannot be fully captured. However, because the regions of the cell influenced by the transient have micrometer-scale dimensions and the ion-track radius is approximately 0.05 µm (several times smaller than the JFET or channel regions), no significant deviation in the overall SEB mechanisms is expected. Nevertheless, the absolute values of temperature and current obtained from the simulations should be regarded as qualitative. For this reason, the effects of the buffer layer and the BOX implant are discussed exclusively in relative terms, focusing on comparative trends rather than absolute thresholds.

4. Buffer Layer Effects on VDMOS Structure

The most common approach reported in the literature to enhance SEB robustness in VDMOS power devices is the introduction of a buffer layer between the N⁻ epitaxial layer and the N⁺ substrate [11,24]. This structural modification provides several benefits, among which two effects are particularly relevant for SEB mitigation:

• It reduces electron–hole pair generation by impact ionization at the N⁻/N⁺ junction during the plasma track formation, since the electric field peak at this junction is reduced.
• It increases the second breakdown voltage (point A to A’ schematically shown in Figure 7) via the reduction in the electric field at the N⁻/N⁺ junction due to a decrease in effective charge density $\left|\mathsf{\rho }\right|=\mathrm{q}\left[{\displaystyle \frac{\mathrm{J}}{\mathrm{q}{\mathrm{v}}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}-{\mathrm{N}}_{\mathrm{D}}\right]$ [11]. This allows the device to operate at higher V_DS, thereby preventing ion impacts from driving the device toward a high-current operating point (SEB).

The second breakdown voltage of a power device can be analytically described as a first approximation, under the assumption of an ideal N/N⁺ junction. Equation (3), derived from [25], relates the maximum electric field (E_MAX) to the buffer layer characteristics, namely its doping concentration (N_B) and thickness (W_B).

$${\mathrm{E}}_{\mathrm{M}\mathrm{A}\mathrm{X}}={\displaystyle \frac{1}{{\mathsf{\epsilon }}_{\mathrm{S}}}}\left[\sqrt{({\displaystyle \frac{{\mathrm{J}}_{\mathrm{C}}}{{\mathrm{v}}_{\mathrm{S}\mathrm{A}\mathrm{T}}}}-\mathrm{q}{\mathrm{N}}_{\mathrm{E}})({\mathrm{V}}_{\mathrm{D}\mathrm{S}}2{\mathsf{\epsilon }}_{\mathrm{S}}+{\mathrm{W}}_{\mathrm{B}}^2\mathrm{q}({\mathrm{N}}_{\mathrm{B}}-{\mathrm{N}}_{\mathrm{E}}))}-\mathrm{q}{\mathrm{W}}_{\mathrm{B}}({\mathrm{N}}_{\mathrm{B}}-{\mathrm{N}}_{\mathrm{E}})\right]$$

(3)

where the critical current density J_C, corresponding to the onset of the second breakdown, is given by

$${\mathrm{J}}_{\mathrm{C}}={\mathrm{v}}_{\mathrm{S}\mathrm{A}\mathrm{T}}\left[{\displaystyle \frac{{\mathrm{E}}_{\mathrm{C}\mathrm{R}\mathrm{I}\mathrm{T}\mathrm{S}\mathrm{i}}^2{\mathsf{\epsilon }}_{\mathrm{S}}}{2{\mathrm{V}}_{\mathrm{D}\mathrm{S}}^{2\mathrm{n}\mathrm{d}}}}+\mathrm{q}{\mathrm{N}}_{\mathrm{E}}\right]$$

(4)

The remaining parameters are epilayer doping concentration (N_E), applied voltage (V_DS), minimum voltage for second breakdown (${\mathrm{V}}_{\mathrm{D}\mathrm{S}}^{2\mathrm{n}\mathrm{d}}$) and material-dependent constants. Figure 8 shows the calculated maximum electric field at V_DS = 60 V for different buffer layer doping and thickness values, together with the maximum field sustainable by silicon.

In this work, a buffer layer resistivity of 0.25 Ω·cm is selected, corresponding to a doping concentration of 2.2 × 10¹⁶ cm⁻³. Under these conditions, the minimum feasible buffer layer thickness is 0.75 µm and the maximum reduction in the electric field corresponds to a W_B $~$ 4 µm.

However, the BJT-injected current density during the transient may exceed J_C, meaning that the minimum buffer layer thickness for the selected doping is insufficient to prevent second breakdown. For this reason, a 2.5 µm buffer layer will be considered in this work.

The effect of a 0.25 Ω·cm buffer layer with 2.5 µm thickness on the VDMOS cell is shown in Figure 9a. The second breakdown voltage has increased from 37 V to 46 V for the same J_C due to the reduction in generated holes that allows the device to turn to the blocking state after the transient, as exposed in Section 2.

To assess the influence of the buffer layer on the power losses and peak temperature reached during a SEB event, a comparative electro-thermal simulation study was performed. Figure 9b shows the effect of the buffer layer on temperature and current transients following iron-ion impacts at the JFET region with V_DS = 60 V. The inclusion of the buffer layer leads to a reduction in the transient drain current (lowering its amplitude by a factor of two). However, this modification alone is not sufficient to prevent SEB. Regarding the temperature evolution, despite the halved current, the maximum temperature peak remains almost unchanged up to 2 × 10⁻⁸ s. The physical origin of this behavior is discussed in Section 6.

5. P-Well BOX Implant Effects on the VDMOS Structure

Numerous studies have addressed the suppression of the parasitic BJT activation in VDMOS devices through different strategies, including modifications of the P-body doping and geometry [12], the introduction of parallel P-type structures to redirect charge carriers away from the parasitic BJT [14], or the incorporation of regions with enhanced recombination rates [26]. Although effective, these approaches typically alter the original VDMOS electrical characteristics or require substantial process redesign.

In this work, a different approach is proposed based on the introduction of a BOX implant in the P-body region during the final fabrication steps of the VDMOS process, which, in contrast with other solutions, does not change the cell structure without affecting the electrical device characteristics, and could be included into the fabrication process without major changes. Due to the high diffusivity of dopants in silicon, any implantation performed earlier in the process would experience significant diffusion during subsequent thermal steps, preventing the formation of a high-concentration and well-confined BOX profile. For this reason, the BOX implant profile is implemented at a late stage of the process flow, immediately before the back-end phase.

Specifically, a boron BOX profile is formed by means of a double implantation through 50 nm of oxide using doses of 5 × 10¹⁵ cm⁻² at 200 keV and 3 × 10¹⁵ cm⁻² at 140 keV, resulting in a peak concentration of approximately 2.2 × 10²⁰ cm⁻³. The implantation is followed by a Rapid Thermal Annealing (RTA) step and is performed using the contact-level mask, thereby minimizing lateral diffusion and preserving the intended BOX profile.

Figure 10a shows the simulated P-body doping profile after the introduction of the BOX implant, together with the resulting reduction in local resistivity. Because the resistivity decreases by several orders of magnitude, the BOX-implanted region contributes negligibly to the total P-body resistance compared with the surrounding unimplanted areas. Since the BOX implant is performed through the contact-level mask, as shown in Figure 10b, the minimum interlevel oxide thickness constrains the overlap of N⁺ and the BOX implant.

The reduction in P-body resistance directly impacts parasitic BJT activation. As shown in Figure 11, both the V_DS and drain current required to trigger BJT conduction increase, indicating a reduced susceptibility to latch-up.

Starting from the reference VDMOS cell and incorporating the BOX implant described in Figure 10a, the injected BJT current during the heavy-ion event is significantly reduced, leading to lower-power dissipated peak temperatures during the transient. Figure 12 compares the current and temperature transients for an iron-ion impact in the JFET region and V_DS 60 V, with and without the BOX implant. It should be noted that, even with the BOX implant, the device is not able to withstand the 120 MeV iron-heavy ion impact since the destructive high current state is still reached with hotspot temperatures higher than the silicon melting point (1680 K). However, The BOX implant reduces the transient current by approximately 15%, thereby lowering both the dissipated power and the peak temperature.

Since the BOX profile is located beneath the N⁺ source and entirely within the P-body, no significant modifications to the electrical characteristics of the device (breakdown voltage, R_ONxS resistance) are observed. The only noticeable effect is a slight shift in the junction position between the P-body and the source; however, according to the simulations, this shift does not produce any measurable impact on R_ON. Additionally, since the BOX profile is within the P-body, no major changes in device capacitances are expected.

6. Combined Effects of Buffer Layer and BOX Implant

This section presents the results obtained by simultaneously introducing the buffer layer and the BOX implant into the VDMOS structure, as illustrated in Figure 13a. The increase in SEB robustness can be qualitatively evaluated through the enhanced avalanche curve shown in Figure 13b, on which the onset current and voltage for second breakdown and BJT activation are increased: drain current necessary for destructive second breakdown is doubled and the minimum V_DS increased by $~30\mathrm{\%}$.

As discussed in Section 3.3.2, parasitic BJT activation and the resulting SEB behavior strongly depend on the ion impact location. Impacts occurring in the JFET region are more prone to BJT activation due to the higher hole current, whereas channel impacts typically lead to higher peak temperature despite weaker BJT triggering. Consequently, the effectiveness of both the buffer layer and the BOX implant must be evaluated separately for each impact position, expecting the BOX implant to be more effective for ion impacts at the JFET region than in the channel. Figure 14 shows the transient evolution of drain current and maximum device temperature following iron-ion impacts in the JFET (14a) and channel (14b) regions, both for the reference device and for the device incorporating the combined 2.5 µm buffer layer and BOX implant.

The introduction of the combined buffer layer + BOX solution leads to a significant decrease in transient current (total dissipated power) and peak temperature because the device no longer reaches the destructive high current point and the peak temperature remains below the silicon melting point for both JFET and channel impacts.

It should be noted that when including only the buffer layer to the device, the current decreases considerably, but the maximum temperature remains almost unchanged; this is explained by Figure 15, which shows the temperature distribution inside the device with and without the buffer layer. As can be seen, the hotspot at the center of the device remains almost equal, but without a buffer layer the area of high-power losses extends more widely across the N⁻/N⁺ junction, which implies that the high electric field is present over a larger zone and the total holes generated increase, making the device more prone to SEB and have a larger high-temperature affected area.

In this work, a buffer layer with a thickness of 2.5 µm has been employed. Increasing the buffer layer thickness would further enhance SEB robustness, as indicated by the trends shown in Figure 8. If the buffer layer alone can avoid the destructive high-current point (second breakdown) for the rated V_DS, the additional effect the BOX implant becomes less significant_. Even when the buffer layer dominates the SEB behavior under specific set of conditions (V_DS, heavy ion atomic mass), the presence of the BOX implant can extent the tolerance to heavier ions, thereby increasing the overall reliability of the device against SEB.

7. Discussion and Conclusions

The results presented in this work provide insight into the mechanisms governing SEB in silicon VDMOS power devices and into the effectiveness of device-level design strategies aimed at improving SEB robustness. Previous studies have shown that SEB is primarily driven by the activation of the parasitic bipolar junction transistor (BJT) and the subsequent evolution toward stable high-current states or thermally destructive transients, depending on the applied bias and the ion-induced charge deposition. The present electro-thermal simulations are consistent with these observations, confirming the central role of drain-source voltage, impact location, and temperature in defining the outcome of heavy-ion events.

The introduction of a buffer layer between the epitaxial layer and the substrate has been widely reported as an effective means to increase the second breakdown voltage and to mitigate SEB by suppressing stable high-current operating points. The results obtained in this work corroborate these findings, showing that the buffer layer limits the electric field peak at the N⁻/N⁺ junction and prevents the device from entering a second breakdown regime under heavy-ion irradiation. However, the simulations also indicate that electrical stabilization alone does not fully eliminate the risk of thermally driven failure, particularly for ion impacts that lead to high localized power dissipation.

Strategies based on modifying the P-body region have previously been proposed to reduce parasitic BJT activation by altering hole transport or recombination. In line with these approaches, the BOX implant investigated in this study increases effective P-body conductivity, thereby raising the hole current threshold required to trigger BJT conduction. The simulated results confirm that this modification reduces the injected BJT current and lowers the resulting temperature rise, while preserving the static electrical characteristics of the device. Nevertheless, when applied alone, the BOX implant does not provide sufficient protection against studied heavy-ion events, especially for channel impacts where thermal effects dominate.

The combined implementation of the buffer layer and the BOX implant addresses both electrical and thermal aspects of SEB. By preventing stable high-current states and simultaneously limiting parasitic BJT activation, the proposed solution achieves a more pronounced reduction in peak temperature than either modification applied independently. The remaining sensitivity to ion impact location, particularly in the channel region, is consistent with previous reports highlighting the importance of initial current peaks and localized heating in SEB transients.

Overall, the results of this work are in agreement with existing literature on SEB mitigation while extending it by demonstrating that a combination of buffer layer engineering and localized P-body resistance reduction can enhance SEB robustness without degrading key electrical parameters. This approach provides a viable alternative to excessive voltage derating and can be integrated into standard VDMOS fabrication flows without significant increase in cost or complexity, offering practical benefits for radiation-tolerant power device design over a wide range of VDMOS.

Future work will focus on evaluating the feasibility of incorporating the proposed BOX implant via the fabrication of prototype devices. Their electrical characterization under radiation environments will also be pursued in order to validate simulation results and further assess the effectiveness of the proposed mitigation strategies.