Accurate and Efficient Process Modeling and Inverse Optimization for Trench Metal Oxide Semiconductor Field Effect Transistors: A Machine Learning Proxy Approach

Abstract

This study proposes a novel framework integrating long short-term memory (LSTM) networks with Bayesian optimization (BO) to address process–device co-optimization challenges in trench-gate metal–oxide–semiconductor field-effect transistor (MOSFET) manufacturing. Conventional TCAD simulations, while accurate, suffer from computational inefficiency in high-dimensional parameter spaces. To overcome this, an LSTM-based TCAD proxy model is developed, leveraging hierarchical temporal dependencies to predict electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to physical simulations. The model, validated on both N-type and P-type 20 V trench MOS devices, outperforms conventional RNN and GRU architectures, reducing average relative errors by 1.78% through its gated memory mechanism. A BO-driven inverse optimization methodology is further introduced to navigate trade-offs between conflicting objectives (e.g., minimizing on-resistance while maximizing breakdown voltage), achieving recipe predictions with a maximum deviation of 8.3% from experimental data. Validation via TCAD-simulated extrapolation tests and SEM metrology confirms the framework’s robustness under extended operating ranges (e.g., 0–40 V drain voltage) and dimensional tolerances within industrial specifications. The proposed approach establishes a scalable, data-driven paradigm for semiconductor manufacturing, effectively bridging TCAD simulations with production realities while minimizing empirical trial-and-error iterations.

1. Introduction

Trench-gate metal–oxide–semiconductor field-effect transistors (TG-MOSFETs) have emerged as pivotal components in modern power electronics, driving advancements in renewable energy systems, electric vehicles, and high-efficiency power converters [1,2]. Their vertical trench architecture offers significant advantages over planar designs. These include reduced specific on-resistance (Ron) and enhanced switching efficiency, which are critical for high-frequency operations [3,4]. However, conventional trench MOSFETs are constrained by intrinsic limitations such as high reverse recovery charge (Qrr) and switching losses associated with their body diode, which degrade performance in fast-switching applications [5,6]. To address these challenges, recent innovations have focused on integrating Schottky barrier diodes (SBDs) into trench structures, creating hybrid architectures like the SBD-TG-NMOS which aim to bypass parasitic effects and improve conduction efficiency [7,8]. Despite these advancements, optimizing the fabrication process—spanning etch uniformity, doping gradients, and thermal management—remains a multi-dimensional challenge, particularly for balancing conflicting objectives such as breakdown voltage (BV) and Ron [9,10].

Traditional technology computer-aided design (TCAD) simulations have been widely adopted to predict device performance by solving physical equations governing carrier transport and electrostatics [11,12,13]. However, their computational inefficiency becomes prohibitive in high-dimensional parameter spaces, such as those involving multi-process variables (e.g., ion-implantation dose, gate oxide thickness, and annealing time) [14,15,16]. This limitation hinders iterative design exploration and real-time process calibration, both of which are essential for industrial-scale manufacturing. Machine learning (ML) approaches [17,18], particularly recurrent neural networks (RNNs), have shown promise in modeling sequential fabrication steps by leveraging temporal dependencies in process data [19,20,21]. Yet, conventional RNNs struggle with long-term dependency capture due to vanishing gradients and fixed memory states, limiting their applicability to complex multi-step semiconductor processes [22]. Long short-term memory (LSTM) networks, with their gated architecture, overcome these limitations by adaptively retaining critical temporal information across extended sequences, making them suitable for modeling nonlinear process–device relationships [23,24,25]. Despite their potential, the application of LSTMs to trench MOSFET process optimization, particularly for co-optimizing BV and Ron, remains underexplored.

Recent advances in Bayesian optimization (BO) have demonstrated its efficacy in navigating high-dimensional design spaces, especially for multi-objective problems common in semiconductor manufacturing [26,27]. BO’s probabilistic framework, combined with Gaussian process regression, enables efficient exploration of trade-offs between conflicting objectives, such as maximizing BV while minimizing Ron. However, integrating BO with LSTM-based surrogate models to bridge TCAD simulations and fabrication realities has not been systematically investigated, particularly for N-type and P-type trench MOS devices with asymmetric doping profiles and carrier mobility effects. Existing studies often focus on isolated aspects of process optimization, neglecting the holistic interplay between sequential fabrication steps and terminal device performance [28]. This gap underscores the need for a unified framework capable of addressing both device types while maintaining alignment with industrial requirements.

To address these challenges, this study proposes a co-optimization framework combining LSTM-based TCAD proxy modeling with BO-driven inverse optimization. The LSTM model hierarchically encodes nonlinear relationships between sequential process parameters (e.g., trench depth, doping concentration) and electrical responses, while the BO methodology identifies optimal process recipes to balance BV–Ron trade-offs. Validated on 20 V N-type and P-type trench MOS devices, this framework bridges the divide between physical simulations and high-volume manufacturing, offering a scalable solution for rapid process adaptation.

The remainder of this paper is organized as follows: Section 2 details the structural design and TCAD-validated fabrication process flow of trench MOSFETs, emphasizing critical steps such as gate oxidation and ion implantation. Section 3 introduces the LSTM proxy model architecture and its integration with BO for multi-objective optimization. Section 4 validates the framework through TCAD simulations and experimental metrology. Section 5 summarizes the conclusions of this study.

2. Process Simulation

2.1. Trench MOSFET

The trench-gate metal–oxide–semiconductor field-effect transistor (TG-MOSFET) has emerged as a critical component in high-frequency, low-voltage power electronics, particularly for applications such as DC–DC converters. However, conventional TG-MOSFETs are often limited by high reverse recovery charge and switching losses associated with their intrinsic body diode. To address these challenges, a novel trench-gate NMOS device integrated with a Schottky barrier diode (SBD), termed the SBD-TG-NMOS, is proposed. This architecture combines the advantages of trench-gate MOSFETs and Schottky diodes, achieving enhanced electrical performance while retaining robust breakdown characteristics [6,8,29].

The SBD-TG-NMOS features a vertical trench-gate configuration, as depicted in Figure 1. Reduced conduction losses: The integrated SBD provides a low-resistance path during forward conduction, bypassing the MOSFET’s body diode. A key innovation lies in the replacement of the conventional ohmic source contact with a Schottky barrier interface, enabling the integration of a built-in SBD parallel to the MOSFET’s body diode. The trench gate is embedded within a lightly doped epitaxial layer, with a p-well/n-well region defining the channel. The Schottky contact is strategically positioned adjacent to the trench gate, facilitating direct interaction with the drift region during operation. This design ensures efficient current conduction through the SBD during reverse recovery, minimizing parasitic effects.

As can be seen from Figure 2, the cross-sectional scanning electron microscope (SEM) image reveals the structural details of a trench MOSFET. Figure 2 illustrates the structural features of the device, with critical dimensions marked for characterization including the gate oxide layer and trench depth. The etch depths at two strategic locations of the trench MOS structure were measured as 1.045 μm and 0.337 μm, respectively.

2.2. Device Process Flow

Figure 3 presents a cross-sectional schematic of the TCAD-validated trench MOSFET fabrication process. The manufacturing sequence proceeds as follows: (1) A high-quality semiconductor layer is epitaxially grown on the substrate (Epi Start). (2) Trench regions are defined through hard mask etching (Hardmask Etch), followed by deep trench etching to form vertical structures (Trench Etch). (3) A gate dielectric layer is thermally grown within the trenches (Gate Oxidation). (4) Polysilicon is deposited as gate electrode material (Poly Deposition) and planarized via chemical mechanical polishing (Poly CMP). (5) Sacrificial oxidation (Sac Oxidation) is performed to optimize interface properties. (6) Body region doping is achieved through ion-implantation and annealing processes (Body Implantation/Anneal), followed by source region optimization using analogous techniques (Source Implantation/Anneal). (7) Interlayer dielectric formation is completed with undoped silicate glass deposition (USG Deposition). (8) Metal interconnects are patterned through contact etching (Contact Etch). This process flow integrates advanced etching precision, doping control, and interface optimization techniques, ensuring superior gate controllability and device reliability as validated by TCAD simulations.

Fifteen critical process parameters were systematically identified from the manufacturing sequence, encompassing etch rates and gas flow parameters in patterning steps, temperature–time profiles during oxidation, dose–energy combinations in ion implantation, and thermal budgets in annealing protocols. These variables were selected as the focus of investigation. A full-factorial design of experiments (DOE) framework was implemented to account for all parameter interactions, followed by the generation of statistically representative sample sets for TCAD simulations. This systematic methodology enables comprehensive process–response mapping while maintaining computational efficiency in predictive modeling.

The TCAD process simulation model was calibrated against experimental process conditions and electrical characteristics, achieving strong agreement between simulation and measurement (deviation < 3%).

Figure 4 presents schematic diagrams of two distinct trench MOSFET device architectures. Three TCAD-based trench MOSFET variants (N20 V, N30 V, and P20 V) were constructed for simulation and validation, with identical critical dimensions maintained across all configurations. Key electrical parameters, including breakdown voltage (BV) and resistance (Ron), were found to be predominantly governed by ion-implantation and annealing processes. This correlation enables process recipe modifications during manufacturing to be precisely mirrored in TCAD simulations. The dimensional uniformity allows systematic acquisition of experimental and production data, significantly enhancing model verification accuracy through controlled variable isolation.

3. Methodology

3.1. Machine Learning Methodology

Recurrent neural networks (RNNs) represent a class of artificial neural networks specifically designed to process sequential data by leveraging temporal dependencies. Unlike feedforward networks, RNNs incorporate cyclic connections that enable the retention of historical information through hidden states. This architecture allows the network to map input sequences {$x_1,x_2,\dots ,x_T\}$ to output sequences {$y_1,y_2,\dots ,y_T\}$, making them inherently suitable for tasks such as time-series prediction, natural language processing, and dynamic system modeling [19].

Mathematically, the hidden state $h_t$ at time step $t$ is updated recursively as follows:

$$h_t=\sigma (W_{xh}^T·x_t+W_{hh}^T·h_{t-1}+b_h)$$

(1)

where $W_{xh}$ and $W_{hh}$ are weight matrices for input and recurrent connections, $b_h$ is a bias term, and σ(⋅) denotes an activation function (e.g., tanh or ReLU). The output $y_t$ is derived from the following hidden state:

$$y_t=W_{hy}^T·h_t+b_y$$

(2)

While RNNs excel at capturing short-term dependencies, their performance degrades for sequences with long-range temporal correlations due to the vanishing/exploding gradient problem. During backpropagation through time (BPTT), gradients used to update network weights diminish or grow exponentially as they propagate across multiple time steps. This instability limits the network’s ability to learn relationships spanning distant time intervals. Additionally, the fixed-size hidden state imposes constraints on memory capacity, further restricting modeling fidelity in applications requiring persistent context retention. As shown in Figure 5, the chain structure diagram of RNNs is given.

To address the limitations of conventional RNNs, long short-term memory (LSTM) networks introduce a gated mechanism that explicitly manages information flow through persistent and transient memory states. This architecture, first proposed by Hochreiter and Schmidhuber [30], enables adaptive retention and forgetting of contextual information over extended sequences.

An LSTM unit comprises three critical components, as shown in Figure 6.

1.

Input gate ($i_t)$ and candidate state ($g_t$): Control the integration of new information into $C_t$ with the following:

$$InputGat\mathrm{e:} i_t=\sigma (W_{xi}^T·x_t+W_{hi}^T·h_{t-1}+b_i)$$

(3)

$$Input Modilation Gat\mathrm{e:} g_t=tanh(W_{xg}^T·x_t+W_{hg}^T·h_{t-1}+b_g)$$

(4)

2.

Forget gate $\left(f_t\right)$: Regulates the retention of the persistent memory state $C_{t-1}$ using the following:

$$Forget Gat\mathrm{e:} f_t=\sigma (W_{xf}^T·x_t+W_{hf}^T·h_{t-1}+b_f)$$

(5)

3.

Output gate ($o_t$): Modulates the exposure of $C_t$ to the transient state $h_t$ through the following:

$$Output Gat\mathrm{e:} o_t=\sigma (W_{xo}^T·x_t+W_{ho}^T·h_{t-1}+b_o)$$

(6)

4.

The persistent memory state $C_t$ is updated via a weighted combination of historical and novel inputs, which can be depicted as follows:

$$C_t=f_t\otimes C_{t-1}+i_t\otimes g_t$$

(7)

5.

Where $\otimes$ denotes element-wise multiplication. The transient state $h_t$, which serves as the network’s output, is computed as follows:

$$y_t=h_t=o_t\otimes tanh\left(C_t\right)$$

(8)

It has the following advantages over RNNs:

• Gradient stability: The additive nature of $C_t$ mitigates gradient dissipation/explosion, enabling stable training over long sequences.
• Contextual selectivity: Gating mechanisms allow the network to prioritize relevant temporal features while suppressing noise.
• Black-box modeling: LSTMs eliminate the need for explicit physical equations, making them ideal for modeling complex nonlinear systems like GaN HEMTs.

By decoupling memory retention from iterative updates, LSTMs achieve superior performance in applications requiring both short-term responsiveness and long-term dependency capture, as demonstrated in subsequent sections. Figure 6 shows a basic unit structure diagram of LSTM.

LSTM Technique-Based Process Model

In the TCAD simulation, the electrical parameters of some devices are solved through iterative generation, exhibiting characteristics of non-uniform sampling. Despite the non-uniform sampling characteristics introduced by iterative parameter solving, fundamental similarities persist in the electrical curves. These recurring patterns originate from the unified physical mechanisms (e.g., carrier transport equations) underlying all simulated devices. Using an encoder–decoder effectively addresses this issue while ensuring the consistency of the data input into the model. Multilayer perception (MLP) network architecture is employed as the core of the encoder–decoder, like Figure 7. The encoder–decoder framework acts as a “smart compressor”:

Encoder: Identifies 5–10 fundamental curve templates from raw data (e.g., exponential saturation curves for Ron).

Decoder: Reconstructs full parameter sets using these templates + process condition inputs.

The fabrication of trench MOSFETs involves sequential process steps with inherent temporal interdependencies, where outputs from prior steps (e.g., etch profiles, oxide thickness) directly define inputs for subsequent stages. To address this sequential complexity, an LSTM network is proposed as a TCAD proxy model. Unlike conventional RNNs, LSTM leverages gate-controlled information flow (input, forget, and output gates) to selectively retain long-range dependencies, effectively mitigating gradient vanishing issues common in multi-step process simulations.

A total of 1768 training data are generated via TCAD simulations calibrated with experimental process recipes and electrical measurements. A design of experiments (DOE) systematically samples critical parameters (e.g., trench depth, gate oxide thickness) across their feasible ranges, ensuring coverage of nonlinear interactions. Electrical test data, including transfer characteristics (Id-Vg), output curves (Id-Vd), and breakdown voltages, are collected under varying bias conditions.

The LSTM network adopts a multi-layer structure, like Figure 8, to hierarchically capture process–device relationships. Each LSTM cell ingests time-step inputs comprising recipe parameters (e.g., reactive gas flow, etch angle) and metrology data (e.g., post-etch critical dimensions). The hidden states propagate sequentially across process steps, emulating the cascading nature of fabrication. For instance, in trench etching simulations, inputs include after-develop inspection (ADI) measurements and recipe variables, while outputs predict after-etch inspection (AEI) profiles. For multi-dimensional parameter spaces inherent to complex processes like ion-implantation, a stacked LSTM architecture with three hidden layers (128/256/128 units each) is deployed to enhance nonlinear mapping capabilities.

The LSTM architecture (3 layers with 128/256/128 units) was optimized through iterative hyperparameter tuning to balance accuracy and computational efficiency. Configurations within common ranges (64–512 units, 2–3 layers) were systematically explored, prioritizing lightweight structures while retaining nonlinear mapping capabilities for high-dimensional process parameters. The final design was selected based on empirical validation, and unit reductions in layers minimized redundancy without compromising fidelity. This approach ensured robustness and alignment with industrial scalability requirements.

The proposed LSTM-based framework is fundamentally constrained by the practical realities of semiconductor manufacturing, where only recipe parameters (e.g., gas flow rates, temperature ramps, plasma power) can be actively monitored and adjusted during processing, whilst the final device characteristics are solely accessible through post-fabrication metrology data (e.g., sheet resistance, threshold voltage, leakage current). This data-driven paradigm necessitates a modeling approach that rigorously maps sequential recipe variations to terminal electrical responses without intermediate physical inspections—a constraint intrinsic to high-volume production environments. Crucially, both input vectors (process recipes) and output responses (electrical metrics) are restricted to numerical representations of controlled variables and measured outcomes, respectively, with process optimization objectives formulated as multivariate regression problems against device specification targets.

The model is implemented in TensorFlow using a Nadam optimizer and means squared error (MSE) loss function. Training converges iteratively, with early stopping triggered when validation loss plateaus—typically within 200 epochs. To enhance robustness, dropout layers (rate = 0.2) are inserted between LSTM layers, regularizing the network against overfitting. Figure 9 shows the training loss function curve.

The sequential chained architecture of recurrent networks demonstrates inherent compatibility with semiconductor manufacturing processes. Among numerous architectural variants (RNN, LSTM, GRU, and Bi-RNN), three predominant frameworks were systematically compared using identical N20V device specifications. Architectural configurations were optimized through layer-wise adjustments to maintain equivalent trainable parameters.

As detailed in

Table 1. Performances comparison of different models.

Model	Total Layers (Equivalent Parameters)	Gating Complexity	Parameters per Layer	Long-Term Dependency Capture	Extraction Time (s)	Average Relative Error (%)
RNN	16	None	Lowest	Weak	57.67	2.870
GRU	13	Moderate (2 gates)	Lower	Moderate	68.92	1.323
LSTM	11	High (3 gates)	Higher	Strong	78.26	1.092

, the standard RNN architecture, despite its simplest gating mechanism (no explicit gates) and fastest extraction time (57.67 s), exhibits limited capability in long-term dependency modeling, resulting in the highest average relative error (2.870%). The LSTM architecture exhibited superior modeling accuracy despite requiring 14% longer computational time per epoch compared to GRU counterparts. The GRU variant introduces moderate gating complexity (update and reset gates) with 13 equivalent layers, achieving improved error reduction (1.323%) at the cost of marginally increased computational overhead (68.92 s). Notably, the LSTM attains the highest parameter efficiency (11 equivalent layers) while maintaining robust long-term dependency capture.

This performance advantage led to the selection of LSTM as the surrogate model, with its gated memory mechanism proving particularly effective in capturing nonlinear process–response relationships inherent to ion implantation and thermal annealing dynamics.

3.2. Multi-Objective Optimization

Based on the LSTM-based forward process model established in the previous section, a Bayesian optimization-driven reverse optimization methodology is proposed in this study to enhance the figure of merit (FoM) of trench MOS devices. This systematic approach enables timely calibration of process recipes during actual manufacturing operations. Figure 10 shows the workflow diagram based on Bayesian multi-objective optimization.

Bayesian optimization (BO) is a probabilistic framework designed for the global optimization of expensive black-box functions [31]. It leverages Gaussian process (GP) regression to model the unknown objective function $f\left(x\right)$, where x represents the input parameters. A GP prior is defined by a mean function $m\left(x\right)$ and a covariance kernel $K(x,x’)$, capturing the spatial correlation between parameter configurations. For robustness in modeling non-smooth or heteroscedastic functions, the Matern 5/2 kernel is often preferred over the squared exponential kernel due to its adaptability to varying smoothness assumptions.

The acquisition function, such as expected improvement (EI), guides the iterative selection of subsequent evaluation points by balancing exploration and exploitation. EI quantifies the potential gain over the current best observation $f\left(x^{+}\right)$ through the following:

$$a_{EI}\left(x\right)=\mathbb{E}[\mathrm{m}\mathrm{a}\mathrm{x}(f\left(x^{+}\right)-f\left(x\right),0\left)\right]$$

(9)

which is analytically tractable under the GP posterior. To account for hyperparameter uncertainty, a fully Bayesian treatment integrates over kernel parameters via Markov chain Monte Carlo (MCMC) sampling, ensuring robustness against model misspecification.

In power device optimization, conflicting objectives—such as maximizing breakdown voltage (BV) while minimizing specific on-resistance (R_on)—necessitate a Pareto-optimal framework. The adaptive weighted sum (AWS) method transforms multi-objective problems into scalarized formulations by dynamically adjusting weights to uniformly sample the Pareto front. For the FoM (as Formula (10)), the utility function is defined as follows:

$$Fom={\displaystyle \frac{{BV}^2}{R_{on}}}$$

(10)

$$U\left(x\right)=\lambda ·{\displaystyle \frac{{BV}^2}{{BV}_{max}}}+(1-\lambda )·{\displaystyle \frac{R_{on,min}}{R_{on}}}$$

(11)

where λ ∈ [0, 1] governs the trade-off between objectives, and normalization ensures dimensionless comparability. AWS refines weight distributions iteratively, prioritizing regions with sparse Pareto solutions to enhance coverage and resolution.

Inverse optimization bridges the gap between target performance metrics and feasible input parameters. Given a pre-trained LSTM model $\mathcal{M}$ that predicts BV and R_on from process variables (e.g., trench depth, doping concentration), the inverse problem seeks parameters x^* that minimize the deviation from target FoM^*, which can be shown as follows:

$$x^{*}=\arg min\left|\right|\mathcal{M}\left(x\right)-{FoM}^{*}\left|\right|$$

(12)

BO accelerates this search by constructing a surrogate model of the inverse response surface, enabling efficient exploration of high-dimensional parameter spaces.

4. Results and Discussion

4.1. Model Validation

The predictive capability of the proposed LSTM-based TCAD proxy model was rigorously validated through comprehensive comparisons with conventional TCAD simulations across key electrical parameters of trench MOSFET devices. Figure 11, Figure 12, Figure 13 and Figure 14 illustrate the alignment between LSTM predictions and TCAD-generated data for transfer characteristics, output curves, breakdown voltage, and body diode behavior.

For transfer characteristics (Figure 11), the LSTM model successfully captures the Vth and subthreshold swing (SS) across both NMOS and PMOS configurations, with deviations limited to 0.95% and 1.1%, respectively. This accuracy is attributed to the model’s ability to hierarchically encode nonlinear relationships between process parameters (e.g., gate oxide thickness, doping profiles) and terminal electrical responses. The output characteristics (Figure 12) further demonstrate the model’s fidelity in simulating channel conductance and saturation current, achieving errors below 1.5% even under strong gate voltage nonlinearity.

Breakdown voltage (BV) analysis (Figure 13) reveals that the LSTM framework accurately replicates avalanche breakdown phenomena, with discrepancies of 1.6% (NMOS) and 2.3% (PMOS) compared to TCAD. Body diode characterization (Figure 14) confirms the model’s capacity to predict forward voltage drops (VF) with <1% error, though slight underestimations in PMOS devices suggest opportunities for refining recombination rate calibrations in future iterations.

All the above test cases demonstrate the effectiveness of the LSTM surrogate model in establishing the trench MOS device process flow, ensuring both the efficiency of the model and achieving industrial-level prediction accuracy.

The model’s generalization capability was further validated through extrapolation tests beyond the nominal operating ranges. As shown in Figure 15, transfer characteristics of the N30V device were predicted over an extended gate voltage range (0–2 V) using a model trained exclusively on N20 V device data. The LSTM framework maintains predictive consistency, with an 8.5% deviation in Vth. This capability stems from the LSTM’s gated memory architecture, which selectively retains long-term dependencies in process–device relationships, thereby mitigating error accumulation in multi-step simulations.

Similarly, breakdown voltage extrapolation (Figure 16) demonstrates robust performance under high-field conditions (0–40 V). The model achieves a 6.2% deviation in critical BV parameters, validating its ability to capture nonlinear leakage current dynamics without explicit physical formulations. Such extrapolation accuracy is critical for industrial applications as process variations often necessitate predictions beyond experimentally validated ranges.

4.2. Inverse Optimization

The inverse optimization capability of the proposed framework was rigorously validated through Bayesian optimization (BO), demonstrating superior performance in navigating high-dimensional process parameter spaces while avoiding local optima. As illustrated in Figure 17, the inverse optimization verification was performed on a single N20V device. To improve the accuracy of inverse optimization and modeling precision, the data for the established forward LSTM fitting model exclusively included all process parameters of N20 V devices, with constant values from fixed process variables removed. The retained 15 key parameters were used to optimize and refine the model. The reduced number of modeling parameters alleviates the search difficulty of Bayesian inverse optimization to some extent. As shown in Figure 17, the definitions of the 15 corresponding process parameters are clearly labeled. The BO-driven parameter predictions exhibit a maximum deviation of 8.3% from actual process recipes across critical variables such as ion-implantation dose, trench etch angle, and gate oxidation time. This precision is attributed to BO’s Gaussian process (GP) regression framework, which probabilistically models the nonlinear relationships between process parameters and device performance metrics (e.g., BV, Ron), enabling efficient exploration of the design space.

To enhance the interpretability of the LSTM model, SHAP analysis was performed to quantify the impact of individual process parameters on the breakdown voltage (BV). As illustrated in the SHAP value summary (as shown in Figure 18), parameters such as trench depth (+2.11), trench angle (+1.52), and gate OX temp (+1.83) exhibited the strongest positive correlations with BV. Conversely, plus dose (−0.32), plus energy (−0.21), and body dose (−0.33) showed minor negative influences, likely due to their indirect effects on carrier mobility and junction leakage.

Notably, trench depth dominated the BV response, aligning with TCAD-simulated electric field distributions where deeper trenches reduced peak field crowding. The hierarchical dependencies revealed by SHAP values further validated the LSTM’s alignment with physical principles. This analysis bridges the “black-box” nature of LSTM with actionable process insights, enabling targeted optimization of critical parameters.

The ion-implantation process recipe parameters obtained through Bayesian backward optimization were used in combination to re-simulate this step in TCAD. As shown in Figure 19, the implanted ions gradually penetrate deeper into the substrate with the increase in annealing time. Furthermore, after annealing, the resulting source maintains a high level of consistency with the original TCAD simulation results.

After evaluating the cost and difficulty of obtaining data in the actual production process, we selected the SAC OX step to demonstrate the performance of Bayesian backward optimization. The SEM images provide a detailed view of the trench dimension changes. The robustness of the methodology was further validated through SEM metrology (Figure 20). The dimensional variation in trenches produced by the wet etching process compared to standard processing parameters remains within acceptable tolerance limits, demonstrating the industrial viability of this methodology.

The validation results of the LSTM-based proxy model and Bayesian optimization framework collectively demonstrate a synergistic approach to trench MOSFET process–device co-optimization. The LSTM model’s high-fidelity predictions provide a computationally efficient surrogate for TCAD simulations, enabling rapid exploration of high-dimensional parameter spaces. This accuracy is critical for BO-driven inverse optimization, where the probabilistic Gaussian process regression leverages the LSTM’s outputs to navigate trade-offs between conflicting objectives with minimal experimental iterations.

5. Conclusions

This study establishes a robust LSTM-Bayesian optimization framework for trench MOSFET process–device co-optimization. The LSTM-based TCAD proxy model achieves industrial-level accuracy, predicting key electrical parameters (e.g., breakdown voltage, threshold voltage) with deviations below 3.5% compared to conventional simulations. Its hierarchical architecture effectively captures nonlinear process–device relationships, outperforming RNN and GRU counterparts by reducing average relative errors by 1.78%. Extrapolation tests validate its generalization capability, with deviations of 8.5% (Vth) and 6.2% (BV) under extended operating ranges highlighting its adaptability to process variations.

Bayesian optimization enables efficient inverse design, identifying optimal process recipes with a maximum 8.3% deviation from actual parameters while balancing conflicting objectives via Pareto optimal trade-offs. Experimental validation through SEM metrology confirms dimensional tolerances within industrial specifications, underscoring practical viability. Future work should refine PMOS recombination rate calibrations and explore hybrid architectures to mitigate computational overhead. This framework bridges TCAD simulations and manufacturing, offering a scalable, data-driven paradigm for next-generation power electronics development.